AM263Px MCU+ SDK  09.01.00
Release Notes 09.01.00

Also refer to individual module pages for more details on each feature, unsupported features, important usage guidelines.
The examples will show usage of SW modules and APIs on a specific CPU instance and OS combination.
Unless explicitly noted otherwise, the SW modules would work in both FreeRTOS and no-RTOS environment.
Unless explicitly noted otherwise, the SW modules would work on any of the R5F's present on the SOC.
Current PMIC support in SDK is bare minimum meant to power up the modules and should not be used beyond this including safety use-case etc
This SDK release supports AM263Px-LP board (ZCZ_C) package with limited validation. Please refer to test report for details
CSP 1.2.6 or beyond needs to be used for XIP load/run from CCS. Refer Update CSP for installation steps.

Key New features

Modules Not tested/supported in this release

  • Ethernet phy (ETHPHY) board driver

Device and Validation Information

SOC Supported CPUs EVM Host PC
AM263Px R5F AM263Px ControlCard E2 Rev (referred to as am263Px-cc in code).
Windows 10 64b or Ubuntu 18.04 64b
AM263Px R5F AM263Px LaunchPad (referred to as am263Px-lp in code).
Windows 10 64b or Ubuntu 18.04 64b

Dependent Tools and Compiler Information

Tools Supported CPUs Version
Code Composer Studio R5F 12.5.0
SysConfig R5F 1.18.0, build 3266
FreeRTOS Kernel R5F 10.4.3
Mbed-TLS R5F mbedtls-2.13.1

Key Features

Experimental Features

Features listed below are early versions and should be considered as "experimental".
Users can evaluate the feature, however the feature is not fully tested at TI side.
TI would not support these feature on public e2e.
Experimental features will be enabled with limited examples and SW modules.
Feature Module
GUI for UART Uniflash Tool Bootloader

OS Kernel

OS Supported CPUs SysConfig Support Key features tested Key features not tested / NOT supported
FreeRTOS Kernel R5F NA Task, Task notification, interrupts, semaphores, mutexs, timers Task load measurement using FreeRTOS run time statistics APIs. Limited support for ROV features.
FreeRTOS POSIX R5F NA pthread, mqueue, semaphore, clock -
NO RTOS R5F NA See Driver Porting Layer (DPL) below -

Driver Porting Layer (DPL)

Module Supported CPUs SysConfig Support OS support Key features tested Key features not tested / NOT supported
Cache R5F YES FreeRTOS, NORTOS Cache write back, invalidate, enable/disable -
Clock R5F YES FreeRTOS, NORTOS Tick timer at user specified resolution, timeouts and delays -
CpuId R5F NA FreeRTOS, NORTOS Verify Core ID and Cluster ID that application is currently running on -
CycleCounter R5F NA FreeRTOS, NORTOS Measure CPU cycles using CPU specific internal counters -
Debug R5F YES FreeRTOS, NORTOS Logging and assert to any combo of: UART, CCS, shared memory -
Heap R5F NA FreeRTOS, NORTOS Create arbitrary heaps in user defined memory segments -
Hwi R5F YES FreeRTOS, NORTOS Interrupt register, enable/disable/restore, Interrupt prioritization -
MPU R5F YES FreeRTOS, NORTOS Setup MPU and control access to address space -
Semaphore R5F NA FreeRTOS, NORTOS Binary, Counting Semaphore, recursive mutexs with timeout -
Task R5F NA FreeRTOS Create, delete tasks -
Timer R5F YES FreeRTOS, NORTOS Configure arbitrary timers -

Secondary Bootloader (SBL)

Module Supported CPUs SysConfig Support OS support Key features tested Key features not tested / NOT supported
Bootloader R5FSS0-0 YES NORTOS Boot modes: OSPI, UART. All R5F's. RPRC, multi-core image format Force Dual Core Mode

SOC Device Drivers

Peripheral Supported CPUs SysConfig Support DMA Supported Key features tested Key features not tested / NOT supported
ADC R5F YES Yes. Example: adc_soc_continuous_dma Single software triggered conversion, Multiple ADC trigger using PWM, Result read using DMA, EPWM trip through PPB limit, PPB limits, PPB offsets, burst mode oversampling, differential mode, Offset, EPWM triggered conversion PPB Aggregrator features, trigger repeaters, external channel selection
Bootloader R5F YES Yes. DMA enabled for SBL OSPI Boot modes: OSPI, UART. All R5F's -
CMPSS R5F YES NA Asynchronous PWM trip -
CPSW R5F YES No MAC loopback, PHY loopback, LWIP: Getting IP, Ping, Iperf, Layer 2 MAC, Layer 2 PTP Timestamping and Ethernet CPSW Switch support -
DAC R5F YES Yes. Example: dac_sine_dma Constant voltage, Square wave generation, Sine wave generation with and without DMA, Ramp wave generation, Random Voltage generation -
ECAP R5F YES No ECAP APWM mode, PWM capture -
EDMA R5F YES NA DMA transfer using interrupt and polling mode, QDMA Transfer, Channel Chaining, PaRAM Linking -
EPWM R5F YES Yes. Example: epwm_dma PWM outputs A and B in up-down count mode, Trip zone, Update PWM using EDMA, Valley switching, High resolution time period adjustment, type5 feature -
EQEP R5F YES NA Speed and Position measurement. Frequency Measurement -
FSI R5F YES Yes. Example: fsi_loopback_dma RX, TX, polling, interrupt mode, Dma, single lane loopback. - FSI Spi Mode
GPIO R5F YES NA Output, Input and Interrupt functionality -
I2C R5F YES No Controller mode, basic read/write -
IPC Notify R5F YES NA Mailbox functionality, IPC between RTOS/NORTOS CPUs M4F core
IPC Rpmsg R5F YES NA RPMessage protocol based IPC M4F core
MCAN R5F YES No RX, TX, interrupt and polling mode, Corrupt Message Transmission Prevention, Error Passive state, Bus Off State, Bus Monitoring Mode -
MCSPI R5F YES Yes. Example: mcspi_loopback_dma Controller/Peripheral mode, basic read/write, polling, interrupt and DMA mode -
MDIO R5F YES NA Register read/write, link status and link interrupt enable API -
MMCSD R5F YES NA MMCSD 4bit, Raw read/write file IO, eMMC
PINMUX R5F YES NA Tested with multiple peripheral pinmuxes -
PMU R5F NO NA Tested various PMU events Counter overflow detection is not enabled
OptiFlash R5F Yes NA FLC, RL2, RAT functionality, XIP with RL2 enabled OptiShare
OSPI R5F YES Yes. Example: ospi_flash_dma Read direct, Write indirect, Read/Write commands, DMA for read -
RTI R5F YES No Counter read, timebase selection, comparator setup for Interrupt, DMA requests Capture feature, fast enabling/disabling of events not tested
RESOLVER R5F YES No Angle and Speed Calcution. input Band Pass Filter, Manual Phase Gain Correction and Manual Ideal Sample Selection Mode calculation Tuning
SDFM R5F YES No Filter data read from CPU, Filter data read with PWM sync -
SOC R5F YES NA Lock/unlock MMRs, clock enable, set Hz, Xbar configuration, SW Warm Reset, Address Translation -
SPINLOCK R5F NA NA Lock, unlock HW spinlock -
UART R5F YES Yes. Example: uart_echo_dma Basic read/write at baud rate 115200, polling, interrupt mode HW flow control not tested, DMA mode not supported
WATCHDOG R5F YES NA Reset mode, Interrupt mode -

Board Device Drivers

Peripheral Supported CPUs SysConfig Support Key features tested Key features not tested
EEPROM R5F YES Only compiled -
ETHPHY R5F YES Tested with ethercat_slave_beckhoff_ssc_demo example -


Module Supported CPUs SysConfig Support OS Support Key features tested Key features not tested
LwIP R5F YES FreeRTOS TCP/UDP IP networking stack with and without checksum offload enabled, TCP/UDP IP networking stack with server and client functionality, basic Socket APIs, netconn APIs and raw APIs, DHCP, ping, TCP iperf, scatter-gather, DSCP priority mapping Other LwIP features
Ethernet driver (ENET) R5F YES FreeRTOS Ethernet as port using CPSW, MAC loopback and PHY loopback, Layer 2 MAC, Packet Timestamping, interrupt pacing, Policer and Classifier RMII mode, CPSW EST, MDIO Manual Mode, CBS (IEEE 802.1Qav), Strapped PHY (Early Ethernet)

Safety Diagnostic Library

Module Supported CPUs SysConfig Support OS support Key features tested Key features not tested / NOT supported
MCRC R5F NA NORTOS Full CPU, Auto CPU Mode and Semi CPU Auto Mode -
DCC R5F NA NORTOS Single Shot and Continuous modes -
PBIST R5F NA NORTOS Memories supported by MSS PBIST controller. -
ESM R5F NA NORTOS Tested in combination with RTI, DCC -
RTI R5F NA NORTOS WINDOWSIZE_100_PERCENT, WINDOWSIZE_50_PERCENT ,Latency/Propagation timing error(early)(50% window),Latency/Propagation timing error(late)(50% window) -
CCM R5F NA NORTOS CCM Self Test Mode,Error Forcing Mode and Self Test Error Forcing Mode. -
R5F STC(LBIST), Static Register Read R5F NA NORTOS STC of R5F, R5F CPU Static Register Read -

Fixed Issues

ID Head Line Module Applicable Releases Applicable Devices Resolution/Comments
- - - - -

Known Issues

ID Head Line Module Reported in release Workaround
MCUSDK-11507 ENET: CPSW MAC port is stuck forever and dropping all the Rx/Tx packets with reception of corrupts preamble CPSW 09.00.01 None
MCUSDK-12312 ROM bootloader fails when booting from Macronix Flash on AM263Px-LP SBL 09.01.00 Use UART/CCS Boot
MCUSDK-12313 OSPI Phy Tuning not working on Macronix Flash on AM263Px-LP SBL 09.01.00 Use UART/CCS Boot
MCUSDK-12289 32 KB TCM is used in examples sysconfig MPU module, size should be 64 KB Common 09.01.00 Use 64KB TCM in user application
MCUSDK-12278 Sysconfig: Missing EPWMxSYNCPER configuration EPWM 09.01.00 Use HRPWM_setSyncPulseSource API to configure EPWMxSYNCPER
MCUSDK-12265 SDFM example failure on am263px-lp SDFM 09.01.00 None
MCUSDK-12264 EQEP position speed example failure on am263px-lp EQEP 09.01.00 None
MCUSDK-12263 ECAP APWM example failure on am263px-lp ECAP 09.01.00 None
MCUSDK-12262 EPWM deadband example failure EPWM 09.01.00 None
MCUSDK-12247 Syscfg: ouptutxbar generated code doesnt change the instance XBAR 09.01.00 Use XBAR driver API to configure the output xbar instance
MCUSDK-11675 INDAC write only works if MPU for flash is only configured as Strongly-ordered OSPI 09.01.00 None
MCUSDK-12340 RGMII1 clock is getting set in gel/CCS boot flow for am263px-lp Networking 09.01.00 Use UART boot mode


ID Head Line Module SDK Status
i2311 USART: Spurious DMA Interrupts UART Implemented
i2354 SDFM: Two Back-to-Back Writes to SDCPARMx Register Bit Fields CEVT1SEL, CEVT2SEL, and HZEN Within Three SD-Modulator Clock Cycles can Corrupt SDFM State Machine, Resulting in Spurious Comparator Events SDFM Open
i2345 CPSW: Ethernet Packet corruption occurs if CPDMA fetches a packet which spans across memory banks CPSW Implemented
i2350 McSPI data transfer using EDMA in 'ABSYNC' mode stops after 32 bits transfer McSPI Open
i2356 ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt Mode) is not Set ADC Implemented
i2324 No synchronizer present between GCM and GCD status signals Common Open
i2401 CPSW: Host Timestamps Cause CPSW Port to Lock up CPSW Open


ID Head Line Module Reported in release Workaround
- - - - -

Upgrade and Compatibility Information

Compiler Options

Module Affected API Change Additional Remarks
- - - -

SOC Device Drivers

Module Affected API Change Additional Remarks
Memory configurator SysConfig Remove array for memory region names User needs to delete the memory configurator entry and add the memory configuration again via SysConfig. A button to initialize the memory configuration to default is provided.


Module Affected API Change Additional Remarks
- - - -