Introduction

This file contains the data structures for accessing the DWC_usb3 core registers and DMA descriptor fields.

The application interfaces with the HS OTG core by reading from and writing to the Control and Status Register (CSR) space through the AHB Slave interface. These registers are 32 bits wide, and the addresses are 32-bit-block aligned. CSRs are classified as follows:

Core Global Registers
Device Global Registers
Device Endpoint Specific Registers

Go to the source code of this file.

Data Structures
struct	geventbuf_data_t

struct	dwc_usb3_core_global_regs_t

struct	dwc_usb3_dev_global_regs_t

struct	dwc_usb3_dev_ep_regs_t

struct	dwc_usb3_dma_desc_t
	DMA Descriptor structure. More...

Macros
#define	DWC_RMMICTL_MPHY_STATE_BITS 0x0e000000U

#define	DWC_RMMICTL_MPHY_STATE_SHIFT 25U

#define	DWC_MPHY_STATE_DISABLED 0U

#define	DWC_MPHY_STATE_HIBERN8 1U

#define	DWC_MPHY_STATE_SLEEP 2U

#define	DWC_MPHY_STATE_STALL 3U

#define	DWC_MPHY_STATE_PWM_BURST 4U

#define	DWC_MPHY_STATE_HS_BURST 5U

#define	DWC_MPHY_STATE_LINE_CFG 6U

#define	DWC_MPHY_STATE_LINE_RESET 7U

#define	DWC_RMMICTL_AUTO_EXIT_RRAP_BIT 0x10000000U

#define	DWC_RMMICTL_AUTO_EXIT_RRAP_SHIFT 28U

#define	DWC_RMMICTL_AUTO_ROM_RRAP_BIT 0x20000000U

#define	DWC_RMMICTL_AUTO_ROM_RRAP_SHIFT 29U

#define	DWC_RMMICTL_AUTO_EXIT_H8_BIT 0x40000000U

#define	DWC_RMMICTL_AUTO_EXIT_H8_SHIFT 30U

#define	DWC_RMMICTL_AUTO_ROM_H8_BIT 0x80000000U

#define	DWC_RMMICTL_AUTO_ROM_H8_SHIFT 31U

#define	DWC_FIFOSZ_DEPTH_BITS 0x0000ffffU

#define	DWC_FIFOSZ_DEPTH_SHIFT 0U

#define	DWC_FIFOSZ_STARTADDR_BITS 0xffff0000U

#define	DWC_FIFOSZ_STARTADDR_SHIFT 16U

#define	DWC_DEVT_BITS 0x00000f00U

#define	DWC_DEVT_SHIFT 8U

#define	DWC_DEVT_DISCONN 0U /** @< */

#define	DWC_DEVT_USBRESET 1U /** @< */

#define	DWC_DEVT_CONNDONE 2U /** @< */

#define	DWC_DEVT_ULST_CHNG 3U /** @< */

#define	DWC_DEVT_WKUP 4U /** @< */

#define	DWC_DEVT_HIBER_REQ 5U /** @< */

#define	DWC_DEVT_U3_L2L1_SUSP 6U /** @< */

#define	DWC_DEVT_SOF 7U /** @< */

#define	DWC_DEVT_ERRATICERR 9U /** @< */

#define	DWC_DEVT_CMD_CMPL 10U /** @< */

#define	DWC_DEVT_OVERFLOW 11U /** @< */

#define	DWC_DEVT_VNDR_DEV_TST_RCVD 12U /** @< */

#define	DWC_DEVT_INACT_TIMEOUT_RCVD 13U

#define	DWC_DEVT_EVT_INFO_BITS 0xffff0000U

#define	DWC_DEVT_EVT_INFO_SHIFT 16U

#define	DWC_DEVT_ULST_STATE_BITS 0x000f0000U

#define	DWC_DEVT_ULST_STATE_SHIFT 16U

#define	DWC_LINK_STATE_U0 0U /** @< */

#define	DWC_LINK_STATE_U1 1U /** @< */

#define	DWC_LINK_STATE_U2 2U /** @< */

#define	DWC_LINK_STATE_U3 3U /** @< */

#define	DWC_LINK_STATE_SS_DIS 4U /** @< */

#define	DWC_LINK_STATE_RX_DET 5U /** @< */

#define	DWC_LINK_STATE_SS_INACT 6U /** @< */

#define	DWC_LINK_STATE_POLL 7U /** @< */

#define	DWC_LINK_STATE_RECOV 8U /** @< */

#define	DWC_LINK_STATE_HRESET 9U /** @< */

#define	DWC_LINK_STATE_CMPLY 10U /** @< */

#define	DWC_LINK_STATE_LPBK 11U /** @< */

#define	DWC_LINK_STATE_RESET 14U /** @< */

#define	DWC_LINK_STATE_RESUME 15U

#define	DWC_LINK_STATE_ON 0U /** @< */

#define	DWC_LINK_STATE_SLEEP 2U /** @< */

#define	DWC_LINK_STATE_SUSPEND 3U /** @< */

#define	DWC_LINK_STATE_EARLY_SUSPEND 5U

#define	DWC_DEVT_ULST_SS_BIT 0x00100000U

#define	DWC_DEVT_ULST_SS_SHIFT 20U

#define	DWC_DEVT_HIBER_STATE_BITS DWC_DEVT_ULST_STATE_BITS

#define	DWC_DEVT_HIBER_STATE_SHIFT DWC_DEVT_ULST_STATE_SHIFT

#define	DWC_DEVT_HIBER_SS_BIT DWC_DEVT_ULST_SS_BIT

#define	DWC_DEVT_HIBER_SS_SHIFT DWC_DEVT_ULST_SS_SHIFT

#define	DWC_DEVT_HIBER_HIRD_BITS 0x0f000000U

#define	DWC_DEVT_HIBER_HIRD_SHIFT 24U

#define	DWC_DEPEVT_EPNUM_BITS 0x0000003eU

#define	DWC_DEPEVT_EPNUM_SHIFT 1U

#define	DWC_DEPEVT_INTTYPE_BITS 0x000003c0U

#define	DWC_DEPEVT_INTTYPE_SHIFT 6U

#define	DWC_DEPEVT_XFER_CMPL 1U /** @< */

#define	DWC_DEPEVT_XFER_IN_PROG 2U /** @< */

#define	DWC_DEPEVT_XFER_NRDY 3U /** @< */

#define	DWC_DEPEVT_FIFOXRUN 4U /** @< */

#define	DWC_DEPEVT_STRM_EVT 6U /** @< */

#define	DWC_DEPEVT_EPCMD_CMPL 7U

#define	DWC_DEPEVT_NO_MORE_RSCS_BIT 0x00001000U

#define	DWC_DEPEVT_NO_MORE_RSCS_SHIFT 12U

#define	DWC_DEPEVT_ISOC_TIME_PASSED_BIT 0x00002000U

#define	DWC_DEPEVT_ISOC_TIME_PASSED_SHIFT 13U

#define	DWC_DEPEVT_STRM_EVT_BITS 0x0000f000U

#define	DWC_DEPEVT_STRM_EVT_SHIFT 12U

#define	DWC_DEPEVT_STRM_FOUND 1U /** @< */

#define	DWC_DEPEVT_STRM_NOT_FOUND 2U

#define	DWC_DEPEVT_BUS_ERR_BIT 0x00001000U

#define	DWC_DEPEVT_BUS_ERR_SHIFT 12U

#define	DWC_DEPEVT_SHORT_PKT_BIT 0x00002000U

#define	DWC_DEPEVT_SHORT_PKT_SHIFT 13U

#define	DWC_DEPEVT_IOC_BIT 0x00004000U

#define	DWC_DEPEVT_IOC_SHIFT 14U

#define	DWC_DEPEVT_LST_BIT 0x00008000U

#define	DWC_DEPEVT_LST_SHIFT 15U

#define	DWC_DEPEVT_MISSED_ISOC_BIT DWC_DEPEVT_LST_BIT

#define	DWC_DEPEVT_MISSED_ISOC_SHIFT DWC_DEPEVT_LST_SHIFT

#define	DWC_DEPEVT_CTRL_BITS 0x00003000U

#define	DWC_DEPEVT_CTRL_SHIFT 12U

#define	DWC_DEPEVT_XFER_ACTIVE_BIT 0x00008000U

#define	DWC_DEPEVT_XFER_ACTIVE_SHIFT 15U

#define	DWC_DEPEVT_CTRL_SETUP 0U /** @< */

#define	DWC_DEPEVT_CTRL_DATA 1U /** @< */

#define	DWC_DEPEVT_CTRL_STATUS 2U

#define	DWC_DEPEVT_STRM_ID_BITS 0xffff0000U

#define	DWC_DEPEVT_STRM_ID_SHIFT 16U

#define	DWC_DEPEVT_ISOC_UFRAME_NUM_BITS 0xffff0000U

#define	DWC_DEPEVT_ISOC_UFRAME_NUM_SHIFT 16U

#define	DWC_DEPEVT_XFER_RSC_IDX_BITS 0x007f0000U

#define	DWC_DEPEVT_XFER_RSC_IDX_SHIFT 16U

#define	DWC_DEPEVT_CUR_DAT_SEQ_NUM_BITS 0x001f0000U

#define	DWC_DEPEVT_CUR_DAT_SEQ_NUM_SHIFT 16U

#define	DWC_DEPEVT_FLOW_CTRL_BIT 0x00200000U

#define	DWC_DEPEVT_FLOW_CTRL_SHIFT 21U

#define	DWC_GINT_PHY_PORT_BITS 0xf00U

#define	DWC_GINT_PHY_PORT_SHIFT 8U

#define	DWC_CORE_GLOBAL_REG_OFFSET 0x100U

#define	DWC_EPMAP_RES_NUM_BITS 0x1fU

#define	DWC_EPMAP_RES_NUM_SHIFT 0U

#define	DWC_DEV_GLOBAL_REG_OFFSET 0x700U

#define	DWC_EPCFG1_INTRNUM_BITS 0x0000003fU

#define	DWC_EPCFG1_INTRNUM_SHIFT 0U

#define	DWC_EPCFG1_XFER_CMPL_BIT 0x00000100U

#define	DWC_EPCFG1_XFER_CMPL_SHIFT 8U

#define	DWC_EPCFG1_XFER_IN_PROG_BIT 0x00000200U

#define	DWC_EPCFG1_XFER_IN_PROG_SHIFT 9U

#define	DWC_EPCFG1_XFER_NRDY_BIT 0x00000400U

#define	DWC_EPCFG1_XFER_NRDY_SHIFT 10U

#define	DWC_EPCFG1_FIFOXRUN_BIT 0x00000800U

#define	DWC_EPCFG1_FIFOXRUN_SHIFT 11U

#define	DWC_EPCFG1_SETUP_PNDG_BIT 0x00001000U

#define	DWC_EPCFG1_SETUP_PNDG_SHIFT 12U

#define	DWC_EPCFG1_EPCMD_CMPL_BIT 0x00002000U

#define	DWC_EPCFG1_EPCMD_CMPL_SHIFT 13U

#define	DWC_EPCFG1_BINTERVAL_BITS 0x00ff0000U

#define	DWC_EPCFG1_BINTERVAL_SHIFT 16U

#define	DWC_EPCFG1_STRM_CAP_BIT 0x01000000U

#define	DWC_EPCFG1_STRM_CAP_SHIFT 24U

#define	DWC_EPCFG1_EP_DIR_BIT 0x02000000U

#define	DWC_EPCFG1_EP_DIR_SHIFT 25U

#define	DWC_EPCFG1_EP_NUM_BITS 0x3c000000U

#define	DWC_EPCFG1_EP_NUM_SHIFT 26

#define	DWC_EPCFG0_EPTYPE_BITS 0x00000006U

#define	DWC_EPCFG0_EPTYPE_SHIFT 1U

#define	DWC_USB3_EP_TYPE_CONTROL 0U /** @< */

#define	DWC_USB3_EP_TYPE_ISOC 1U /** @< */

#define	DWC_USB3_EP_TYPE_BULK 2U /** @< */

#define	DWC_USB3_EP_TYPE_INTR 3U

#define	DWC_EPCFG0_MPS_BITS 0x00003ff8U

#define	DWC_EPCFG0_MPS_SHIFT 3U

#define	DWC_EPCFG0_FLOW_CTRL_STATE_BIT 0x00010000U

#define	DWC_EPCFG0_FLOW_CTRL_STATE_SHIFT 16U

#define	DWC_EPCFG0_TXFNUM_BITS 0x003e0000U

#define	DWC_EPCFG0_TXFNUM_SHIFT 17U

#define	DWC_EPCFG0_BRSTSIZ_BITS 0x03c00000U

#define	DWC_EPCFG0_BRSTSIZ_SHIFT 22U

#define	DWC_EPCFG0_DSNUM_BITS 0x7c000000U

#define	DWC_EPCFG0_DSNUM_SHIFT 26U

#define	DWC_EPCFG0_IGN_DSNUM_BIT 0x80000000U

#define	DWC_EPCFG0_IGN_DSNUM_SHIFT 31U

#define	DWC_EPCFG0_CFG_ACTION_BITS 0xc0000000U

#define	DWC_EPCFG0_CFG_ACTION_SHIFT 30U

#define	DWC_CFG_ACTION_INIT 0U /** @< */

#define	DWC_CFG_ACTION_RESTORE 1U /** @< */

#define	DWC_CFG_ACTION_MODIFY 2U

#define	DWC_DEV_OUT_EP_REG_OFFSET 0x800U

#define	DWC_DEV_IN_EP_REG_OFFSET 0x810U

#define	DWC_EP_REG_OFFSET 0x20U

Register (GSBUSCFG0).
This enum represents the bit fields of the Core SoC Bus Configuration 0 Bus Burst Len Access: R_W. 0: single 1: incr 3: incr4 7: incr8 15: incr16 31: incr32 (non-AHB mode only) 63: incr64 (non-AHB mode only) 127: incr128 (non-AHB mode only) 255: incr256 (non-AHB mode only)
#define	DWC_SBUSCFG0_HBURSTLEN_BITS 0x000000ffU

#define	DWC_SBUSCFG0_HBURSTLEN_SHIFT 0U

#define	DWC_SBUSCFG0_INT_DMA_BURST_SINGLE 0U

#define	DWC_SBUSCFG0_INT_DMA_BURST_INCR 1U

#define	DWC_SBUSCFG0_INT_DMA_BURST_INCR4 3U

#define	DWC_SBUSCFG0_INT_DMA_BURST_INCR8 7U

#define	DWC_SBUSCFG0_INT_DMA_BURST_INCR16 15U

#define	DWC_SBUSCFG0_INT_DMA_BURST_INCR32 31U

#define	DWC_SBUSCFG0_INT_DMA_BURST_INCR64 63U

#define	DWC_SBUSCFG0_INT_DMA_BURST_INCR128 127U

#define	DWC_SBUSCFG0_INT_DMA_BURST_INCR256 255U

#define	DWC_SBUSCFG0_DES_WR_POST_BIT 0x00000100U

#define	DWC_SBUSCFG0_DES_WR_POST_SHIFT 8U

#define	DWC_SBUSCFG0_DAT_WR_POST_BIT 0x00000200U

#define	DWC_SBUSCFG0_DAT_WR_POST_SHIFT 9U

#define	DWC_SBUSCFG0_DES_BIG_END_BIT 0x00000400U

#define	DWC_SBUSCFG0_DES_BIG_END_SHIFT 10U

#define	DWC_SBUSCFG0_DAT_BIG_END_BIT 0x00000800U

#define	DWC_SBUSCFG0_DAT_BIG_END_SHIFT 11U

#define	DWC_SBUSCFG0_STORE_AND_FORWARD_BIT 0x00001000U

#define	DWC_SBUSCFG0_STORE_AND_FORWARD_SHIFT 12U

#define	DWC_SBUSCFG0_SING_REQ_BIT 0x00004000U

#define	DWC_SBUSCFG0_SING_REQ_SHIFT 14U

#define	DWC_SBUSCFG0_READ_AFTER_WRITE_BIT 0x00008000U

#define	DWC_SBUSCFG0_READ_AFTER_WRITE_SHIFT 15U

#define	DWC_SBUSCFG0_DES_WR_REQ_INFO_BITS 0x000f0000U

#define	DWC_SBUSCFG0_DES_WR_REQ_INFO_SHIFT 16U

#define	DWC_SBUSCFG0_DAT_WR_REQ_INFO_BITS 0x00f00000U

#define	DWC_SBUSCFG0_DAT_WR_REQ_INFO_SHIFT 20U

#define	DWC_SBUSCFG0_DES_RD_REQ_INFO_BITS 0x0f000000U

#define	DWC_SBUSCFG0_DES_RD_REQ_INFO_SHIFT 24U

#define	DWC_SBUSCFG0_DAT_RD_REQ_INFO_BITS 0xf0000000U

#define	DWC_SBUSCFG0_DAT_RD_REQ_INFO_SHIFT 28U

Register (GSBUSCFG1).
This macros represents the bit fields of the Core SoC Bus Configuration 1
#define	DWC_SBUSCFG1_DES_ADDR_SPC_BITS 0x0000000fU

#define	DWC_SBUSCFG1_DES_ADDR_SPC_SHIFT 0U

#define	DWC_SBUSCFG1_DAT_ADDR_SPC_BITS 0x000000f0U

#define	DWC_SBUSCFG1_DAT_ADDR_SPC_SHIFT 4U

Register (GTXTHRCFG).
This enum represents the bit fields of the Core Tx Threshold Control
#define	DWC_TXTHRCTL_USB_MAX_TX_BURST_SIZE_BITS 0x00ff0000U

#define	DWC_TXTHRCTL_USB_MAX_TX_BURST_SIZE_SHIFT 16U

#define	DWC_TXTHRCTL_USB_TX_PKT_CNT_BITS 0x1f000000U

#define	DWC_TXTHRCTL_USB_TX_PKT_CNT_SHIFT 24U

#define	DWC_TXTHRCTL_USB_TX_PKT_CNT_EN_BIT 0x20000000U

#define	DWC_TXTHRCTL_USB_TX_PKT_CNT_EN_SHIFT 29U

Register (GRXTHRCFG).
This enum represents the bit fields of the Core Rx Threshold Control Register (GRXTHRCFG).
#define	DWC_RXTHRCTL_USB_MAX_RX_BURST_SIZE_BITS 0x00f80000U

#define	DWC_RXTHRCTL_USB_MAX_RX_BURST_SIZE_SHIFT 19U

#define	DWC_RXTHRCTL_USB_RX_PKT_CNT_BITS 0x0f000000U

#define	DWC_RXTHRCTL_USB_RX_PKT_CNT_SHIFT 24U

#define	DWC_RXTHRCTL_USB_RX_PKT_CNT_EN_BIT 0x20000000U

#define	DWC_RXTHRCTL_USB_RX_PKT_CNT_EN_SHIFT 29U

Register (GCTL).
This enum represents the bit fields of the Core Control
#define	DWC_GCTL_DSBL_CLCK_GTNG_BIT 0x00000001U

#define	DWC_GCTL_DSBL_CLCK_GTNG_SHIFT 0U

#define	DWC_GCTL_GBL_HIBER_EN_BIT 0x00000002U

#define	DWC_GCTL_GBL_HIBER_EN_SHIFT 1U

#define	DWC_GCTL_DIS_SCRAMBLE_BIT 0x00000008U

#define	DWC_GCTL_DIS_SCRAMBLE_SHIFT 3U

#define	DWC_GCTL_SCALE_DOWN_BITS 0x00000030U

#define	DWC_GCTL_SCALE_DOWN_SHIFT 4U

#define	DWC_GCTL_RAM_CLK_SEL_BITS 0x000000c0U

#define	DWC_GCTL_RAM_CLK_SEL_SHIFT 6U

#define	DWC_GCTL_DEBUG_ATTACH_BIT 0x00000100U

#define	DWC_GCTL_DEBUG_ATTACH_SHIFT 8U

#define	DWC_GCTL_U1U2_TIMER_SCALE_BIT 0x00000200U

#define	DWC_GCTL_U1U2_TIMER_SCALE_SHIFT 9U

#define	DWC_GCTL_SOFITPSYNC_BIT 0x00000400U

#define	DWC_GCTL_SOFITPSYNC_SHIFT 10U

#define	DWC_GCTL_CORE_SOFT_RST_BIT 0x00000800U

#define	DWC_GCTL_CORE_SOFT_RST_SHIFT 11U

#define	DWC_GCTL_PRT_CAP_DIR_BITS 0x00003000U

#define	DWC_GCTL_PRT_CAP_DIR_SHIFT 12U

#define	DWC_GCTL_PRT_CAP_HOST 1U

#define	DWC_GCTL_PRT_CAP_DEVICE 2U

#define	DWC_GCTL_PRT_CAP_OTG 3U

#define	DWC_GCTL_FRMSCLDWN_BITS 0x0000c000U

#define	DWC_GCTL_FRMSCLDWN_SHIFT 14U

#define	DWC_GCTL_U2RSTECN_BIT 0x00010000U

#define	DWC_GCTL_U2RSTECN_SHIFT 16U

#define	DWC_GCTL_BYPSSETADDR_BIT 0x00020000U

#define	DWC_GCTL_BYPSSETADDR_SHIFT 17U

#define	DWC_GCTL_MASTERFILTBYPASS_BIT 0x00040000U

#define	DWC_GCTL_MASTERFILTBYPASS_SHIFT 18U

#define	DWC_GCTL_PWR_DN_SCALE_BITS 0xfff80000U

#define	DWC_GCTL_PWR_DN_SCALE_SHIFT 19U

Register (GEVTEN).
This enum represents the bit fields of the Core Interrupt Mask
#define	DWC_GEVTEN_ULPI_CK_EVT_EN_BIT 0x00000001U

#define	DWC_GEVTEN_ULPI_CK_EVT_SHIFT 0U

#define	DWC_GEVTEN_I2C_EVT_EN_BIT 0x00000002U

#define	DWC_GEVTEN_I2C_EVT_EN_SHIFT 1U

Register (GSTS).
This enum represents the bit fields of the Core Status
#define	DWC_GSTS_CURMODE_BITS 0x00000003U

#define	DWC_GSTS_CURMODE_SHIFT 0U

#define	DWC_GSTS_DEVICE_MODE 0U

#define	DWC_GSTS_HOST_MODE 1U

#define	DWC_GSTS_DRD_MODE 2U

#define	DWC_GSTS_BUS_ERR_ADDR_VLD_BIT 0x00000010U

#define	DWC_GSTS_BUS_ERR_ADDR_VLD_SHIFT 4U

#define	DWC_GSTS_CSR_TIMEOUT_BIT 0x00000020U

#define	DWC_GSTS_CSR_TIMEOUT_SHIFT 5U

#define	DWC_GSTS_DEV_EVT_PENDING_BIT 0x00000040U

#define	DWC_GSTS_DEV_EVT_PENDING_SHIFT 6U

#define	DWC_GSTS_HOST_EVT_PENDING_BIT 0x00000080U

#define	DWC_GSTS_HOST_EVT_PENDING_SHIFT 7U

#define	DWC_GSTS_ADP_EVT_PENDING_BIT 0x00000100U

#define	DWC_GSTS_ADP_EVT_PENDING_SHIFT 8U

#define	DWC_GSTS_BC_EVT_PENDING_BIT 0x00000200U

#define	DWC_GSTS_BC_EVT_PENDING_SHIFT 9U

#define	DWC_GSTS_OTG_EVT_PENDING_BIT 0x00000400U

#define	DWC_GSTS_OTG_EVT_PENDING_SHIFT 10U

#define	DWC_GSTS_SSIC_IP_BIT 0x00000800U

#define	DWC_GSTS_SSIC_IP_SHIFT 11U

#define	DWC_GSTS_CBELT_BITS 0xfff00000U

#define	DWC_GSTS_CBELT_SHIFT 20U

Register (GHWPARAMS0).
This enum represents the bit fields of the Hardware Parameters 0
#define	DWC_HWP0_MODE_BITS 0x00000007U

#define	DWC_HWP0_MODE_SHIFT 0U

#define	DWC_HWP0_MBUS_TYPE_BITS 0x00000038U

#define	DWC_HWP0_MBUS_TYPE_SHIFT 3U

#define	DWC_HWP0_SBUS_TYPE_BITS 0x000000c0U

#define	DWC_HWP0_SBUS_TYPE_SHIFT 6U

#define	DWC_HWP0_MDWIDTH_BITS 0x0000ff00U

#define	DWC_HWP0_MDWIDTH_SHIFT 8U

#define	DWC_HWP0_SDWIDTH_BITS 0x00ff0000U

#define	DWC_HWP0_SDWIDTH_SHIFT 16U

#define	DWC_HWP0_AWIDTH_BITS 0x3f000000U

#define	DWC_HWP0_AWIDTH_SHIFT 24U

Register (GHWPARAMS1).
This enum represents the bit fields of the Hardware Parameters 1
#define	DWC_HWP1_IDWIDTH_M1_BITS 0x00000007U

#define	DWC_HWP1_IDWIDTH_M1_SHIFT 0U

#define	DWC_HWP1_BURSTWIDTH_M1_BITS 0x00000038U

#define	DWC_HWP1_BURSTWIDTH_M1_SHIFT 3U

#define	DWC_HWP1_DATAINFOWIDTH_BITS 0x000001c0U

#define	DWC_HWP1_DATAINFOWIDTH_SHIFT 6U

#define	DWC_HWP1_REQINFOWIDTH_BITS 0x00000e00U

#define	DWC_HWP1_REQINFOWIDTH_SHIFT 9U

#define	DWC_HWP1_ASPACEWIDTH_BITS 0x00007000U

#define	DWC_HWP1_ASPACEWIDTH_SHIFT 12U

#define	DWC_HWP1_DEV_NUM_INT_BITS 0x001f8000U

#define	DWC_HWP1_DEV_NUM_INT_SHIFT 15U

#define	DWC_HWP1_NUM_RAMS_BITS 0x00600000U

#define	DWC_HWP1_NUM_RAMS_SHIFT 21U

#define	DWC_HWP1_SPRAM_TYP_BIT 0x00800000U

#define	DWC_HWP1_SPRAM_TYP_SHIFT 23U

#define	DWC_HWP1_EN_PWROPT_BITS 0x03000000U

#define	DWC_HWP1_EN_PWROPT_SHIFT 24U

#define	DWC_EN_PWROPT_NONE 0U

#define	DWC_EN_PWROPT_CLK_GATING_ONLY 1U

#define	DWC_EN_PWROPT_HIBERNATION 2U

#define	DWC_HWP1_MAC_PHY_CLKS_SYNC_BIT 0x04000000U

#define	DWC_HWP1_MAC_PHY_CLKS_SYNC_SHIFT 26U

#define	DWC_HWP1_MAC_RAM_CLKS_SYNC_BIT 0x08000000U

#define	DWC_HWP1_MAC_RAM_CLKS_SYNC_SHIFT 27U

#define	DWC_HWP1_RAM_BUS_CLKS_SYNC_BIT 0x10000000U

#define	DWC_HWP1_RAM_BUS_CLKS_SYNC_SHIFT 28U

#define	DWC_HWP1_RM_OPT_FEATURES_BIT 0x40000000U

#define	DWC_HWP1_RM_OPT_FEATURES_SHIFT 30U

Register (GHWPARAMS2).
This enum represents the bit fields of the Hardware Parameters 2
#define	DWC_HWP2_USERID_BITS 0xffffffffU

#define	DWC_HWP2_USERID_SHIFT 0U

Register (GHWPARAMS3).
This enum represents the bit fields of the Hardware Parameters 3
#define	DWC_HWP3_SSPHY_IFC_BITS 0x00000003U

#define	DWC_HWP3_SSPHY_IFC_SHIFT 0U

#define	DWC_HWP3_HSPHY_IFC_BITS 0x0000000cU

#define	DWC_HWP3_HSPHY_IFC_SHIFT 2U

#define	DWC_HWP3_FSPHY_IFC_BITS 0x00000030U

#define	DWC_HWP3_FSPHY_IFC_SHIFT 4U

#define	DWC_HWP3_HSPHY_DWIDTH_BITS 0x000000c0U

#define	DWC_HWP3_HSPHY_DWIDTH_SHIFT 6U

#define	DWC_HWP3_VEND_CTL_IFC_BIT 0x00000400U

#define	DWC_HWP3_VEND_CTL_IFC_SHIFT 10U

#define	DWC_HWP3_ULPI_CARKIT_BIT 0x00000800U

#define	DWC_HWP3_ULPI_CARKIT_SHIFT 11U

#define	DWC_HWP3_NUM_EPS_BITS 0x0003f000U

#define	DWC_HWP3_NUM_EPS_SHIFT 12U

#define	DWC_HWP3_NUM_IN_EPS_BITS 0x007c0000U

#define	DWC_HWP3_NUM_IN_EPS_SHIFT 18U

#define	DWC_HWP3_TOT_XFR_RSRC_BITS 0x7f800000U

#define	DWC_HWP3_TOT_XFR_RSRC_SHIFT 23U

Register (GHWPARAMS4).
This enum represents the bit fields of the Hardware Parameters 4
#define	DWC_HWP4_TRBS_PER_XFER_BITS 0x0000003fU

#define	DWC_HWP4_TRBS_PER_XFER_SHIFT 0U

#define	DWC_HWP4_HIBER_SPAD_BITS 0x0001e000U

#define	DWC_HWP4_HIBER_SPAD_SHIFT 13U

#define	DWC_HWP4_NUM_SS_USB_INST_BITS 0x001e0000U

#define	DWC_HWP4_NUM_SS_USB_INST_SHIFT 17U

#define	DWC_HWP4_EN_ISOC_SUPT_BIT 0x00800000U

#define	DWC_HWP4_EN_ISOC_SUPT_SHIFT 23U

#define	DWC_HWP4_BMU_PTL_DEPTH_BITS 0x0f000000U

#define	DWC_HWP4_BMU_PTL_DEPTH_SHIFT 24U

#define	DWC_HWP4_BMU_LSP_DEPTH_BITS 0xf0000000U

#define	DWC_HWP4_BMU_LSP_DEPTH_SHIFT 28U

Register (GHWPARAMS5).
This enum represents the bit fields of the Hardware Parameters 5
#define	DWC_HWP5_BMU_BUSGM_DEPTH_BITS 0x0000000fU

#define	DWC_HWP5_BMU_BUSGM_DEPTH_SHIFT 0U

#define	DWC_HWP5_RXQ_FIFO_DEPTH_BITS 0x000003f0U

#define	DWC_HWP5_RXQ_FIFO_DEPTH_SHIFT 4U

#define	DWC_HWP5_TXQ_FIFO_DEPTH_BITS 0x0000fc00U

#define	DWC_HWP5_TXQ_FIFO_DEPTH_SHIFT 10U

#define	DWC_HWP5_DWQ_FIFO_DEPTH_BITS 0x003f0000U

#define	DWC_HWP5_DWQ_FIFO_DEPTH_SHIFT 16U

#define	DWC_HWP5_DFQ_FIFO_DEPTH_BITS 0x0fc00000U

#define	DWC_HWP5_DFQ_FIFO_DEPTH_SHIFT 22U

Register (GHWPARAMS6).
This enum represents the bit fields of the Hardware Parameters 6
#define	DWC_HWP6_PSQ_FIFO_DEPTH_BITS 0x0000003fU

#define	DWC_HWP6_PSQ_FIFO_DEPTH_SHIFT 0U

#define	DWC_HWP6_EN_DBG_PORTS_BIT 0x00000040U

#define	DWC_HWP6_EN_DBG_PORTS_SHIFT 6U

#define	DWC_HWP6_EN_FPGA_BIT 0x00000080U

#define	DWC_HWP6_EN_FPGA_SHIFT 7U

#define	DWC_HWP6_EN_SRP_BIT 0x00000400U

#define	DWC_HWP6_EN_SRP_SHIFT 10U

#define	DWC_HWP6_EN_HNP_BIT 0x00000800U

#define	DWC_HWP6_EN_HNP_SHIFT 11U

#define	DWC_HWP6_EN_ADP_BIT 0x00001000U

#define	DWC_HWP6_EN_ADP_SHIFT 12U

#define	DWC_HWP6_EN_OTG_BIT 0x00002000U

#define	DWC_HWP6_EN_OTG_SHIFT 13U

#define	DWC_HWP6_EN_BC_BIT 0x00004000U

#define	DWC_HWP6_EN_BC_SHIFT 14U

#define	DWC_HWP6_EN_BUS_FILTERS_BIT 0x00008000U

#define	DWC_HWP6_EN_BUS_FILTERS_SHIFT 15U

#define	DWC_HWP6_RAM0_DEPTH_BITS 0xffff0000U

#define	DWC_HWP6_RAM0_DEPTH_SHIFT 16U

Register (GHWPARAMS7).
This enum represents the bit fields of the Hardware Parameters 7
#define	DWC_HWP7_RAM1_DEPTH_BITS 0x0000ffffU

#define	DWC_HWP7_RAM1_DEPTH_SHIFT 0U

#define	DWC_HWP7_RAM2_DEPTH_BITS 0xffff0000U

#define	DWC_HWP7_RAM2_DEPTH_SHIFT 16U

Register (GHWPARAMS8).
This enum represents the bit fields of the Hardware Parameters 8
#define	DWC_HWP8_DCACHE_DEPTH_BITS 0xffffffffU

#define	DWC_HWP8_DCACHE_DEPTH_SHIFT 0U

Register (GDBGFIFOSPACE).
This enum represents the bit fields of the Debug Queue/FIFO Space 0 - 31 TxFIFO Number 32 - 63 RxFIFO Number 64 - 95 TxReqQ Number 96 - 127 RxReqQ Number 128 - 159 RxInfoQ Number 160 DescFetchQ 161 EventQ 162 ProtocolStatusQ
#define	DWC_DBGFIFOSPACE_FIFO_QUEUE_SEL_BITS 0x000000ffU

#define	DWC_DBGFIFOSPACE_FIFO_QUEUE_SEL_SHIFT 0U

#define	DWC_DBGFIFOSPACE_SPACE_AVAIL_BITS 0xffff0000U

#define	DWC_DBGFIFOSPACE_SPACE_AVAIL_SHIFT 16U

Register (GDBGLTSSM).
This enum represents the bit fields of the Debug LTSSM
#define	DWC_DBGLTSSM_PIPE_STATUS_BITS 0x0003ffffU

#define	DWC_DBGLTSSM_PIPE_STATUS_SHIFT 0U

#define	DWC_DBGLTSSM_LTDB_SUB_STATE_BITS 0x003c0000U

#define	DWC_DBGLTSSM_LTDB_SUB_STATE_SHIFT 18U

#define	DWC_DBGLTSSM_LTDB_STATE_BITS 0x03c00000U

#define	DWC_DBGLTSSM_LTDB_STATE_SHIFT 22U

#define	DWC_DBGLTSSM_LTDB_TIMEOUT_BIT 0x04000000U

#define	DWC_DBGLTSSM_LTDB_TIMEOUT_SHIFT 26U

Registers (GUSB2PHYCFGn).
This enum represents the bit fields of the Core USB2 PHY Configuration
#define	DWC_USB2PHYCFG_TOUT_CAL_BITS 0x00000007U

#define	DWC_USB2PHYCFG_TOUT_CAL_SHIFT 0U

#define	DWC_USB2PHYCFG_16B_PHY_IF_BIT 0x00000008U

#define	DWC_USB2PHYCFG_16B_PHY_IF_SHIFT 3U

#define	DWC_USB2PHYCFG_DDR_SEL_BIT 0x00000008U

#define	DWC_USB2PHYCFG_DDR_SEL_SHIFT 3U

#define	DWC_USB2PHYCFG_UTMI_ULPI_BIT 0x00000010U

#define	DWC_USB2PHYCFG_UTMI_ULPI_SHIFT 4U

#define	DWC_USB2PHYCFG_FSINTF_BIT 0x00000020U

#define	DWC_USB2PHYCFG_FSINTF_SHIFT 5U

#define	DWC_USB2PHYCFG_SUS_PHY_BIT 0x00000040U

#define	DWC_USB2PHYCFG_SUS_PHY_SHIFT 6U

#define	DWC_USB2PHYCFG_PHY_SEL_BIT 0x00000080U

#define	DWC_USB2PHYCFG_PHY_SEL_SHIFT 7U

#define	DWC_USB2PHYCFG_ENBL_SLP_M_BIT 0x00000100U

#define	DWC_USB2PHYCFG_ENBL_SLP_M_SHIFT 8U

#define	DWC_USB2PHYCFG_USB_TRD_TIM_BITS 0x00003c00U

#define	DWC_USB2PHYCFG_USB_TRD_TIM_SHIFT 10U

#define	DWC_USB2PHYCFG_PHY_LPWR_CLK_SEL_BIT 0x00004000U

#define	DWC_USB2PHYCFG_PHY_LPWR_CLK_SEL_SHIFT 14U

#define	DWC_USB2PHYCFG_ULPI_AUTO_RES_BIT 0x0000800U

#define	DWC_USB2PHYCFG_ULPI_AUTO_RES_SHIFT 15U

#define	DWC_USB2PHYCFG_ULPI_CLK_SUS_M_BIT 0x00010000U

#define	DWC_USB2PHYCFG_ULPI_CLK_SUS_M_SHIFT 16U

#define	DWC_USB2PHYCFG_ULPI_EXT_VBUS_DRV_BIT 0x00020000U

#define	DWC_USB2PHYCFG_ULPI_EXT_VBUS_DRV_SHIFT 17U

#define	DWC_USB2PHYCFG_ULPI_EXT_VBUS_IND_BIT 0x00040000U

#define	DWC_USB2PHYCFG_ULPI_EXT_VBUS_IND_SHIFT 18U

#define	DWC_USB2PHYCFG_PHY_INTR_NUM_BITS 0x01f80000U

#define	DWC_USB2PHYCFG_PHY_INTR_NUM_SHIFT 19U

#define	DWC_USB2PHYCFG_OTG_INTR_NUM_BITS 0x7e000000U

#define	DWC_USB2PHYCFG_OTG_INTR_NUM_SHIFT 25U

#define	DWC_USB2PHYCFG_PHY_SOFT_RST_BIT 0x80000000U

#define	DWC_USB2PHYCFG_PHY_SOFT_RST_SHIFT 31U

Registers (GUSB2I2CCTLn).
This enum represents the bit fields in the USB2 I2C Control
#define	DWC_USB2I2C_RSVD_BITS 0xffffffffU

#define	DWC_USB2I2C_RSVD_SHIFT 0U

Registers (GUSB2PHYACCn).
This enum represents the bit fields in the USB2 Phy Vendor Control
#define	DWC_USB2PHY_REGDATA_BITS 0x000000ffU

#define	DWC_USB2PHY_REGDATA_SHIFT 0U

#define	DWC_USB2PHY_VCTRL_BITS 0x0000ff00U

#define	DWC_USB2PHY_VCTRL_SHIFT 8U

#define	DWC_USB2PHY_EXTREGADDR_BITS 0x00003f00U

#define	DWC_USB2PHY_EXTREGADDR_SHIFT 8U

#define	DWC_USB2PHY_REGADDR_BITS 0x003f0000U

#define	DWC_USB2PHY_REGADDR_SHIFT 16U

#define	DWC_USB2PHY_REGWR_BIT 0x00400000U

#define	DWC_USB2PHY_REGWR_SHIFT 22U

#define	DWC_USB2PHY_VSTSBSY_BIT 0x00800000U

#define	DWC_USB2PHY_VSTSBSY_SHIFT 23U

#define	DWC_USB2PHY_VSTSDONE_BIT 0x01000000U

#define	DWC_USB2PHY_VSTSDONE_SHIFT 24U

#define	DWC_USB2PHY_NEWREGREQ_BIT 0x02000000U

#define	DWC_USB2PHY_NEWREGREQ_SHIFT 25U

#define	DWC_USB2PHY_DIS_ULPI_DRVR_BIT 0x04000000U

#define	DWC_USB2PHY_DIS_ULPI_DRVR_SHIFT 26U

Registers (GUSB3PIPECTLn).
This enum represents the bit fields of the USB3 Pipe Control
#define	DWC_PIPECTL_ELAS_BUF_MODE_BIT 0x00000001U

#define	DWC_PIPECTL_ELAS_BUF_MODE_SHIFT 0U

#define	DWC_PIPECTL_TX_DEMPH_BITS 0x00000006U

#define	DWC_PIPECTL_TX_DEMPH_SHIFT 1U

#define	DWC_PIPECTL_TX_MARGIN_BITS 0x00000038U

#define	DWC_PIPECTL_TX_MARGIN_SHIFT 3U

#define	DWC_PIPECTL_TX_SWING_BIT 0x00000040U

#define	DWC_PIPECTL_TX_SWING_SHIFT 6U

#define	DWC_PIPECTL_SSIC_EN_BIT 0x00000080U

#define	DWC_PIPECTL_SSIC_EN_SHIFT 7U

#define	DWC_PIPECTL_LFPS_FILTER_BIT 0x00000200U

#define	DWC_PIPECTL_LFPS_FILTER_SHIFT 9U

#define	DWC_PIPECTL_P3_EX_SIG_P2_BIT 0x00000400U

#define	DWC_PIPECTL_P3_EX_SIG_P2_SHIFT 10U

#define	DWC_PIPECTL_P3_P2_TRAN_OK_BIT 0x00000800U

#define	DWC_PIPECTL_P3_P2_TRAN_OK_SHIFT 11U

#define	DWC_PIPECTL_LFPS_P0_ALGN_BIT 0x00001000U

#define	DWC_PIPECTL_LFPS_P0_ALGN_SHIFT 12U

#define	DWC_PIPECTL_DATA_WIDTH_BITS 0x00018000U

#define	DWC_PIPECTL_DATA_WIDTH_SHIFT 15U

#define	DWC_PIPECTL_SUS_PHY_BIT 0x00020000U

#define	DWC_PIPECTL_SUS_PHY_SHIFT 17U

#define	DWC_PIPECTL_PHY_SOFT_RST_BIT 0x80000000U

#define	DWC_PIPECTL_PHY_SOFT_RST_SHIFT 31U

Registers (GEVENTSIZn).
This enum represents the bit fields of the Event Buffer Size
#define	DWC_EVENTSIZ_SIZ_BITS 0x0000ffffU

#define	DWC_EVENTSIZ_SIZ_SHIFT 0U

#define	DWC_EVENTSIZ_INT_MSK_BIT 0x80000000U

#define	DWC_EVENTSIZ_INT_MSK_SHIFT 31U

Registers (GEVENTCNTn).
This enum represents the bit fields of the Event Buffer Count
#define	DWC_EVENTCNT_CNT_BITS 0x0000ffffU

#define	DWC_EVENTCNT_CNT_SHIFT 0U

#define	DWC_EVENT_NON_EP_BIT 0x01U

#define	DWC_EVENT_NON_EP_SHIFT 0U

#define	DWC_EVENT_INTTYPE_BITS 0xfeU

#define	DWC_EVENT_INTTYPE_SHIFT 1U

#define	DWC_EVENT_DEV_INT 0U /** @< */

#define	DWC_EVENT_OTG_INT 1U /** @< */

#define	DWC_EVENT_CARKIT_INT 3U /** @< */

#define	DWC_EVENT_I2C_INT 4U


#define	DWC_DCFG_DEVSPD_BITS 0x000007U

#define	DWC_DCFG_DEVSPD_SHIFT 0U

#define	DWC_SPEED_HS_PHY_30MHZ_OR_60MHZ 0U /** @< */

#define	DWC_SPEED_FS_PHY_30MHZ_OR_60MHZ 1U /** @< */

#define	DWC_SPEED_LS_PHY_6MHZ 2U /** @< */

#define	DWC_SPEED_FS_PHY_48MHZ 3U /** @< */

#define	DWC_SPEED_SS_PHY_125MHZ_OR_250MHZ 4U

#define	DWC_DCFG_DEVADDR_BITS 0x0003f8U

#define	DWC_DCFG_DEVADDR_SHIFT 3U

#define	DWC_DCFG_PER_FR_INTVL_BITS 0x000c00U

#define	DWC_DCFG_PER_FR_INTVL_SHIFT 10U

#define	DWC_DCFG_PER_FR_INTVL_80 0U /** @< */

#define	DWC_DCFG_PER_FR_INTVL_85 1U /** @< */

#define	DWC_DCFG_PER_FR_INTVL_90 2U /** @< */

#define	DWC_DCFG_PER_FR_INTVL_95 3U

#define	DWC_DCFG_DEV_INTR_NUM_BITS 0x01f000U

#define	DWC_DCFG_DEV_INTR_NUM_SHIFT 12U

#define	DWC_DCFG_NUM_RCV_BUF_BITS 0x3e0000U

#define	DWC_DCFG_NUM_RCV_BUF_SHIFT 17U

#define	DWC_DCFG_LPM_CAP_BIT 0x400000U

#define	DWC_DCFG_LPM_CAP_SHIFT 22U

Register (DCTL).
This enum represents the bit fields in the Device Control
#define	DWC_DCTL_SFT_DISCONN_BIT 0x00000001U

#define	DWC_DCTL_SFT_DISCONN_SHIFT 0U

#define	DWC_DCTL_TSTCTL_BITS 0x0000001eU

#define	DWC_DCTL_TSTCTL_SHIFT 1U

#define	DWC_DCTL_ULST_CHNG_REQ_BITS 0x000001e0U

#define	DWC_DCTL_ULST_CHNG_REQ_SHIFT 5U

#define	DWC_LINK_STATE_REQ_NO_ACTION 0U /** @< */

#define	DWC_LINK_STATE_REQ_SS_DISABLED 4U /** @< */

#define	DWC_LINK_STATE_REQ_RX_DETECT 5U /** @< */

#define	DWC_LINK_STATE_REQ_INACTIVE 6U /** @< */

#define	DWC_LINK_STATE_REQ_RECOVERY 8U /** @< */

#define	DWC_LINK_STATE_REQ_COMPLIANCE 10U /** @< */

#define	DWC_LINK_STATE_REQ_LOOPBACK 11U /** @< */

#define	DWC_LINK_STATE_REQ_HOST_MODE_ONLY 15U

#define	DWC_LINK_STATE_REQ_REMOTE_WAKEUP 8U

#define	DWC_DCTL_ACCEPT_U1_EN_BIT 0x00000200U

#define	DWC_DCTL_ACCEPT_U1_EN_SHIFT 9U

#define	DWC_DCTL_INIT_U1_EN_BIT 0x00000400U

#define	DWC_DCTL_INIT_U1_EN_SHIFT 10U

#define	DWC_DCTL_ACCEPT_U2_EN_BIT 0x00000800U

#define	DWC_DCTL_ACCEPT_U2_EN_SHIFT 11U

#define	DWC_DCTL_INIT_U2_EN_BIT 0x00001000U

#define	DWC_DCTL_INIT_U2_EN_SHIFT 12U

#define	DWC_DCTL_CSS_BIT 0x00010000U

#define	DWC_DCTL_CSS_SHIFT 16U

#define	DWC_DCTL_CRS_BIT 0x00020000U

#define	DWC_DCTL_CRS_SHIFT 17U

#define	DWC_DCTL_L1_HIBER_EN_BIT 0x00040000U

#define	DWC_DCTL_L1_HIBER_EN_RES_SHIFT 18U

#define	DWC_DCTL_KEEP_CONNECT_BIT 0x00080000U

#define	DWC_DCTL_KEEP_CONNECT_SHIFT 19U

#define	DWC_DCTL_LPM_NYET_THRESH_BITS 0x00f00000U

#define	DWC_DCTL_LPM_NYET_THRESH_SHIFT 20U

#define	DWC_DCTL_APP_L1_RES_BIT 0x00800000U

#define	DWC_DCTL_APP_L1_RES_SHIFT 23U

#define	DWC_DCTL_HIRD_THR_BITS 0x1f000000U

#define	DWC_DCTL_HIRD_THR_SHIFT 24U

#define	DWC_DCTL_LSFT_RST_BIT 0x20000000U

#define	DWC_DCTL_LSFT_RST_SHIFT 29U

#define	DWC_DCTL_CSFT_RST_BIT 0x40000000U

#define	DWC_DCTL_CSFT_RST_SHIFT 30U

#define	DWC_DCTL_RUN_STOP_BIT 0x80000000U

#define	DWC_DCTL_RUN_STOP_SHIFT 31U

Register (DEVTEN).
This enum represents the bit fields of the Device Event Enable
#define	DWC_DEVTEN_DISCONN_BIT 0x0001U

#define	DWC_DEVTEN_DISCONN_SHIFT 0U

#define	DWC_DEVTEN_USBRESET_BIT 0x0002U

#define	DWC_DEVTEN_USBRESET_SHIFT 1U

#define	DWC_DEVTEN_CONNDONE_BIT 0x0004U

#define	DWC_DEVTEN_CONNDONE_SHIFT 2U

#define	DWC_DEVTEN_ULST_CHNG_BIT 0x0008U

#define	DWC_DEVTEN_ULST_CHNG_SHIFT 3U

#define	DWC_DEVTEN_WKUP_BIT 0x0010U

#define	DWC_DEVTEN_WKUP_SHIFT 4U

#define	DWC_DEVTEN_HIBER_REQ_BIT 0x0020U

#define	DWC_DEVTEN_HIBER_REQ_SHIFT 5U

#define	DWC_DEVTEN_U3_L2L1_SUSP_BIT 0x0040U

#define	DWC_DEVTEN_U3_L2L1_SUSP_SHIFT 6U

#define	DWC_DEVTEN_SOF_BIT 0x0080U

#define	DWC_DEVTEN_SOF_SHIFT 7U

#define	DWC_DEVTEN_ERRATICERR_BIT 0x0200U

#define	DWC_DEVTEN_ERRATICERR_SHIFT 9U

#define	DWC_DEVTEN_INACT_TIMEOUT_BIT 0x2000U

#define	DWC_DEVTEN_INACT_TIMEOUT_SHIFT 13U

Register (DSTS).
This enum represents the bit fields in the Device Status
#define	DWC_DSTS_CONNSPD_BITS 0x00000007U

#define	DWC_DSTS_CONNSPD_SHIFT 0U

#define	DWC_DSTS_SOF_FN_BITS 0x0001fff8U

#define	DWC_DSTS_SOF_FN_SHIFT 3U

#define	DWC_DSTS_RXFIFO_EMPTY_BIT 0x00020000U

#define	DWC_DSTS_RXFIFO_EMPTY_SHIFT 17U

#define	DWC_DSTS_USBLNK_STATE_BITS 0x003c0000U

#define	DWC_DSTS_USBLNK_STATE_SHIFT 18U

#define	DWC_DSTS_DEV_CTRL_HLT_BIT 0x00400000U

#define	DWC_DSTS_DEV_CTRL_HLT_SHIFT 22U

#define	DWC_DSTS_CORE_IDLE_BIT 0x00800000U

#define	DWC_DSTS_CORE_IDLE_SHIFT 23U

#define	DWC_DSTS_SSS_BIT 0x01000000U

#define	DWC_DSTS_SSS_SHIFT 24U

#define	DWC_DSTS_RSS_BIT 0x02000000U

#define	DWC_DSTS_RSS_SHIFT 25U

#define	DWC_DSTS_SRE_BIT 0x10000000U

#define	DWC_DSTS_SRE_SHIFT 28U

#define	DWC_DSTS_LNR_BIT 0x20000000U

#define	DWC_DSTS_LNR_SHIFT 29U

Register (DGCMDPARn) for the various commands.
This enum represents the bit fields in the Device Generic Command Parameter
#define	DWC_DGCMD_PER_PARAM_SEL_BITS 0x000003ffU

#define	DWC_DGCMD_PER_PARAM_SEL_SHIFT 0U

#define	DWC_DGCMDPAR_HOST_ROLE_REQ_BITS 0x00000003U

#define	DWC_DGCMDPAR_HOST_ROLE_REQ_SHIFT 0U

#define	DWC_DGCMDPAR_HOST_ROLE_REQ_INITIATE 1U /** @< */

#define	DWC_DGCMDPAR_HOST_ROLE_REQ_CONFIRM 2U

#define	DWC_DGCMDPAR_DEV_NOTIF_TYPE_BITS 0x0000000fU

#define	DWC_DGCMDPAR_DEV_NOTIF_TYPE_SHIFT 0U

#define	DWC_DGCMD_FUNCTION_WAKE_DEV_NOTIF 1U /** @< */

#define	DWC_DGCMD_LATENCY_TOL_DEV_NOTIF 2U /** @< */

#define	DWC_DGCMD_BUS_INTVL_ADJ_DEV_NOTIF 3U /** @< */

#define	DWC_DGCMD_HOST_ROLE_REQ_DEV_NOTIF 4U

#define	DWC_DGCMDPAR_DEV_NOTIF_PARAM_BITS 0xfffffff0U

#define	DWC_DGCMDPAR_DEV_NOTIF_PARAM_SHIFT 4U

#define	DWC_DGCMDPAR_BELT_VALUE_BITS 0x000003ffU

#define	DWC_DGCMDPAR_BELT_VALUE_SHIFT 0U

#define	DWC_DGCMDPAR_BELT_SCALE_BITS 0x00000c00U

#define	DWC_DGCMDPAR_BELT_SCALE_SHIFT 10U

#define	DWC_LATENCY_VALUE_MULT_1024 1U /** @< */

#define	DWC_LATENCY_VALUE_MULT_32768 2U /** @< */

#define	DWC_LATENCY_VALUE_MULT_1048576 3U

Register (DGCMDn).
This enum represents the bit fields in the Device Generic Command
#define	DWC_DGCMD_TYP_BITS 0x0ffU

#define	DWC_DGCMD_TYP_SHIFT 0U

#define	DWC_DGCMD_SET_PERIODIC_PARAMS 2U /** @< */

#define	DWC_DGCMD_XMIT_FUNC_WAKE_DEV_NOTIF 3U /** @< */

#define	DWC_DGCMD_SET_SCRATCHPAD_ARRAY_ADR_LO 4U /** @< */

#define	DWC_DGCMD_SET_SCRATCHPAD_ARRAY_ADR_HI 5U /** @< */

#define	DWC_DGCMD_XMIT_HOST_ROLE_REQUEST 6U /** @< */

#define	DWC_DGCMD_XMIT_DEV_NOTIF 7U /** @< */

#define	DWC_DGCMD_SELECTED_FIFO_FLUSH 9U /** @< */

#define	DWC_DGCMD_ALL_FIFO_FLUSH 10U /** @< */

#define	DWC_DGCMD_SET_EP_NRDY 12U /** @< */

#define	DWC_DGCMD_RUN_SOC_BUS_LOOPBK_TST 16U

#define	DWC_DGCMD_IOC_BIT 0x100U

#define	DWC_DGCMD_IOC_SHIFT 8U

#define	DWC_DGCMD_ACT_BIT 0x400U

#define	DWC_DGCMD_ACT_SHIFT 10U

#define	DWC_DGCMD_STS_BITS 0xf000U

#define	DWC_DGCMD_STS_SHIFT 12U

#define	DWC_DGCMD_STS_ERROR 15U

Register (DEPCMDn).
This enum represents the bit fields in the Device Endpoint Command
#define	DWC_EPCMD_TYP_BITS 0x0ffU

#define	DWC_EPCMD_TYP_SHIFT 0U

#define	DWC_EPCMD_SET_EP_CFG 1U /** @< */

#define	DWC_EPCMD_SET_XFER_CFG 2U /** @< */

#define	DWC_EPCMD_GET_EP_STATE 3U /** @< */

#define	DWC_EPCMD_SET_STALL 4U /** @< */

#define	DWC_EPCMD_CLR_STALL 5U /** @< */

#define	DWC_EPCMD_START_XFER 6U /** @< */

#define	DWC_EPCMD_UPDATE_XFER 7U /** @< */

#define	DWC_EPCMD_END_XFER 8U /** @< */

#define	DWC_EPCMD_START_NEW_CFG 9U

#define	DWC_EPCMD_IOC_BIT 0x100U

#define	DWC_EPCMD_IOC_SHIFT 8U

#define	DWC_EPCMD_ACT_BIT 0x400U

#define	DWC_EPCMD_ACT_SHIFT 10U

#define	DWC_EPCMD_HP_FRM_BIT 0x800U

#define	DWC_EPCMD_HP_FRM_SHIFT 11U

#define	DWC_EPCMD_CMPL_STS_BITS 0xf000U

#define	DWC_EPCMD_CMPL_STS_SHIFT 12U

#define	DWC_EPCMD_STR_NUM_OR_UF_BITS 0xffff0000U

#define	DWC_EPCMD_STR_NUM_OR_UF_SHIFT 16U

#define	DWC_EPCMD_XFER_RSRC_IDX_BITS 0x007f0000U

#define	DWC_EPCMD_XFER_RSRC_IDX_SHIFT 16U

DMA Descriptor Status quadlet
This enum represents the bit fields in the DMA Descriptor Status quadlet.
#define	DWC_DSCSTS_XFRCNT_BITS 0x00ffffffU

#define	DWC_DSCSTS_XFRCNT_SHIFT 0U

#define	DWC_DSCSTS_PCM1_BITS 0x03000000U

#define	DWC_DSCSTS_PCM1_SHIFT 24U

#define	DWC_DSCSTS_TRBRSP_BITS 0xf0000000U

#define	DWC_DSCSTS_TRBRSP_SHIFT 28U

#define	DWC_TRBRSP_MISSED_ISOC_IN 1U /** @< */

#define	DWC_TRBRSP_SETUP_PEND 2U /** @< */

#define	DWC_TRBRSP_XFER_IN_PROG 4U

DMA Descriptor Control quadlet
This enum represents the bit fields in the DMA Descriptor Control quadlet.
#define	DWC_DSCCTL_HWO_BIT 0x00000001U

#define	DWC_DSCCTL_HWO_SHIFT 0U

#define	DWC_DSCCTL_LST_BIT 0x00000002U

#define	DWC_DSCCTL_LST_SHIFT 1U

#define	DWC_DSCCTL_CHN_BIT 0x00000004U

#define	DWC_DSCCTL_CHN_SHIFT 2U

#define	DWC_DSCCTL_CSP_BIT 0x00000008U

#define	DWC_DSCCTL_CSP_SHIFT 3U

#define	DWC_DSCCTL_TRBCTL_BITS 0x000003f0U

#define	DWC_DSCCTL_TRBCTL_SHIFT 4U

#define	DWC_DSCCTL_TRBCTL_NORMAL 1 /** @< */

#define	DWC_DSCCTL_TRBCTL_SETUP 2 /** @< */

#define	DWC_DSCCTL_TRBCTL_STATUS_2 3 /** @< */

#define	DWC_DSCCTL_TRBCTL_STATUS_3 4 /** @< */

#define	DWC_DSCCTL_TRBCTL_CTLDATA_1ST 5 /** @< */

#define	DWC_DSCCTL_TRBCTL_ISOC_1ST 6 /** @< */

#define	DWC_DSCCTL_TRBCTL_ISOC 7 /** @< */

#define	DWC_DSCCTL_TRBCTL_LINK 8

#define	DWC_DSCCTL_ISP_BIT 0x00000400U

#define	DWC_DSCCTL_ISP_SHIFT 10U

#define	DWC_DSCCTL_IMI_BIT DWC_DSCCTL_ISP_BIT

#define	DWC_DSCCTL_IMI_SHIFT DWC_DSCCTL_ISP_SHIFT

#define	DWC_DSCCTL_IOC_BIT 0x00000800U

#define	DWC_DSCCTL_IOC_SHIFT 11U

#define	DWC_DSCCTL_STRMID_SOFN_BITS 0x3fffc000U

#define	DWC_DSCCTL_STRMID_SOFN_SHIFT 14U

Macro Definition Documentation

◆ DWC_SBUSCFG0_HBURSTLEN_BITS

#define DWC_SBUSCFG0_HBURSTLEN_BITS 0x000000ffU

Bit Mask for HBURSTLEN field in GSBUSCFG0 register

◆ DWC_SBUSCFG0_HBURSTLEN_SHIFT

#define DWC_SBUSCFG0_HBURSTLEN_SHIFT 0U

Bit Shift for HBURSTLEN field in GSBUSCFG0 register

◆ DWC_SBUSCFG0_INT_DMA_BURST_SINGLE

#define DWC_SBUSCFG0_INT_DMA_BURST_SINGLE 0U

Single burst length

◆ DWC_SBUSCFG0_INT_DMA_BURST_INCR

#define DWC_SBUSCFG0_INT_DMA_BURST_INCR 1U

Incremental burst length

◆ DWC_SBUSCFG0_INT_DMA_BURST_INCR4

#define DWC_SBUSCFG0_INT_DMA_BURST_INCR4 3U

Incremental burst length of 4

◆ DWC_SBUSCFG0_INT_DMA_BURST_INCR8

#define DWC_SBUSCFG0_INT_DMA_BURST_INCR8 7U

Incremental burst length of 8

◆ DWC_SBUSCFG0_INT_DMA_BURST_INCR16

#define DWC_SBUSCFG0_INT_DMA_BURST_INCR16 15U

Incremental burst length of 16

◆ DWC_SBUSCFG0_INT_DMA_BURST_INCR32

#define DWC_SBUSCFG0_INT_DMA_BURST_INCR32 31U

Incremental burst length of 32

◆ DWC_SBUSCFG0_INT_DMA_BURST_INCR64

#define DWC_SBUSCFG0_INT_DMA_BURST_INCR64 63U

Incremental burst length of 64

◆ DWC_SBUSCFG0_INT_DMA_BURST_INCR128

#define DWC_SBUSCFG0_INT_DMA_BURST_INCR128 127U

Incremental burst length of 128

◆ DWC_SBUSCFG0_INT_DMA_BURST_INCR256

#define DWC_SBUSCFG0_INT_DMA_BURST_INCR256 255U

Incremental burst length of 256

◆ DWC_SBUSCFG0_DES_WR_POST_BIT

#define DWC_SBUSCFG0_DES_WR_POST_BIT 0x00000100U

Descriptor Write is Posted Access: R_W

◆ DWC_SBUSCFG0_DES_WR_POST_SHIFT

#define DWC_SBUSCFG0_DES_WR_POST_SHIFT 8U

◆ DWC_SBUSCFG0_DAT_WR_POST_BIT

#define DWC_SBUSCFG0_DAT_WR_POST_BIT 0x00000200U

Data Write is Posted Access: R_W

◆ DWC_SBUSCFG0_DAT_WR_POST_SHIFT

#define DWC_SBUSCFG0_DAT_WR_POST_SHIFT 9U

◆ DWC_SBUSCFG0_DES_BIG_END_BIT

#define DWC_SBUSCFG0_DES_BIG_END_BIT 0x00000400U

Descriptor Access is Big-Endian Access: R_W

◆ DWC_SBUSCFG0_DES_BIG_END_SHIFT

#define DWC_SBUSCFG0_DES_BIG_END_SHIFT 10U

◆ DWC_SBUSCFG0_DAT_BIG_END_BIT

#define DWC_SBUSCFG0_DAT_BIG_END_BIT 0x00000800U

Data Access is Big-Endian Access: R_W

◆ DWC_SBUSCFG0_DAT_BIG_END_SHIFT

#define DWC_SBUSCFG0_DAT_BIG_END_SHIFT 11U

◆ DWC_SBUSCFG0_STORE_AND_FORWARD_BIT

#define DWC_SBUSCFG0_STORE_AND_FORWARD_BIT 0x00001000U

Store and Forward Mode Access: R_W

◆ DWC_SBUSCFG0_STORE_AND_FORWARD_SHIFT

#define DWC_SBUSCFG0_STORE_AND_FORWARD_SHIFT 12U

◆ DWC_SBUSCFG0_SING_REQ_BIT

#define DWC_SBUSCFG0_SING_REQ_BIT 0x00004000U

Force Single Request Access: R_W

◆ DWC_SBUSCFG0_SING_REQ_SHIFT

#define DWC_SBUSCFG0_SING_REQ_SHIFT 14U

◆ DWC_SBUSCFG0_READ_AFTER_WRITE_BIT

#define DWC_SBUSCFG0_READ_AFTER_WRITE_BIT 0x00008000U

Descriptor Readback Enable Access: R_W

◆ DWC_SBUSCFG0_READ_AFTER_WRITE_SHIFT

#define DWC_SBUSCFG0_READ_AFTER_WRITE_SHIFT 15U

◆ DWC_SBUSCFG0_DES_WR_REQ_INFO_BITS

#define DWC_SBUSCFG0_DES_WR_REQ_INFO_BITS 0x000f0000U

Descriptor Write Request Info Access: R_W

◆ DWC_SBUSCFG0_DES_WR_REQ_INFO_SHIFT

#define DWC_SBUSCFG0_DES_WR_REQ_INFO_SHIFT 16U

◆ DWC_SBUSCFG0_DAT_WR_REQ_INFO_BITS

#define DWC_SBUSCFG0_DAT_WR_REQ_INFO_BITS 0x00f00000U

Data Write Request Info Access: R_W

◆ DWC_SBUSCFG0_DAT_WR_REQ_INFO_SHIFT

#define DWC_SBUSCFG0_DAT_WR_REQ_INFO_SHIFT 20U

◆ DWC_SBUSCFG0_DES_RD_REQ_INFO_BITS

#define DWC_SBUSCFG0_DES_RD_REQ_INFO_BITS 0x0f000000U

Descriptor Read Request Info Access: R_W

◆ DWC_SBUSCFG0_DES_RD_REQ_INFO_SHIFT

#define DWC_SBUSCFG0_DES_RD_REQ_INFO_SHIFT 24U

◆ DWC_SBUSCFG0_DAT_RD_REQ_INFO_BITS

#define DWC_SBUSCFG0_DAT_RD_REQ_INFO_BITS 0xf0000000U

Data Read Request Info Access: R_W

◆ DWC_SBUSCFG0_DAT_RD_REQ_INFO_SHIFT

#define DWC_SBUSCFG0_DAT_RD_REQ_INFO_SHIFT 28U

◆ DWC_SBUSCFG1_DES_ADDR_SPC_BITS

#define DWC_SBUSCFG1_DES_ADDR_SPC_BITS 0x0000000fU

OCP Address Space For Descriptor Access: R_W

◆ DWC_SBUSCFG1_DES_ADDR_SPC_SHIFT

#define DWC_SBUSCFG1_DES_ADDR_SPC_SHIFT 0U

◆ DWC_SBUSCFG1_DAT_ADDR_SPC_BITS

#define DWC_SBUSCFG1_DAT_ADDR_SPC_BITS 0x000000f0U

OCP Address Space For Data Access: R_W

◆ DWC_SBUSCFG1_DAT_ADDR_SPC_SHIFT

#define DWC_SBUSCFG1_DAT_ADDR_SPC_SHIFT 4U

◆ DWC_TXTHRCTL_USB_MAX_TX_BURST_SIZE_BITS

#define DWC_TXTHRCTL_USB_MAX_TX_BURST_SIZE_BITS 0x00ff0000U

Maximum Tx Burst Size Access: R_W

◆ DWC_TXTHRCTL_USB_MAX_TX_BURST_SIZE_SHIFT

#define DWC_TXTHRCTL_USB_MAX_TX_BURST_SIZE_SHIFT 16U

◆ DWC_TXTHRCTL_USB_TX_PKT_CNT_BITS

#define DWC_TXTHRCTL_USB_TX_PKT_CNT_BITS 0x1f000000U

Tx Multi-Packet Threshold Count Access: R_W

◆ DWC_TXTHRCTL_USB_TX_PKT_CNT_SHIFT

#define DWC_TXTHRCTL_USB_TX_PKT_CNT_SHIFT 24U

◆ DWC_TXTHRCTL_USB_TX_PKT_CNT_EN_BIT

#define DWC_TXTHRCTL_USB_TX_PKT_CNT_EN_BIT 0x20000000U

Tx Multi-Packet Threshold Enable Access: R_W

◆ DWC_TXTHRCTL_USB_TX_PKT_CNT_EN_SHIFT

#define DWC_TXTHRCTL_USB_TX_PKT_CNT_EN_SHIFT 29U

◆ DWC_RXTHRCTL_USB_MAX_RX_BURST_SIZE_BITS

#define DWC_RXTHRCTL_USB_MAX_RX_BURST_SIZE_BITS 0x00f80000U

Maximum Rx Burst Size Access: R_W

◆ DWC_RXTHRCTL_USB_MAX_RX_BURST_SIZE_SHIFT

#define DWC_RXTHRCTL_USB_MAX_RX_BURST_SIZE_SHIFT 19U

◆ DWC_RXTHRCTL_USB_RX_PKT_CNT_BITS

#define DWC_RXTHRCTL_USB_RX_PKT_CNT_BITS 0x0f000000U

Rx Multi-Packet Threshold Count Access: R_W

◆ DWC_RXTHRCTL_USB_RX_PKT_CNT_SHIFT

#define DWC_RXTHRCTL_USB_RX_PKT_CNT_SHIFT 24U

◆ DWC_RXTHRCTL_USB_RX_PKT_CNT_EN_BIT

#define DWC_RXTHRCTL_USB_RX_PKT_CNT_EN_BIT 0x20000000U

Rx Multi-Packet Threshold Enable Access: R_W

◆ DWC_RXTHRCTL_USB_RX_PKT_CNT_EN_SHIFT

#define DWC_RXTHRCTL_USB_RX_PKT_CNT_EN_SHIFT 29U

◆ DWC_GCTL_DSBL_CLCK_GTNG_BIT

#define DWC_GCTL_DSBL_CLCK_GTNG_BIT 0x00000001U

Disable Clock Gating Access: R_W

◆ DWC_GCTL_DSBL_CLCK_GTNG_SHIFT

#define DWC_GCTL_DSBL_CLCK_GTNG_SHIFT 0U

◆ DWC_GCTL_GBL_HIBER_EN_BIT

#define DWC_GCTL_GBL_HIBER_EN_BIT 0x00000002U

Global Hibernation Enable Access: R_W

◆ DWC_GCTL_GBL_HIBER_EN_SHIFT

#define DWC_GCTL_GBL_HIBER_EN_SHIFT 1U

◆ DWC_GCTL_DIS_SCRAMBLE_BIT

#define DWC_GCTL_DIS_SCRAMBLE_BIT 0x00000008U

Disable Scrambling Access: R_W

◆ DWC_GCTL_DIS_SCRAMBLE_SHIFT

#define DWC_GCTL_DIS_SCRAMBLE_SHIFT 3U

◆ DWC_GCTL_SCALE_DOWN_BITS

#define DWC_GCTL_SCALE_DOWN_BITS 0x00000030U

Scale-down Mode Access: R_W

◆ DWC_GCTL_SCALE_DOWN_SHIFT

#define DWC_GCTL_SCALE_DOWN_SHIFT 4U

◆ DWC_GCTL_RAM_CLK_SEL_BITS

#define DWC_GCTL_RAM_CLK_SEL_BITS 0x000000c0U

RAM Clock Select Access: R_W

◆ DWC_GCTL_RAM_CLK_SEL_SHIFT

#define DWC_GCTL_RAM_CLK_SEL_SHIFT 6U

◆ DWC_GCTL_DEBUG_ATTACH_BIT

#define DWC_GCTL_DEBUG_ATTACH_BIT 0x00000100U

Debug Attach Access: R_W

◆ DWC_GCTL_DEBUG_ATTACH_SHIFT

#define DWC_GCTL_DEBUG_ATTACH_SHIFT 8U

◆ DWC_GCTL_U1U2_TIMER_SCALE_BIT

#define DWC_GCTL_U1U2_TIMER_SCALE_BIT 0x00000200U

Disable U1/U2 Timer Scaledown Access: R_W

◆ DWC_GCTL_U1U2_TIMER_SCALE_SHIFT

#define DWC_GCTL_U1U2_TIMER_SCALE_SHIFT 9U

◆ DWC_GCTL_SOFITPSYNC_BIT

#define DWC_GCTL_SOFITPSYNC_BIT 0x00000400U

SOF ITP SYNC Access: R_W

◆ DWC_GCTL_SOFITPSYNC_SHIFT

#define DWC_GCTL_SOFITPSYNC_SHIFT 10U

◆ DWC_GCTL_CORE_SOFT_RST_BIT

#define DWC_GCTL_CORE_SOFT_RST_BIT 0x00000800U

Core Soft Reset Access: R_W

◆ DWC_GCTL_CORE_SOFT_RST_SHIFT

#define DWC_GCTL_CORE_SOFT_RST_SHIFT 11U

◆ DWC_GCTL_PRT_CAP_DIR_BITS

#define DWC_GCTL_PRT_CAP_DIR_BITS 0x00003000U

Port Capability Direction Access: R_W

◆ DWC_GCTL_PRT_CAP_DIR_SHIFT

#define DWC_GCTL_PRT_CAP_DIR_SHIFT 12U

◆ DWC_GCTL_PRT_CAP_HOST

#define DWC_GCTL_PRT_CAP_HOST 1U

Port Capability Values

◆ DWC_GCTL_PRT_CAP_DEVICE

#define DWC_GCTL_PRT_CAP_DEVICE 2U

◆ DWC_GCTL_PRT_CAP_OTG

#define DWC_GCTL_PRT_CAP_OTG 3U

◆ DWC_GCTL_FRMSCLDWN_BITS

#define DWC_GCTL_FRMSCLDWN_BITS 0x0000c000U

Frame Scale Down Access: R_W

◆ DWC_GCTL_FRMSCLDWN_SHIFT

#define DWC_GCTL_FRMSCLDWN_SHIFT 14U

◆ DWC_GCTL_U2RSTECN_BIT

#define DWC_GCTL_U2RSTECN_BIT 0x00010000U

U2 Reset ECN Access: R_W

◆ DWC_GCTL_U2RSTECN_SHIFT

#define DWC_GCTL_U2RSTECN_SHIFT 16U

◆ DWC_GCTL_BYPSSETADDR_BIT

#define DWC_GCTL_BYPSSETADDR_BIT 0x00020000U

Bypass SetAddress Access: R_W

◆ DWC_GCTL_BYPSSETADDR_SHIFT

#define DWC_GCTL_BYPSSETADDR_SHIFT 17U

◆ DWC_GCTL_MASTERFILTBYPASS_BIT

#define DWC_GCTL_MASTERFILTBYPASS_BIT 0x00040000U

Master Filter Bypass Access: R_W

◆ DWC_GCTL_MASTERFILTBYPASS_SHIFT

#define DWC_GCTL_MASTERFILTBYPASS_SHIFT 18U

◆ DWC_GCTL_PWR_DN_SCALE_BITS

#define DWC_GCTL_PWR_DN_SCALE_BITS 0xfff80000U

Power Down Scale Access: R_W

◆ DWC_GCTL_PWR_DN_SCALE_SHIFT

#define DWC_GCTL_PWR_DN_SCALE_SHIFT 19U

◆ DWC_GEVTEN_ULPI_CK_EVT_EN_BIT

#define DWC_GEVTEN_ULPI_CK_EVT_EN_BIT 0x00000001U

ULPI Carkit Event Enable Access: R_W

◆ DWC_GEVTEN_ULPI_CK_EVT_SHIFT

#define DWC_GEVTEN_ULPI_CK_EVT_SHIFT 0U

◆ DWC_GEVTEN_I2C_EVT_EN_BIT

#define DWC_GEVTEN_I2C_EVT_EN_BIT 0x00000002U

I2C Event Enable Access: R_W

◆ DWC_GEVTEN_I2C_EVT_EN_SHIFT

#define DWC_GEVTEN_I2C_EVT_EN_SHIFT 1U

◆ DWC_GSTS_CURMODE_BITS

#define DWC_GSTS_CURMODE_BITS 0x00000003U

Current Mode Access: RO.

0: Device Mode
1: Host Mode
2: DRD Mode

◆ DWC_GSTS_CURMODE_SHIFT

#define DWC_GSTS_CURMODE_SHIFT 0U

◆ DWC_GSTS_DEVICE_MODE

#define DWC_GSTS_DEVICE_MODE 0U

◆ DWC_GSTS_HOST_MODE

#define DWC_GSTS_HOST_MODE 1U

◆ DWC_GSTS_DRD_MODE

#define DWC_GSTS_DRD_MODE 2U

◆ DWC_GSTS_BUS_ERR_ADDR_VLD_BIT

#define DWC_GSTS_BUS_ERR_ADDR_VLD_BIT 0x00000010U

Bus Error Address Valid Access: RO

◆ DWC_GSTS_BUS_ERR_ADDR_VLD_SHIFT

#define DWC_GSTS_BUS_ERR_ADDR_VLD_SHIFT 4U

◆ DWC_GSTS_CSR_TIMEOUT_BIT

#define DWC_GSTS_CSR_TIMEOUT_BIT 0x00000020U

CSR Timeout

◆ DWC_GSTS_CSR_TIMEOUT_SHIFT

#define DWC_GSTS_CSR_TIMEOUT_SHIFT 5U

◆ DWC_GSTS_DEV_EVT_PENDING_BIT

#define DWC_GSTS_DEV_EVT_PENDING_BIT 0x00000040U

Device Interrupt Pending

◆ DWC_GSTS_DEV_EVT_PENDING_SHIFT

#define DWC_GSTS_DEV_EVT_PENDING_SHIFT 6U

◆ DWC_GSTS_HOST_EVT_PENDING_BIT

#define DWC_GSTS_HOST_EVT_PENDING_BIT 0x00000080U

Host Interrupt Pending

◆ DWC_GSTS_HOST_EVT_PENDING_SHIFT

#define DWC_GSTS_HOST_EVT_PENDING_SHIFT 7U

◆ DWC_GSTS_ADP_EVT_PENDING_BIT

#define DWC_GSTS_ADP_EVT_PENDING_BIT 0x00000100U

ADP Interrupt Pending

◆ DWC_GSTS_ADP_EVT_PENDING_SHIFT

#define DWC_GSTS_ADP_EVT_PENDING_SHIFT 8U

◆ DWC_GSTS_BC_EVT_PENDING_BIT

#define DWC_GSTS_BC_EVT_PENDING_BIT 0x00000200U

BC Interrupt Pending

◆ DWC_GSTS_BC_EVT_PENDING_SHIFT

#define DWC_GSTS_BC_EVT_PENDING_SHIFT 9U

◆ DWC_GSTS_OTG_EVT_PENDING_BIT

#define DWC_GSTS_OTG_EVT_PENDING_BIT 0x00000400U

OTG Interrupt Pending

◆ DWC_GSTS_OTG_EVT_PENDING_SHIFT

#define DWC_GSTS_OTG_EVT_PENDING_SHIFT 10U

◆ DWC_GSTS_SSIC_IP_BIT

#define DWC_GSTS_SSIC_IP_BIT 0x00000800U

SSIC Interrupt Pending

◆ DWC_GSTS_SSIC_IP_SHIFT

#define DWC_GSTS_SSIC_IP_SHIFT 11U

◆ DWC_GSTS_CBELT_BITS

#define DWC_GSTS_CBELT_BITS 0xfff00000U

Current BELT Value Access: RO

◆ DWC_GSTS_CBELT_SHIFT

#define DWC_GSTS_CBELT_SHIFT 20U

◆ DWC_HWP0_MODE_BITS

#define DWC_HWP0_MODE_BITS 0x00000007U

◆ DWC_HWP0_MODE_SHIFT

#define DWC_HWP0_MODE_SHIFT 0U

◆ DWC_HWP0_MBUS_TYPE_BITS

#define DWC_HWP0_MBUS_TYPE_BITS 0x00000038U

◆ DWC_HWP0_MBUS_TYPE_SHIFT

#define DWC_HWP0_MBUS_TYPE_SHIFT 3U

◆ DWC_HWP0_SBUS_TYPE_BITS

#define DWC_HWP0_SBUS_TYPE_BITS 0x000000c0U

◆ DWC_HWP0_SBUS_TYPE_SHIFT

#define DWC_HWP0_SBUS_TYPE_SHIFT 6U

◆ DWC_HWP0_MDWIDTH_BITS

#define DWC_HWP0_MDWIDTH_BITS 0x0000ff00U

◆ DWC_HWP0_MDWIDTH_SHIFT

#define DWC_HWP0_MDWIDTH_SHIFT 8U

◆ DWC_HWP0_SDWIDTH_BITS

#define DWC_HWP0_SDWIDTH_BITS 0x00ff0000U

◆ DWC_HWP0_SDWIDTH_SHIFT

#define DWC_HWP0_SDWIDTH_SHIFT 16U

◆ DWC_HWP0_AWIDTH_BITS

#define DWC_HWP0_AWIDTH_BITS 0x3f000000U

◆ DWC_HWP0_AWIDTH_SHIFT

#define DWC_HWP0_AWIDTH_SHIFT 24U

◆ DWC_HWP1_IDWIDTH_M1_BITS

#define DWC_HWP1_IDWIDTH_M1_BITS 0x00000007U

◆ DWC_HWP1_IDWIDTH_M1_SHIFT

#define DWC_HWP1_IDWIDTH_M1_SHIFT 0U

◆ DWC_HWP1_BURSTWIDTH_M1_BITS

#define DWC_HWP1_BURSTWIDTH_M1_BITS 0x00000038U

◆ DWC_HWP1_BURSTWIDTH_M1_SHIFT

#define DWC_HWP1_BURSTWIDTH_M1_SHIFT 3U

◆ DWC_HWP1_DATAINFOWIDTH_BITS

#define DWC_HWP1_DATAINFOWIDTH_BITS 0x000001c0U

◆ DWC_HWP1_DATAINFOWIDTH_SHIFT

#define DWC_HWP1_DATAINFOWIDTH_SHIFT 6U

◆ DWC_HWP1_REQINFOWIDTH_BITS

#define DWC_HWP1_REQINFOWIDTH_BITS 0x00000e00U

◆ DWC_HWP1_REQINFOWIDTH_SHIFT

#define DWC_HWP1_REQINFOWIDTH_SHIFT 9U

◆ DWC_HWP1_ASPACEWIDTH_BITS

#define DWC_HWP1_ASPACEWIDTH_BITS 0x00007000U

◆ DWC_HWP1_ASPACEWIDTH_SHIFT

#define DWC_HWP1_ASPACEWIDTH_SHIFT 12U

◆ DWC_HWP1_DEV_NUM_INT_BITS

#define DWC_HWP1_DEV_NUM_INT_BITS 0x001f8000U

◆ DWC_HWP1_DEV_NUM_INT_SHIFT

#define DWC_HWP1_DEV_NUM_INT_SHIFT 15U

◆ DWC_HWP1_NUM_RAMS_BITS

#define DWC_HWP1_NUM_RAMS_BITS 0x00600000U

◆ DWC_HWP1_NUM_RAMS_SHIFT

#define DWC_HWP1_NUM_RAMS_SHIFT 21U

◆ DWC_HWP1_SPRAM_TYP_BIT

#define DWC_HWP1_SPRAM_TYP_BIT 0x00800000U

◆ DWC_HWP1_SPRAM_TYP_SHIFT

#define DWC_HWP1_SPRAM_TYP_SHIFT 23U

◆ DWC_HWP1_EN_PWROPT_BITS

#define DWC_HWP1_EN_PWROPT_BITS 0x03000000U

◆ DWC_HWP1_EN_PWROPT_SHIFT

#define DWC_HWP1_EN_PWROPT_SHIFT 24U

◆ DWC_EN_PWROPT_NONE

#define DWC_EN_PWROPT_NONE 0U

◆ DWC_EN_PWROPT_CLK_GATING_ONLY

#define DWC_EN_PWROPT_CLK_GATING_ONLY 1U

◆ DWC_EN_PWROPT_HIBERNATION

#define DWC_EN_PWROPT_HIBERNATION 2U

◆ DWC_HWP1_MAC_PHY_CLKS_SYNC_BIT

#define DWC_HWP1_MAC_PHY_CLKS_SYNC_BIT 0x04000000U

◆ DWC_HWP1_MAC_PHY_CLKS_SYNC_SHIFT

#define DWC_HWP1_MAC_PHY_CLKS_SYNC_SHIFT 26U

◆ DWC_HWP1_MAC_RAM_CLKS_SYNC_BIT

#define DWC_HWP1_MAC_RAM_CLKS_SYNC_BIT 0x08000000U

◆ DWC_HWP1_MAC_RAM_CLKS_SYNC_SHIFT

#define DWC_HWP1_MAC_RAM_CLKS_SYNC_SHIFT 27U

◆ DWC_HWP1_RAM_BUS_CLKS_SYNC_BIT

#define DWC_HWP1_RAM_BUS_CLKS_SYNC_BIT 0x10000000U

◆ DWC_HWP1_RAM_BUS_CLKS_SYNC_SHIFT

#define DWC_HWP1_RAM_BUS_CLKS_SYNC_SHIFT 28U

◆ DWC_HWP1_RM_OPT_FEATURES_BIT

#define DWC_HWP1_RM_OPT_FEATURES_BIT 0x40000000U

◆ DWC_HWP1_RM_OPT_FEATURES_SHIFT

#define DWC_HWP1_RM_OPT_FEATURES_SHIFT 30U

◆ DWC_HWP2_USERID_BITS

#define DWC_HWP2_USERID_BITS 0xffffffffU

◆ DWC_HWP2_USERID_SHIFT

#define DWC_HWP2_USERID_SHIFT 0U

◆ DWC_HWP3_SSPHY_IFC_BITS

#define DWC_HWP3_SSPHY_IFC_BITS 0x00000003U

◆ DWC_HWP3_SSPHY_IFC_SHIFT

#define DWC_HWP3_SSPHY_IFC_SHIFT 0U

◆ DWC_HWP3_HSPHY_IFC_BITS

#define DWC_HWP3_HSPHY_IFC_BITS 0x0000000cU

◆ DWC_HWP3_HSPHY_IFC_SHIFT

#define DWC_HWP3_HSPHY_IFC_SHIFT 2U

◆ DWC_HWP3_FSPHY_IFC_BITS

#define DWC_HWP3_FSPHY_IFC_BITS 0x00000030U

◆ DWC_HWP3_FSPHY_IFC_SHIFT

#define DWC_HWP3_FSPHY_IFC_SHIFT 4U

◆ DWC_HWP3_HSPHY_DWIDTH_BITS

#define DWC_HWP3_HSPHY_DWIDTH_BITS 0x000000c0U

◆ DWC_HWP3_HSPHY_DWIDTH_SHIFT

#define DWC_HWP3_HSPHY_DWIDTH_SHIFT 6U

◆ DWC_HWP3_VEND_CTL_IFC_BIT

#define DWC_HWP3_VEND_CTL_IFC_BIT 0x00000400U

◆ DWC_HWP3_VEND_CTL_IFC_SHIFT

#define DWC_HWP3_VEND_CTL_IFC_SHIFT 10U

◆ DWC_HWP3_ULPI_CARKIT_BIT

#define DWC_HWP3_ULPI_CARKIT_BIT 0x00000800U

◆ DWC_HWP3_ULPI_CARKIT_SHIFT

#define DWC_HWP3_ULPI_CARKIT_SHIFT 11U

◆ DWC_HWP3_NUM_EPS_BITS

#define DWC_HWP3_NUM_EPS_BITS 0x0003f000U

◆ DWC_HWP3_NUM_EPS_SHIFT

#define DWC_HWP3_NUM_EPS_SHIFT 12U

◆ DWC_HWP3_NUM_IN_EPS_BITS

#define DWC_HWP3_NUM_IN_EPS_BITS 0x007c0000U

◆ DWC_HWP3_NUM_IN_EPS_SHIFT

#define DWC_HWP3_NUM_IN_EPS_SHIFT 18U

◆ DWC_HWP3_TOT_XFR_RSRC_BITS

#define DWC_HWP3_TOT_XFR_RSRC_BITS 0x7f800000U

◆ DWC_HWP3_TOT_XFR_RSRC_SHIFT

#define DWC_HWP3_TOT_XFR_RSRC_SHIFT 23U

◆ DWC_HWP4_TRBS_PER_XFER_BITS

#define DWC_HWP4_TRBS_PER_XFER_BITS 0x0000003fU

◆ DWC_HWP4_TRBS_PER_XFER_SHIFT

#define DWC_HWP4_TRBS_PER_XFER_SHIFT 0U

◆ DWC_HWP4_HIBER_SPAD_BITS

#define DWC_HWP4_HIBER_SPAD_BITS 0x0001e000U

◆ DWC_HWP4_HIBER_SPAD_SHIFT

#define DWC_HWP4_HIBER_SPAD_SHIFT 13U

◆ DWC_HWP4_NUM_SS_USB_INST_BITS

#define DWC_HWP4_NUM_SS_USB_INST_BITS 0x001e0000U

◆ DWC_HWP4_NUM_SS_USB_INST_SHIFT

#define DWC_HWP4_NUM_SS_USB_INST_SHIFT 17U

◆ DWC_HWP4_EN_ISOC_SUPT_BIT

#define DWC_HWP4_EN_ISOC_SUPT_BIT 0x00800000U

◆ DWC_HWP4_EN_ISOC_SUPT_SHIFT

#define DWC_HWP4_EN_ISOC_SUPT_SHIFT 23U

◆ DWC_HWP4_BMU_PTL_DEPTH_BITS

#define DWC_HWP4_BMU_PTL_DEPTH_BITS 0x0f000000U

◆ DWC_HWP4_BMU_PTL_DEPTH_SHIFT

#define DWC_HWP4_BMU_PTL_DEPTH_SHIFT 24U

◆ DWC_HWP4_BMU_LSP_DEPTH_BITS

#define DWC_HWP4_BMU_LSP_DEPTH_BITS 0xf0000000U

◆ DWC_HWP4_BMU_LSP_DEPTH_SHIFT

#define DWC_HWP4_BMU_LSP_DEPTH_SHIFT 28U

◆ DWC_HWP5_BMU_BUSGM_DEPTH_BITS

#define DWC_HWP5_BMU_BUSGM_DEPTH_BITS 0x0000000fU

◆ DWC_HWP5_BMU_BUSGM_DEPTH_SHIFT

#define DWC_HWP5_BMU_BUSGM_DEPTH_SHIFT 0U

◆ DWC_HWP5_RXQ_FIFO_DEPTH_BITS

#define DWC_HWP5_RXQ_FIFO_DEPTH_BITS 0x000003f0U

◆ DWC_HWP5_RXQ_FIFO_DEPTH_SHIFT

#define DWC_HWP5_RXQ_FIFO_DEPTH_SHIFT 4U

◆ DWC_HWP5_TXQ_FIFO_DEPTH_BITS

#define DWC_HWP5_TXQ_FIFO_DEPTH_BITS 0x0000fc00U

◆ DWC_HWP5_TXQ_FIFO_DEPTH_SHIFT

#define DWC_HWP5_TXQ_FIFO_DEPTH_SHIFT 10U

◆ DWC_HWP5_DWQ_FIFO_DEPTH_BITS

#define DWC_HWP5_DWQ_FIFO_DEPTH_BITS 0x003f0000U

◆ DWC_HWP5_DWQ_FIFO_DEPTH_SHIFT

#define DWC_HWP5_DWQ_FIFO_DEPTH_SHIFT 16U

◆ DWC_HWP5_DFQ_FIFO_DEPTH_BITS

#define DWC_HWP5_DFQ_FIFO_DEPTH_BITS 0x0fc00000U

◆ DWC_HWP5_DFQ_FIFO_DEPTH_SHIFT

#define DWC_HWP5_DFQ_FIFO_DEPTH_SHIFT 22U

◆ DWC_HWP6_PSQ_FIFO_DEPTH_BITS

#define DWC_HWP6_PSQ_FIFO_DEPTH_BITS 0x0000003fU

◆ DWC_HWP6_PSQ_FIFO_DEPTH_SHIFT

#define DWC_HWP6_PSQ_FIFO_DEPTH_SHIFT 0U

◆ DWC_HWP6_EN_DBG_PORTS_BIT

#define DWC_HWP6_EN_DBG_PORTS_BIT 0x00000040U

◆ DWC_HWP6_EN_DBG_PORTS_SHIFT

#define DWC_HWP6_EN_DBG_PORTS_SHIFT 6U

◆ DWC_HWP6_EN_FPGA_BIT

#define DWC_HWP6_EN_FPGA_BIT 0x00000080U

◆ DWC_HWP6_EN_FPGA_SHIFT

#define DWC_HWP6_EN_FPGA_SHIFT 7U

◆ DWC_HWP6_EN_SRP_BIT

#define DWC_HWP6_EN_SRP_BIT 0x00000400U

◆ DWC_HWP6_EN_SRP_SHIFT

#define DWC_HWP6_EN_SRP_SHIFT 10U

◆ DWC_HWP6_EN_HNP_BIT

#define DWC_HWP6_EN_HNP_BIT 0x00000800U

◆ DWC_HWP6_EN_HNP_SHIFT

#define DWC_HWP6_EN_HNP_SHIFT 11U

◆ DWC_HWP6_EN_ADP_BIT

#define DWC_HWP6_EN_ADP_BIT 0x00001000U

◆ DWC_HWP6_EN_ADP_SHIFT

#define DWC_HWP6_EN_ADP_SHIFT 12U

◆ DWC_HWP6_EN_OTG_BIT

#define DWC_HWP6_EN_OTG_BIT 0x00002000U

◆ DWC_HWP6_EN_OTG_SHIFT

#define DWC_HWP6_EN_OTG_SHIFT 13U

◆ DWC_HWP6_EN_BC_BIT

#define DWC_HWP6_EN_BC_BIT 0x00004000U

◆ DWC_HWP6_EN_BC_SHIFT

#define DWC_HWP6_EN_BC_SHIFT 14U

◆ DWC_HWP6_EN_BUS_FILTERS_BIT

#define DWC_HWP6_EN_BUS_FILTERS_BIT 0x00008000U

◆ DWC_HWP6_EN_BUS_FILTERS_SHIFT

#define DWC_HWP6_EN_BUS_FILTERS_SHIFT 15U

◆ DWC_HWP6_RAM0_DEPTH_BITS

#define DWC_HWP6_RAM0_DEPTH_BITS 0xffff0000U

◆ DWC_HWP6_RAM0_DEPTH_SHIFT

#define DWC_HWP6_RAM0_DEPTH_SHIFT 16U

◆ DWC_HWP7_RAM1_DEPTH_BITS

#define DWC_HWP7_RAM1_DEPTH_BITS 0x0000ffffU

◆ DWC_HWP7_RAM1_DEPTH_SHIFT

#define DWC_HWP7_RAM1_DEPTH_SHIFT 0U

◆ DWC_HWP7_RAM2_DEPTH_BITS

#define DWC_HWP7_RAM2_DEPTH_BITS 0xffff0000U

◆ DWC_HWP7_RAM2_DEPTH_SHIFT

#define DWC_HWP7_RAM2_DEPTH_SHIFT 16U

◆ DWC_HWP8_DCACHE_DEPTH_BITS

#define DWC_HWP8_DCACHE_DEPTH_BITS 0xffffffffU

◆ DWC_HWP8_DCACHE_DEPTH_SHIFT

#define DWC_HWP8_DCACHE_DEPTH_SHIFT 0U

◆ DWC_DBGFIFOSPACE_FIFO_QUEUE_SEL_BITS

#define DWC_DBGFIFOSPACE_FIFO_QUEUE_SEL_BITS 0x000000ffU

FIFO/Queue Select Access: R_W

◆ DWC_DBGFIFOSPACE_FIFO_QUEUE_SEL_SHIFT

#define DWC_DBGFIFOSPACE_FIFO_QUEUE_SEL_SHIFT 0U

◆ DWC_DBGFIFOSPACE_SPACE_AVAIL_BITS

#define DWC_DBGFIFOSPACE_SPACE_AVAIL_BITS 0xffff0000U

Space Available Access: R

◆ DWC_DBGFIFOSPACE_SPACE_AVAIL_SHIFT

#define DWC_DBGFIFOSPACE_SPACE_AVAIL_SHIFT 16U

◆ DWC_DBGLTSSM_PIPE_STATUS_BITS

#define DWC_DBGLTSSM_PIPE_STATUS_BITS 0x0003ffffU

Pipe Status Access: R

◆ DWC_DBGLTSSM_PIPE_STATUS_SHIFT

#define DWC_DBGLTSSM_PIPE_STATUS_SHIFT 0U

◆ DWC_DBGLTSSM_LTDB_SUB_STATE_BITS

#define DWC_DBGLTSSM_LTDB_SUB_STATE_BITS 0x003c0000U

LTDB SubState Access: R

◆ DWC_DBGLTSSM_LTDB_SUB_STATE_SHIFT

#define DWC_DBGLTSSM_LTDB_SUB_STATE_SHIFT 18U

◆ DWC_DBGLTSSM_LTDB_STATE_BITS

#define DWC_DBGLTSSM_LTDB_STATE_BITS 0x03c00000U

LTDB State Access: R

◆ DWC_DBGLTSSM_LTDB_STATE_SHIFT

#define DWC_DBGLTSSM_LTDB_STATE_SHIFT 22U

◆ DWC_DBGLTSSM_LTDB_TIMEOUT_BIT

#define DWC_DBGLTSSM_LTDB_TIMEOUT_BIT 0x04000000U

LTDB Timeout Access: R

◆ DWC_DBGLTSSM_LTDB_TIMEOUT_SHIFT

#define DWC_DBGLTSSM_LTDB_TIMEOUT_SHIFT 26U

◆ DWC_RMMICTL_MPHY_STATE_BITS

#define DWC_RMMICTL_MPHY_STATE_BITS 0x0e000000U

This enum represents the bit fields of the Core RMMI PHY Control Registers (GUSB3RMMICTLn).

◆ DWC_RMMICTL_MPHY_STATE_SHIFT

#define DWC_RMMICTL_MPHY_STATE_SHIFT 25U

◆ DWC_MPHY_STATE_DISABLED

#define DWC_MPHY_STATE_DISABLED 0U

◆ DWC_MPHY_STATE_HIBERN8

#define DWC_MPHY_STATE_HIBERN8 1U

◆ DWC_MPHY_STATE_SLEEP

#define DWC_MPHY_STATE_SLEEP 2U

◆ DWC_MPHY_STATE_STALL

#define DWC_MPHY_STATE_STALL 3U

◆ DWC_MPHY_STATE_PWM_BURST

#define DWC_MPHY_STATE_PWM_BURST 4U

◆ DWC_MPHY_STATE_HS_BURST

#define DWC_MPHY_STATE_HS_BURST 5U

◆ DWC_MPHY_STATE_LINE_CFG

#define DWC_MPHY_STATE_LINE_CFG 6U

◆ DWC_MPHY_STATE_LINE_RESET

#define DWC_MPHY_STATE_LINE_RESET 7U

◆ DWC_RMMICTL_AUTO_EXIT_RRAP_BIT

#define DWC_RMMICTL_AUTO_EXIT_RRAP_BIT 0x10000000U

◆ DWC_RMMICTL_AUTO_EXIT_RRAP_SHIFT

#define DWC_RMMICTL_AUTO_EXIT_RRAP_SHIFT 28U

◆ DWC_RMMICTL_AUTO_ROM_RRAP_BIT

#define DWC_RMMICTL_AUTO_ROM_RRAP_BIT 0x20000000U

◆ DWC_RMMICTL_AUTO_ROM_RRAP_SHIFT

#define DWC_RMMICTL_AUTO_ROM_RRAP_SHIFT 29U

◆ DWC_RMMICTL_AUTO_EXIT_H8_BIT

#define DWC_RMMICTL_AUTO_EXIT_H8_BIT 0x40000000U

◆ DWC_RMMICTL_AUTO_EXIT_H8_SHIFT

#define DWC_RMMICTL_AUTO_EXIT_H8_SHIFT 30U

◆ DWC_RMMICTL_AUTO_ROM_H8_BIT

#define DWC_RMMICTL_AUTO_ROM_H8_BIT 0x80000000U

◆ DWC_RMMICTL_AUTO_ROM_H8_SHIFT

#define DWC_RMMICTL_AUTO_ROM_H8_SHIFT 31U

◆ DWC_USB2PHYCFG_TOUT_CAL_BITS

#define DWC_USB2PHYCFG_TOUT_CAL_BITS 0x00000007U

HS/FS Timeout Calibration Access: R_W

◆ DWC_USB2PHYCFG_TOUT_CAL_SHIFT

#define DWC_USB2PHYCFG_TOUT_CAL_SHIFT 0U

◆ DWC_USB2PHYCFG_16B_PHY_IF_BIT

#define DWC_USB2PHYCFG_16B_PHY_IF_BIT 0x00000008U

UTMI+ PHY Intf Width (8-bit/16-bit) SelecT Access: R_W

◆ DWC_USB2PHYCFG_16B_PHY_IF_SHIFT

#define DWC_USB2PHYCFG_16B_PHY_IF_SHIFT 3U

◆ DWC_USB2PHYCFG_DDR_SEL_BIT

#define DWC_USB2PHYCFG_DDR_SEL_BIT 0x00000008U

ULPI DDR Select Access: R_W

◆ DWC_USB2PHYCFG_DDR_SEL_SHIFT

#define DWC_USB2PHYCFG_DDR_SEL_SHIFT 3U

◆ DWC_USB2PHYCFG_UTMI_ULPI_BIT

#define DWC_USB2PHYCFG_UTMI_ULPI_BIT 0x00000010U

UTMI+ / ULPI Select Access: R_W

◆ DWC_USB2PHYCFG_UTMI_ULPI_SHIFT

#define DWC_USB2PHYCFG_UTMI_ULPI_SHIFT 4U

◆ DWC_USB2PHYCFG_FSINTF_BIT

#define DWC_USB2PHYCFG_FSINTF_BIT 0x00000020U

Full-speed Serial Interface Select Access: R_W

◆ DWC_USB2PHYCFG_FSINTF_SHIFT

#define DWC_USB2PHYCFG_FSINTF_SHIFT 5U

◆ DWC_USB2PHYCFG_SUS_PHY_BIT

#define DWC_USB2PHYCFG_SUS_PHY_BIT 0x00000040U

Suspend USB2 Phy Access: R_W

◆ DWC_USB2PHYCFG_SUS_PHY_SHIFT

#define DWC_USB2PHYCFG_SUS_PHY_SHIFT 6U

◆ DWC_USB2PHYCFG_PHY_SEL_BIT

#define DWC_USB2PHYCFG_PHY_SEL_BIT 0x00000080U

USB2.0 HS PHY/USB1.1 FS Serial Xcvr Select Access: R_W

◆ DWC_USB2PHYCFG_PHY_SEL_SHIFT

#define DWC_USB2PHYCFG_PHY_SEL_SHIFT 7U

◆ DWC_USB2PHYCFG_ENBL_SLP_M_BIT

#define DWC_USB2PHYCFG_ENBL_SLP_M_BIT 0x00000100U

Enable UTMI Sleep Access: R_W

◆ DWC_USB2PHYCFG_ENBL_SLP_M_SHIFT

#define DWC_USB2PHYCFG_ENBL_SLP_M_SHIFT 8U

◆ DWC_USB2PHYCFG_USB_TRD_TIM_BITS

#define DWC_USB2PHYCFG_USB_TRD_TIM_BITS 0x00003c00U

USB2.0 Turnaround Time Access: R_W

◆ DWC_USB2PHYCFG_USB_TRD_TIM_SHIFT

#define DWC_USB2PHYCFG_USB_TRD_TIM_SHIFT 10U

◆ DWC_USB2PHYCFG_PHY_LPWR_CLK_SEL_BIT

#define DWC_USB2PHYCFG_PHY_LPWR_CLK_SEL_BIT 0x00004000U

PHY Low-power Clock Select Access: R_W

◆ DWC_USB2PHYCFG_PHY_LPWR_CLK_SEL_SHIFT

#define DWC_USB2PHYCFG_PHY_LPWR_CLK_SEL_SHIFT 14U

◆ DWC_USB2PHYCFG_ULPI_AUTO_RES_BIT

#define DWC_USB2PHYCFG_ULPI_AUTO_RES_BIT 0x0000800U

ULPI Auto Resume Access: R_W

◆ DWC_USB2PHYCFG_ULPI_AUTO_RES_SHIFT

#define DWC_USB2PHYCFG_ULPI_AUTO_RES_SHIFT 15U

◆ DWC_USB2PHYCFG_ULPI_CLK_SUS_M_BIT

#define DWC_USB2PHYCFG_ULPI_CLK_SUS_M_BIT 0x00010000U

ULPI Clock SuspendM Access: R_W

◆ DWC_USB2PHYCFG_ULPI_CLK_SUS_M_SHIFT

#define DWC_USB2PHYCFG_ULPI_CLK_SUS_M_SHIFT 16U

◆ DWC_USB2PHYCFG_ULPI_EXT_VBUS_DRV_BIT

#define DWC_USB2PHYCFG_ULPI_EXT_VBUS_DRV_BIT 0x00020000U

ULPI External Vbus Drive Access: R_W

◆ DWC_USB2PHYCFG_ULPI_EXT_VBUS_DRV_SHIFT

#define DWC_USB2PHYCFG_ULPI_EXT_VBUS_DRV_SHIFT 17U

◆ DWC_USB2PHYCFG_ULPI_EXT_VBUS_IND_BIT

#define DWC_USB2PHYCFG_ULPI_EXT_VBUS_IND_BIT 0x00040000U

ULPI External Vbus Indicator Access: R_W

◆ DWC_USB2PHYCFG_ULPI_EXT_VBUS_IND_SHIFT

#define DWC_USB2PHYCFG_ULPI_EXT_VBUS_IND_SHIFT 18U

◆ DWC_USB2PHYCFG_PHY_INTR_NUM_BITS

#define DWC_USB2PHYCFG_PHY_INTR_NUM_BITS 0x01f80000U

PHY Interrupt Number Access: R_W

◆ DWC_USB2PHYCFG_PHY_INTR_NUM_SHIFT

#define DWC_USB2PHYCFG_PHY_INTR_NUM_SHIFT 19U

◆ DWC_USB2PHYCFG_OTG_INTR_NUM_BITS

#define DWC_USB2PHYCFG_OTG_INTR_NUM_BITS 0x7e000000U

OTG Interrupt Number Access: R_W

◆ DWC_USB2PHYCFG_OTG_INTR_NUM_SHIFT

#define DWC_USB2PHYCFG_OTG_INTR_NUM_SHIFT 25U

◆ DWC_USB2PHYCFG_PHY_SOFT_RST_BIT

#define DWC_USB2PHYCFG_PHY_SOFT_RST_BIT 0x80000000U

PHY Soft Reset Access: R_W

◆ DWC_USB2PHYCFG_PHY_SOFT_RST_SHIFT

#define DWC_USB2PHYCFG_PHY_SOFT_RST_SHIFT 31U

◆ DWC_USB2I2C_RSVD_BITS

#define DWC_USB2I2C_RSVD_BITS 0xffffffffU

All bits are reserved

◆ DWC_USB2I2C_RSVD_SHIFT

#define DWC_USB2I2C_RSVD_SHIFT 0U

◆ DWC_USB2PHY_REGDATA_BITS

#define DWC_USB2PHY_REGDATA_BITS 0x000000ffU

Register Data Access: R_W

◆ DWC_USB2PHY_REGDATA_SHIFT

#define DWC_USB2PHY_REGDATA_SHIFT 0U

◆ DWC_USB2PHY_VCTRL_BITS

#define DWC_USB2PHY_VCTRL_BITS 0x0000ff00U

UTMI+ Vendor Ctrl Register Address Access: R_W

◆ DWC_USB2PHY_VCTRL_SHIFT

#define DWC_USB2PHY_VCTRL_SHIFT 8U

◆ DWC_USB2PHY_EXTREGADDR_BITS

#define DWC_USB2PHY_EXTREGADDR_BITS 0x00003f00U

ULPI Extended Register Address Access: R_W

◆ DWC_USB2PHY_EXTREGADDR_SHIFT

#define DWC_USB2PHY_EXTREGADDR_SHIFT 8U

◆ DWC_USB2PHY_REGADDR_BITS

#define DWC_USB2PHY_REGADDR_BITS 0x003f0000U

Register Address Access: R_W

◆ DWC_USB2PHY_REGADDR_SHIFT

#define DWC_USB2PHY_REGADDR_SHIFT 16U

◆ DWC_USB2PHY_REGWR_BIT

#define DWC_USB2PHY_REGWR_BIT 0x00400000U

Register Write Access: R_W

◆ DWC_USB2PHY_REGWR_SHIFT

#define DWC_USB2PHY_REGWR_SHIFT 22U

◆ DWC_USB2PHY_VSTSBSY_BIT

#define DWC_USB2PHY_VSTSBSY_BIT 0x00800000U

VStatus Busy Access: RO

◆ DWC_USB2PHY_VSTSBSY_SHIFT

#define DWC_USB2PHY_VSTSBSY_SHIFT 23U

◆ DWC_USB2PHY_VSTSDONE_BIT

#define DWC_USB2PHY_VSTSDONE_BIT 0x01000000U

VStatus Done Access: R_SS_SC

◆ DWC_USB2PHY_VSTSDONE_SHIFT

#define DWC_USB2PHY_VSTSDONE_SHIFT 24U

◆ DWC_USB2PHY_NEWREGREQ_BIT

#define DWC_USB2PHY_NEWREGREQ_BIT 0x02000000U

New Register Request Access: R_WS_SC

◆ DWC_USB2PHY_NEWREGREQ_SHIFT

#define DWC_USB2PHY_NEWREGREQ_SHIFT 25U

◆ DWC_USB2PHY_DIS_ULPI_DRVR_BIT

#define DWC_USB2PHY_DIS_ULPI_DRVR_BIT 0x04000000U

Disable ULPI Drivers Access: R_WS_SC

◆ DWC_USB2PHY_DIS_ULPI_DRVR_SHIFT

#define DWC_USB2PHY_DIS_ULPI_DRVR_SHIFT 26U

◆ DWC_PIPECTL_ELAS_BUF_MODE_BIT

#define DWC_PIPECTL_ELAS_BUF_MODE_BIT 0x00000001U

Elastic Buffer Mode Access: R_W

◆ DWC_PIPECTL_ELAS_BUF_MODE_SHIFT

#define DWC_PIPECTL_ELAS_BUF_MODE_SHIFT 0U

◆ DWC_PIPECTL_TX_DEMPH_BITS

#define DWC_PIPECTL_TX_DEMPH_BITS 0x00000006U

Tx De-Emphasis Access: R_W

◆ DWC_PIPECTL_TX_DEMPH_SHIFT

#define DWC_PIPECTL_TX_DEMPH_SHIFT 1U

◆ DWC_PIPECTL_TX_MARGIN_BITS

#define DWC_PIPECTL_TX_MARGIN_BITS 0x00000038U

Tx Margin Access: R_W

◆ DWC_PIPECTL_TX_MARGIN_SHIFT

#define DWC_PIPECTL_TX_MARGIN_SHIFT 3U

◆ DWC_PIPECTL_TX_SWING_BIT

#define DWC_PIPECTL_TX_SWING_BIT 0x00000040U

Tx Swing Access: R_W

◆ DWC_PIPECTL_TX_SWING_SHIFT

#define DWC_PIPECTL_TX_SWING_SHIFT 6U

◆ DWC_PIPECTL_SSIC_EN_BIT

#define DWC_PIPECTL_SSIC_EN_BIT 0x00000080U

USB3 SSIC Enable Access: R_W

◆ DWC_PIPECTL_SSIC_EN_SHIFT

#define DWC_PIPECTL_SSIC_EN_SHIFT 7U

◆ DWC_PIPECTL_LFPS_FILTER_BIT

#define DWC_PIPECTL_LFPS_FILTER_BIT 0x00000200U

LFPS Filter Access: R_W

◆ DWC_PIPECTL_LFPS_FILTER_SHIFT

#define DWC_PIPECTL_LFPS_FILTER_SHIFT 9U

◆ DWC_PIPECTL_P3_EX_SIG_P2_BIT

#define DWC_PIPECTL_P3_EX_SIG_P2_BIT 0x00000400U

P3 Exit Signal In P2 Access: R_W

◆ DWC_PIPECTL_P3_EX_SIG_P2_SHIFT

#define DWC_PIPECTL_P3_EX_SIG_P2_SHIFT 10U

◆ DWC_PIPECTL_P3_P2_TRAN_OK_BIT

#define DWC_PIPECTL_P3_P2_TRAN_OK_BIT 0x00000800U

P3-P2 Transitions OK Access: R_W

◆ DWC_PIPECTL_P3_P2_TRAN_OK_SHIFT

#define DWC_PIPECTL_P3_P2_TRAN_OK_SHIFT 11U

◆ DWC_PIPECTL_LFPS_P0_ALGN_BIT

#define DWC_PIPECTL_LFPS_P0_ALGN_BIT 0x00001000U

LFPS P0 Align Access: R_W

◆ DWC_PIPECTL_LFPS_P0_ALGN_SHIFT

#define DWC_PIPECTL_LFPS_P0_ALGN_SHIFT 12U

◆ DWC_PIPECTL_DATA_WIDTH_BITS

#define DWC_PIPECTL_DATA_WIDTH_BITS 0x00018000U

Pipe Data Width Access: R_W

◆ DWC_PIPECTL_DATA_WIDTH_SHIFT

#define DWC_PIPECTL_DATA_WIDTH_SHIFT 15U

◆ DWC_PIPECTL_SUS_PHY_BIT

#define DWC_PIPECTL_SUS_PHY_BIT 0x00020000U

Suspend USB3 Phy Access: R_W

◆ DWC_PIPECTL_SUS_PHY_SHIFT

#define DWC_PIPECTL_SUS_PHY_SHIFT 17U

◆ DWC_PIPECTL_PHY_SOFT_RST_BIT

#define DWC_PIPECTL_PHY_SOFT_RST_BIT 0x80000000U

PHY Soft Reset Access: R_W

◆ DWC_PIPECTL_PHY_SOFT_RST_SHIFT

#define DWC_PIPECTL_PHY_SOFT_RST_SHIFT 31U

◆ DWC_FIFOSZ_DEPTH_BITS

#define DWC_FIFOSZ_DEPTH_BITS 0x0000ffffU

This enum represents the bit fields in the FIFO Size Registers. Depth Access: R_W

◆ DWC_FIFOSZ_DEPTH_SHIFT

#define DWC_FIFOSZ_DEPTH_SHIFT 0U

◆ DWC_FIFOSZ_STARTADDR_BITS

#define DWC_FIFOSZ_STARTADDR_BITS 0xffff0000U

Starting Address Access: RO or R_W

◆ DWC_FIFOSZ_STARTADDR_SHIFT

#define DWC_FIFOSZ_STARTADDR_SHIFT 16U

◆ DWC_EVENTSIZ_SIZ_BITS

#define DWC_EVENTSIZ_SIZ_BITS 0x0000ffffU

Event Buffer Size Access: R_W

◆ DWC_EVENTSIZ_SIZ_SHIFT

#define DWC_EVENTSIZ_SIZ_SHIFT 0U

◆ DWC_EVENTSIZ_INT_MSK_BIT

#define DWC_EVENTSIZ_INT_MSK_BIT 0x80000000U

Event Interrupt Mask (1 == disable) Access: R_W

◆ DWC_EVENTSIZ_INT_MSK_SHIFT

#define DWC_EVENTSIZ_INT_MSK_SHIFT 31U

◆ DWC_EVENTCNT_CNT_BITS

#define DWC_EVENTCNT_CNT_BITS 0x0000ffffU

Event Count Access: R_W

◆ DWC_EVENTCNT_CNT_SHIFT

#define DWC_EVENTCNT_CNT_SHIFT 0U

◆ DWC_EVENT_NON_EP_BIT

#define DWC_EVENT_NON_EP_BIT 0x01U

This enum represents the bit fields of a generic Event Buffer entry. Non-Endpoint Specific Event flag

◆ DWC_EVENT_NON_EP_SHIFT

#define DWC_EVENT_NON_EP_SHIFT 0U

◆ DWC_EVENT_INTTYPE_BITS

#define DWC_EVENT_INTTYPE_BITS 0xfeU

Non-Endpoint Specific Event Type

◆ DWC_EVENT_INTTYPE_SHIFT

#define DWC_EVENT_INTTYPE_SHIFT 1U

◆ DWC_EVENT_DEV_INT

#define DWC_EVENT_DEV_INT 0U /** @< */

Non-Endpoint Specific Event Type values

◆ DWC_EVENT_OTG_INT

#define DWC_EVENT_OTG_INT 1U /** @< */

◆ DWC_EVENT_CARKIT_INT

#define DWC_EVENT_CARKIT_INT 3U /** @< */

◆ DWC_EVENT_I2C_INT

#define DWC_EVENT_I2C_INT 4U

◆ DWC_DEVT_BITS

#define DWC_DEVT_BITS 0x00000f00U

This enum represents the non-generic bit fields of an Event Buffer entry for Device Specific events (DEVT). Device Specific Event Type

◆ DWC_DEVT_SHIFT

#define DWC_DEVT_SHIFT 8U

◆ DWC_DEVT_DISCONN

#define DWC_DEVT_DISCONN 0U /** @< */

Device Specific Event Type values

◆ DWC_DEVT_USBRESET

#define DWC_DEVT_USBRESET 1U /** @< */

◆ DWC_DEVT_CONNDONE

#define DWC_DEVT_CONNDONE 2U /** @< */

◆ DWC_DEVT_ULST_CHNG

#define DWC_DEVT_ULST_CHNG 3U /** @< */

◆ DWC_DEVT_WKUP

#define DWC_DEVT_WKUP 4U /** @< */

◆ DWC_DEVT_HIBER_REQ

#define DWC_DEVT_HIBER_REQ 5U /** @< */

◆ DWC_DEVT_U3_L2L1_SUSP

#define DWC_DEVT_U3_L2L1_SUSP 6U /** @< */

◆ DWC_DEVT_SOF

#define DWC_DEVT_SOF 7U /** @< */

◆ DWC_DEVT_ERRATICERR

#define DWC_DEVT_ERRATICERR 9U /** @< */

◆ DWC_DEVT_CMD_CMPL

#define DWC_DEVT_CMD_CMPL 10U /** @< */

◆ DWC_DEVT_OVERFLOW

#define DWC_DEVT_OVERFLOW 11U /** @< */

◆ DWC_DEVT_VNDR_DEV_TST_RCVD

#define DWC_DEVT_VNDR_DEV_TST_RCVD 12U /** @< */

◆ DWC_DEVT_INACT_TIMEOUT_RCVD

#define DWC_DEVT_INACT_TIMEOUT_RCVD 13U

◆ DWC_DEVT_EVT_INFO_BITS

#define DWC_DEVT_EVT_INFO_BITS 0xffff0000U

Event Information

◆ DWC_DEVT_EVT_INFO_SHIFT

#define DWC_DEVT_EVT_INFO_SHIFT 16U

◆ DWC_DEVT_ULST_STATE_BITS

#define DWC_DEVT_ULST_STATE_BITS 0x000f0000U

USB/Link State

◆ DWC_DEVT_ULST_STATE_SHIFT

#define DWC_DEVT_ULST_STATE_SHIFT 16U

◆ DWC_LINK_STATE_U0

#define DWC_LINK_STATE_U0 0U /** @< */

USB/Link State values in SS

◆ DWC_LINK_STATE_U1

#define DWC_LINK_STATE_U1 1U /** @< */

◆ DWC_LINK_STATE_U2

#define DWC_LINK_STATE_U2 2U /** @< */

◆ DWC_LINK_STATE_U3

#define DWC_LINK_STATE_U3 3U /** @< */

◆ DWC_LINK_STATE_SS_DIS

#define DWC_LINK_STATE_SS_DIS 4U /** @< */

◆ DWC_LINK_STATE_RX_DET

#define DWC_LINK_STATE_RX_DET 5U /** @< */

◆ DWC_LINK_STATE_SS_INACT

#define DWC_LINK_STATE_SS_INACT 6U /** @< */

◆ DWC_LINK_STATE_POLL

#define DWC_LINK_STATE_POLL 7U /** @< */

◆ DWC_LINK_STATE_RECOV

#define DWC_LINK_STATE_RECOV 8U /** @< */

◆ DWC_LINK_STATE_HRESET

#define DWC_LINK_STATE_HRESET 9U /** @< */

◆ DWC_LINK_STATE_CMPLY

#define DWC_LINK_STATE_CMPLY 10U /** @< */

◆ DWC_LINK_STATE_LPBK

#define DWC_LINK_STATE_LPBK 11U /** @< */

◆ DWC_LINK_STATE_RESET

#define DWC_LINK_STATE_RESET 14U /** @< */

◆ DWC_LINK_STATE_RESUME

#define DWC_LINK_STATE_RESUME 15U

◆ DWC_LINK_STATE_ON

#define DWC_LINK_STATE_ON 0U /** @< */

USB/Link State values in HS/FS/LS

◆ DWC_LINK_STATE_SLEEP

#define DWC_LINK_STATE_SLEEP 2U /** @< */

◆ DWC_LINK_STATE_SUSPEND

#define DWC_LINK_STATE_SUSPEND 3U /** @< */

◆ DWC_LINK_STATE_EARLY_SUSPEND

#define DWC_LINK_STATE_EARLY_SUSPEND 5U

◆ DWC_DEVT_ULST_SS_BIT

#define DWC_DEVT_ULST_SS_BIT 0x00100000U

◆ DWC_DEVT_ULST_SS_SHIFT

#define DWC_DEVT_ULST_SS_SHIFT 20U

◆ DWC_DEVT_HIBER_STATE_BITS

#define DWC_DEVT_HIBER_STATE_BITS DWC_DEVT_ULST_STATE_BITS

◆ DWC_DEVT_HIBER_STATE_SHIFT

#define DWC_DEVT_HIBER_STATE_SHIFT DWC_DEVT_ULST_STATE_SHIFT

◆ DWC_DEVT_HIBER_SS_BIT

#define DWC_DEVT_HIBER_SS_BIT DWC_DEVT_ULST_SS_BIT

◆ DWC_DEVT_HIBER_SS_SHIFT

#define DWC_DEVT_HIBER_SS_SHIFT DWC_DEVT_ULST_SS_SHIFT

◆ DWC_DEVT_HIBER_HIRD_BITS

#define DWC_DEVT_HIBER_HIRD_BITS 0x0f000000U

◆ DWC_DEVT_HIBER_HIRD_SHIFT

#define DWC_DEVT_HIBER_HIRD_SHIFT 24U

◆ DWC_DEPEVT_EPNUM_BITS

#define DWC_DEPEVT_EPNUM_BITS 0x0000003eU

This enum represents the bit fields of an Event Buffer entry for Endpoint Specific events (DEPEVT). Endpoint Number

◆ DWC_DEPEVT_EPNUM_SHIFT

#define DWC_DEPEVT_EPNUM_SHIFT 1U

◆ DWC_DEPEVT_INTTYPE_BITS

#define DWC_DEPEVT_INTTYPE_BITS 0x000003c0U

Endpoint Event Type

◆ DWC_DEPEVT_INTTYPE_SHIFT

#define DWC_DEPEVT_INTTYPE_SHIFT 6U

◆ DWC_DEPEVT_XFER_CMPL

#define DWC_DEPEVT_XFER_CMPL 1U /** @< */

Endpoint Event Type values

◆ DWC_DEPEVT_XFER_IN_PROG

#define DWC_DEPEVT_XFER_IN_PROG 2U /** @< */

◆ DWC_DEPEVT_XFER_NRDY

#define DWC_DEPEVT_XFER_NRDY 3U /** @< */

◆ DWC_DEPEVT_FIFOXRUN

#define DWC_DEPEVT_FIFOXRUN 4U /** @< */

◆ DWC_DEPEVT_STRM_EVT

#define DWC_DEPEVT_STRM_EVT 6U /** @< */

◆ DWC_DEPEVT_EPCMD_CMPL

#define DWC_DEPEVT_EPCMD_CMPL 7U

◆ DWC_DEPEVT_NO_MORE_RSCS_BIT

#define DWC_DEPEVT_NO_MORE_RSCS_BIT 0x00001000U

Event Status for Start Xfer Command

◆ DWC_DEPEVT_NO_MORE_RSCS_SHIFT

#define DWC_DEPEVT_NO_MORE_RSCS_SHIFT 12U

◆ DWC_DEPEVT_ISOC_TIME_PASSED_BIT

#define DWC_DEPEVT_ISOC_TIME_PASSED_BIT 0x00002000U

◆ DWC_DEPEVT_ISOC_TIME_PASSED_SHIFT

#define DWC_DEPEVT_ISOC_TIME_PASSED_SHIFT 13U

◆ DWC_DEPEVT_STRM_EVT_BITS

#define DWC_DEPEVT_STRM_EVT_BITS 0x0000f000U

Event Status for Stream Event

◆ DWC_DEPEVT_STRM_EVT_SHIFT

#define DWC_DEPEVT_STRM_EVT_SHIFT 12U

◆ DWC_DEPEVT_STRM_FOUND

#define DWC_DEPEVT_STRM_FOUND 1U /** @< */

Stream Event Status values

◆ DWC_DEPEVT_STRM_NOT_FOUND

#define DWC_DEPEVT_STRM_NOT_FOUND 2U

◆ DWC_DEPEVT_BUS_ERR_BIT

#define DWC_DEPEVT_BUS_ERR_BIT 0x00001000U

Event Status for Xfer Complete or Xfer In Progress Event

◆ DWC_DEPEVT_BUS_ERR_SHIFT

#define DWC_DEPEVT_BUS_ERR_SHIFT 12U

◆ DWC_DEPEVT_SHORT_PKT_BIT

#define DWC_DEPEVT_SHORT_PKT_BIT 0x00002000U

◆ DWC_DEPEVT_SHORT_PKT_SHIFT

#define DWC_DEPEVT_SHORT_PKT_SHIFT 13U

◆ DWC_DEPEVT_IOC_BIT

#define DWC_DEPEVT_IOC_BIT 0x00004000U

◆ DWC_DEPEVT_IOC_SHIFT

#define DWC_DEPEVT_IOC_SHIFT 14U

◆ DWC_DEPEVT_LST_BIT

#define DWC_DEPEVT_LST_BIT 0x00008000U

◆ DWC_DEPEVT_LST_SHIFT

#define DWC_DEPEVT_LST_SHIFT 15U

◆ DWC_DEPEVT_MISSED_ISOC_BIT

#define DWC_DEPEVT_MISSED_ISOC_BIT DWC_DEPEVT_LST_BIT

◆ DWC_DEPEVT_MISSED_ISOC_SHIFT

#define DWC_DEPEVT_MISSED_ISOC_SHIFT DWC_DEPEVT_LST_SHIFT

◆ DWC_DEPEVT_CTRL_BITS

#define DWC_DEPEVT_CTRL_BITS 0x00003000U

Event Status for Xfer Not Ready Event

◆ DWC_DEPEVT_CTRL_SHIFT

#define DWC_DEPEVT_CTRL_SHIFT 12U

◆ DWC_DEPEVT_XFER_ACTIVE_BIT

#define DWC_DEPEVT_XFER_ACTIVE_BIT 0x00008000U

◆ DWC_DEPEVT_XFER_ACTIVE_SHIFT

#define DWC_DEPEVT_XFER_ACTIVE_SHIFT 15U

◆ DWC_DEPEVT_CTRL_SETUP

#define DWC_DEPEVT_CTRL_SETUP 0U /** @< */

Xfer Not Ready Event Status values

◆ DWC_DEPEVT_CTRL_DATA

#define DWC_DEPEVT_CTRL_DATA 1U /** @< */

◆ DWC_DEPEVT_CTRL_STATUS

#define DWC_DEPEVT_CTRL_STATUS 2U

◆ DWC_DEPEVT_STRM_ID_BITS

#define DWC_DEPEVT_STRM_ID_BITS 0xffff0000U

Stream ID

◆ DWC_DEPEVT_STRM_ID_SHIFT

#define DWC_DEPEVT_STRM_ID_SHIFT 16U

◆ DWC_DEPEVT_ISOC_UFRAME_NUM_BITS

#define DWC_DEPEVT_ISOC_UFRAME_NUM_BITS 0xffff0000U

Isoc uFrame Number (for Xfer Not Ready on Isoc EP)

◆ DWC_DEPEVT_ISOC_UFRAME_NUM_SHIFT

#define DWC_DEPEVT_ISOC_UFRAME_NUM_SHIFT 16U

◆ DWC_DEPEVT_XFER_RSC_IDX_BITS

#define DWC_DEPEVT_XFER_RSC_IDX_BITS 0x007f0000U

Xfer Resource Index (for Start Xfer Command)

◆ DWC_DEPEVT_XFER_RSC_IDX_SHIFT

#define DWC_DEPEVT_XFER_RSC_IDX_SHIFT 16U

◆ DWC_DEPEVT_CUR_DAT_SEQ_NUM_BITS

#define DWC_DEPEVT_CUR_DAT_SEQ_NUM_BITS 0x001f0000U

Current Data Sequence Number (for Get Endpoint State Command)

◆ DWC_DEPEVT_CUR_DAT_SEQ_NUM_SHIFT

#define DWC_DEPEVT_CUR_DAT_SEQ_NUM_SHIFT 16U

◆ DWC_DEPEVT_FLOW_CTRL_BIT

#define DWC_DEPEVT_FLOW_CTRL_BIT 0x00200000U

Flow Control State (for Get Endpoint State Command)

◆ DWC_DEPEVT_FLOW_CTRL_SHIFT

#define DWC_DEPEVT_FLOW_CTRL_SHIFT 21U

◆ DWC_GINT_PHY_PORT_BITS

#define DWC_GINT_PHY_PORT_BITS 0xf00U

This enum represents the non-generic bit fields of an Event Buffer entry for other Core events (GEVT). PHY Port Number

◆ DWC_GINT_PHY_PORT_SHIFT

#define DWC_GINT_PHY_PORT_SHIFT 8U

◆ DWC_CORE_GLOBAL_REG_OFFSET

#define DWC_CORE_GLOBAL_REG_OFFSET 0x100U

◆ DWC_DCFG_DEVSPD_BITS

#define DWC_DCFG_DEVSPD_BITS 0x000007U

This enum represents the bit fields in the Device Configuration Register (DCFG). Device Speed Access: R_W

◆ DWC_DCFG_DEVSPD_SHIFT

#define DWC_DCFG_DEVSPD_SHIFT 0U

◆ DWC_SPEED_HS_PHY_30MHZ_OR_60MHZ

#define DWC_SPEED_HS_PHY_30MHZ_OR_60MHZ 0U /** @< */

Device Speed values

◆ DWC_SPEED_FS_PHY_30MHZ_OR_60MHZ

#define DWC_SPEED_FS_PHY_30MHZ_OR_60MHZ 1U /** @< */

◆ DWC_SPEED_LS_PHY_6MHZ

#define DWC_SPEED_LS_PHY_6MHZ 2U /** @< */

◆ DWC_SPEED_FS_PHY_48MHZ

#define DWC_SPEED_FS_PHY_48MHZ 3U /** @< */

◆ DWC_SPEED_SS_PHY_125MHZ_OR_250MHZ

#define DWC_SPEED_SS_PHY_125MHZ_OR_250MHZ 4U

◆ DWC_DCFG_DEVADDR_BITS

#define DWC_DCFG_DEVADDR_BITS 0x0003f8U

Device Address Access: R_W

◆ DWC_DCFG_DEVADDR_SHIFT

#define DWC_DCFG_DEVADDR_SHIFT 3U

◆ DWC_DCFG_PER_FR_INTVL_BITS

#define DWC_DCFG_PER_FR_INTVL_BITS 0x000c00U

Periodic Frame Interval Access: R_W

◆ DWC_DCFG_PER_FR_INTVL_SHIFT

#define DWC_DCFG_PER_FR_INTVL_SHIFT 10U

◆ DWC_DCFG_PER_FR_INTVL_80

#define DWC_DCFG_PER_FR_INTVL_80 0U /** @< */

Periodic Frame Interval values

◆ DWC_DCFG_PER_FR_INTVL_85

#define DWC_DCFG_PER_FR_INTVL_85 1U /** @< */

◆ DWC_DCFG_PER_FR_INTVL_90

#define DWC_DCFG_PER_FR_INTVL_90 2U /** @< */

◆ DWC_DCFG_PER_FR_INTVL_95

#define DWC_DCFG_PER_FR_INTVL_95 3U

◆ DWC_DCFG_DEV_INTR_NUM_BITS

#define DWC_DCFG_DEV_INTR_NUM_BITS 0x01f000U

Device Interrupt Number Access: R_W

◆ DWC_DCFG_DEV_INTR_NUM_SHIFT

#define DWC_DCFG_DEV_INTR_NUM_SHIFT 12U

◆ DWC_DCFG_NUM_RCV_BUF_BITS

#define DWC_DCFG_NUM_RCV_BUF_BITS 0x3e0000U

Number of Receive Buffers Access: R_W

◆ DWC_DCFG_NUM_RCV_BUF_SHIFT

#define DWC_DCFG_NUM_RCV_BUF_SHIFT 17U

◆ DWC_DCFG_LPM_CAP_BIT

#define DWC_DCFG_LPM_CAP_BIT 0x400000U

LPM Capable Access: R_W

◆ DWC_DCFG_LPM_CAP_SHIFT

#define DWC_DCFG_LPM_CAP_SHIFT 22U

◆ DWC_DCTL_SFT_DISCONN_BIT

#define DWC_DCTL_SFT_DISCONN_BIT 0x00000001U

Soft Disconnect Access: R_W

◆ DWC_DCTL_SFT_DISCONN_SHIFT

#define DWC_DCTL_SFT_DISCONN_SHIFT 0U

◆ DWC_DCTL_TSTCTL_BITS

#define DWC_DCTL_TSTCTL_BITS 0x0000001eU

Test Control Access: R_W

◆ DWC_DCTL_TSTCTL_SHIFT

#define DWC_DCTL_TSTCTL_SHIFT 1U

◆ DWC_DCTL_ULST_CHNG_REQ_BITS

#define DWC_DCTL_ULST_CHNG_REQ_BITS 0x000001e0U

USB/Link State Change Request Access: R_W

◆ DWC_DCTL_ULST_CHNG_REQ_SHIFT

#define DWC_DCTL_ULST_CHNG_REQ_SHIFT 5U

◆ DWC_LINK_STATE_REQ_NO_ACTION

#define DWC_LINK_STATE_REQ_NO_ACTION 0U /** @< */

Requested Link State Transition/Action In SS Mode

◆ DWC_LINK_STATE_REQ_SS_DISABLED

#define DWC_LINK_STATE_REQ_SS_DISABLED 4U /** @< */

◆ DWC_LINK_STATE_REQ_RX_DETECT

#define DWC_LINK_STATE_REQ_RX_DETECT 5U /** @< */

◆ DWC_LINK_STATE_REQ_INACTIVE

#define DWC_LINK_STATE_REQ_INACTIVE 6U /** @< */

◆ DWC_LINK_STATE_REQ_RECOVERY

#define DWC_LINK_STATE_REQ_RECOVERY 8U /** @< */

◆ DWC_LINK_STATE_REQ_COMPLIANCE

#define DWC_LINK_STATE_REQ_COMPLIANCE 10U /** @< */

◆ DWC_LINK_STATE_REQ_LOOPBACK

#define DWC_LINK_STATE_REQ_LOOPBACK 11U /** @< */

◆ DWC_LINK_STATE_REQ_HOST_MODE_ONLY

#define DWC_LINK_STATE_REQ_HOST_MODE_ONLY 15U

◆ DWC_LINK_STATE_REQ_REMOTE_WAKEUP

#define DWC_LINK_STATE_REQ_REMOTE_WAKEUP 8U

Requested Link State Transition/Action In HS/FS/LS Mode

◆ DWC_DCTL_ACCEPT_U1_EN_BIT

#define DWC_DCTL_ACCEPT_U1_EN_BIT 0x00000200U

U1/U2 control Access: R_W

◆ DWC_DCTL_ACCEPT_U1_EN_SHIFT

#define DWC_DCTL_ACCEPT_U1_EN_SHIFT 9U

◆ DWC_DCTL_INIT_U1_EN_BIT

#define DWC_DCTL_INIT_U1_EN_BIT 0x00000400U

◆ DWC_DCTL_INIT_U1_EN_SHIFT

#define DWC_DCTL_INIT_U1_EN_SHIFT 10U

◆ DWC_DCTL_ACCEPT_U2_EN_BIT

#define DWC_DCTL_ACCEPT_U2_EN_BIT 0x00000800U

◆ DWC_DCTL_ACCEPT_U2_EN_SHIFT

#define DWC_DCTL_ACCEPT_U2_EN_SHIFT 11U

◆ DWC_DCTL_INIT_U2_EN_BIT

#define DWC_DCTL_INIT_U2_EN_BIT 0x00001000U

◆ DWC_DCTL_INIT_U2_EN_SHIFT

#define DWC_DCTL_INIT_U2_EN_SHIFT 12U

◆ DWC_DCTL_CSS_BIT

#define DWC_DCTL_CSS_BIT 0x00010000U

Controller Save State Access: R_W

◆ DWC_DCTL_CSS_SHIFT

#define DWC_DCTL_CSS_SHIFT 16U

◆ DWC_DCTL_CRS_BIT

#define DWC_DCTL_CRS_BIT 0x00020000U

Controller Restore State Access: R_W

◆ DWC_DCTL_CRS_SHIFT

#define DWC_DCTL_CRS_SHIFT 17U

◆ DWC_DCTL_L1_HIBER_EN_BIT

#define DWC_DCTL_L1_HIBER_EN_BIT 0x00040000U

L1 Hibernation Enable Access: R_W

◆ DWC_DCTL_L1_HIBER_EN_RES_SHIFT

#define DWC_DCTL_L1_HIBER_EN_RES_SHIFT 18U

◆ DWC_DCTL_KEEP_CONNECT_BIT

#define DWC_DCTL_KEEP_CONNECT_BIT 0x00080000U

Keep Connect (for hibernation) Access: R_W

◆ DWC_DCTL_KEEP_CONNECT_SHIFT

#define DWC_DCTL_KEEP_CONNECT_SHIFT 19U

◆ DWC_DCTL_LPM_NYET_THRESH_BITS

#define DWC_DCTL_LPM_NYET_THRESH_BITS 0x00f00000U

LPM NYET Response Threshold Access: R_W

◆ DWC_DCTL_LPM_NYET_THRESH_SHIFT

#define DWC_DCTL_LPM_NYET_THRESH_SHIFT 20U

◆ DWC_DCTL_APP_L1_RES_BIT

#define DWC_DCTL_APP_L1_RES_BIT 0x00800000U

LPM Response Access: R_W

◆ DWC_DCTL_APP_L1_RES_SHIFT

#define DWC_DCTL_APP_L1_RES_SHIFT 23U

◆ DWC_DCTL_HIRD_THR_BITS

#define DWC_DCTL_HIRD_THR_BITS 0x1f000000U

◆ DWC_DCTL_HIRD_THR_SHIFT

#define DWC_DCTL_HIRD_THR_SHIFT 24U

◆ DWC_DCTL_LSFT_RST_BIT

#define DWC_DCTL_LSFT_RST_BIT 0x20000000U

Light Soft Reset Access: R_W

◆ DWC_DCTL_LSFT_RST_SHIFT

#define DWC_DCTL_LSFT_RST_SHIFT 29U

◆ DWC_DCTL_CSFT_RST_BIT

#define DWC_DCTL_CSFT_RST_BIT 0x40000000U

Core Soft Reset Access: R_W

◆ DWC_DCTL_CSFT_RST_SHIFT

#define DWC_DCTL_CSFT_RST_SHIFT 30U

◆ DWC_DCTL_RUN_STOP_BIT

#define DWC_DCTL_RUN_STOP_BIT 0x80000000U

Run/Stop Access: R_W

◆ DWC_DCTL_RUN_STOP_SHIFT

#define DWC_DCTL_RUN_STOP_SHIFT 31U

◆ DWC_DEVTEN_DISCONN_BIT

#define DWC_DEVTEN_DISCONN_BIT 0x0001U

Disconnect Detected Event Enable Access: R_W

◆ DWC_DEVTEN_DISCONN_SHIFT

#define DWC_DEVTEN_DISCONN_SHIFT 0U

◆ DWC_DEVTEN_USBRESET_BIT

#define DWC_DEVTEN_USBRESET_BIT 0x0002U

USB Reset Enable Access: R_W

◆ DWC_DEVTEN_USBRESET_SHIFT

#define DWC_DEVTEN_USBRESET_SHIFT 1U

◆ DWC_DEVTEN_CONNDONE_BIT

#define DWC_DEVTEN_CONNDONE_BIT 0x0004U

Connect Done Enable Access: R_W

◆ DWC_DEVTEN_CONNDONE_SHIFT

#define DWC_DEVTEN_CONNDONE_SHIFT 2U

◆ DWC_DEVTEN_ULST_CHNG_BIT

#define DWC_DEVTEN_ULST_CHNG_BIT 0x0008U

USB/Link State Change Event Enable Access: R_W

◆ DWC_DEVTEN_ULST_CHNG_SHIFT

#define DWC_DEVTEN_ULST_CHNG_SHIFT 3U

◆ DWC_DEVTEN_WKUP_BIT

#define DWC_DEVTEN_WKUP_BIT 0x0010U

Resume/Remote-Wakeup Event Enable Access: R_W

◆ DWC_DEVTEN_WKUP_SHIFT

#define DWC_DEVTEN_WKUP_SHIFT 4U

◆ DWC_DEVTEN_HIBER_REQ_BIT

#define DWC_DEVTEN_HIBER_REQ_BIT 0x0020U

Hibernation Request Event Enable Access: R_W

◆ DWC_DEVTEN_HIBER_REQ_SHIFT

#define DWC_DEVTEN_HIBER_REQ_SHIFT 5U

◆ DWC_DEVTEN_U3_L2L1_SUSP_BIT

#define DWC_DEVTEN_U3_L2L1_SUSP_BIT 0x0040U

End of Periodic Frame Event Enable Access: R_W

◆ DWC_DEVTEN_U3_L2L1_SUSP_SHIFT

#define DWC_DEVTEN_U3_L2L1_SUSP_SHIFT 6U

◆ DWC_DEVTEN_SOF_BIT

#define DWC_DEVTEN_SOF_BIT 0x0080U

Start of (Micro)Frame Enable Access: R_W

◆ DWC_DEVTEN_SOF_SHIFT

#define DWC_DEVTEN_SOF_SHIFT 7U

◆ DWC_DEVTEN_ERRATICERR_BIT

#define DWC_DEVTEN_ERRATICERR_BIT 0x0200U

Erratic Error Event Enable Access: R_W

◆ DWC_DEVTEN_ERRATICERR_SHIFT

#define DWC_DEVTEN_ERRATICERR_SHIFT 9U

◆ DWC_DEVTEN_INACT_TIMEOUT_BIT

#define DWC_DEVTEN_INACT_TIMEOUT_BIT 0x2000U

U2 Inactivity Timeout Enable Access: R_W

◆ DWC_DEVTEN_INACT_TIMEOUT_SHIFT

#define DWC_DEVTEN_INACT_TIMEOUT_SHIFT 13U

◆ DWC_DSTS_CONNSPD_BITS

#define DWC_DSTS_CONNSPD_BITS 0x00000007U

Connected Speed Access: RO. (see enum dcfg_data for values)

◆ DWC_DSTS_CONNSPD_SHIFT

#define DWC_DSTS_CONNSPD_SHIFT 0U

◆ DWC_DSTS_SOF_FN_BITS

#define DWC_DSTS_SOF_FN_BITS 0x0001fff8U

(Micro)Frame Number of Received SOF Access: RO

◆ DWC_DSTS_SOF_FN_SHIFT

#define DWC_DSTS_SOF_FN_SHIFT 3U

◆ DWC_DSTS_RXFIFO_EMPTY_BIT

#define DWC_DSTS_RXFIFO_EMPTY_BIT 0x00020000U

RX Fifo Empty Access: RO

◆ DWC_DSTS_RXFIFO_EMPTY_SHIFT

#define DWC_DSTS_RXFIFO_EMPTY_SHIFT 17U

◆ DWC_DSTS_USBLNK_STATE_BITS

#define DWC_DSTS_USBLNK_STATE_BITS 0x003c0000U

USB/Link State Access: RO

◆ DWC_DSTS_USBLNK_STATE_SHIFT

#define DWC_DSTS_USBLNK_STATE_SHIFT 18U

◆ DWC_DSTS_DEV_CTRL_HLT_BIT

#define DWC_DSTS_DEV_CTRL_HLT_BIT 0x00400000U

USB/Link State values same as for devt_data_t Device Controller Halted Access: RO

◆ DWC_DSTS_DEV_CTRL_HLT_SHIFT

#define DWC_DSTS_DEV_CTRL_HLT_SHIFT 22U

◆ DWC_DSTS_CORE_IDLE_BIT

#define DWC_DSTS_CORE_IDLE_BIT 0x00800000U

Core Idle Access: RO

◆ DWC_DSTS_CORE_IDLE_SHIFT

#define DWC_DSTS_CORE_IDLE_SHIFT 23U

◆ DWC_DSTS_SSS_BIT

#define DWC_DSTS_SSS_BIT 0x01000000U

Save State Status Access: RO

◆ DWC_DSTS_SSS_SHIFT

#define DWC_DSTS_SSS_SHIFT 24U

◆ DWC_DSTS_RSS_BIT

#define DWC_DSTS_RSS_BIT 0x02000000U

Restore State Status Access: RO

◆ DWC_DSTS_RSS_SHIFT

#define DWC_DSTS_RSS_SHIFT 25U

◆ DWC_DSTS_SRE_BIT

#define DWC_DSTS_SRE_BIT 0x10000000U

Save/Restore Error Access: RO

◆ DWC_DSTS_SRE_SHIFT

#define DWC_DSTS_SRE_SHIFT 28U

◆ DWC_DSTS_LNR_BIT

#define DWC_DSTS_LNR_BIT 0x20000000U

Link-state Not Ready Access: RO

◆ DWC_DSTS_LNR_SHIFT

#define DWC_DSTS_LNR_SHIFT 29U

◆ DWC_DGCMD_PER_PARAM_SEL_BITS

#define DWC_DGCMD_PER_PARAM_SEL_BITS 0x000003ffU

Periodic Parameters - for DWC_DGCMD_SET_PERIODIC_PARAMS command

◆ DWC_DGCMD_PER_PARAM_SEL_SHIFT

#define DWC_DGCMD_PER_PARAM_SEL_SHIFT 0U

◆ DWC_DGCMDPAR_HOST_ROLE_REQ_BITS

#define DWC_DGCMDPAR_HOST_ROLE_REQ_BITS 0x00000003U

Host Role Request - for DWC_DGCMD_XMIT_HOST_ROLE_REQUEST command

◆ DWC_DGCMDPAR_HOST_ROLE_REQ_SHIFT

#define DWC_DGCMDPAR_HOST_ROLE_REQ_SHIFT 0U

◆ DWC_DGCMDPAR_HOST_ROLE_REQ_INITIATE

#define DWC_DGCMDPAR_HOST_ROLE_REQ_INITIATE 1U /** @< */

RSP Phase values - for DWC_DGCMD_XMIT_HOST_ROLE_REQUEST (older cores) or DWC_DGCMD_HOST_ROLE_REQ_DEV_NOTIF (newer cores)

◆ DWC_DGCMDPAR_HOST_ROLE_REQ_CONFIRM

#define DWC_DGCMDPAR_HOST_ROLE_REQ_CONFIRM 2U

◆ DWC_DGCMDPAR_DEV_NOTIF_TYPE_BITS

#define DWC_DGCMDPAR_DEV_NOTIF_TYPE_BITS 0x0000000fU

Notification Type - for DWC_DGCMD_XMIT_DEV_NOTIF command

◆ DWC_DGCMDPAR_DEV_NOTIF_TYPE_SHIFT

#define DWC_DGCMDPAR_DEV_NOTIF_TYPE_SHIFT 0U

◆ DWC_DGCMD_FUNCTION_WAKE_DEV_NOTIF

#define DWC_DGCMD_FUNCTION_WAKE_DEV_NOTIF 1U /** @< */

Notification Type values - for DWC_DGCMD_XMIT_DEV_NOTIF command

◆ DWC_DGCMD_LATENCY_TOL_DEV_NOTIF

#define DWC_DGCMD_LATENCY_TOL_DEV_NOTIF 2U /** @< */

◆ DWC_DGCMD_BUS_INTVL_ADJ_DEV_NOTIF

#define DWC_DGCMD_BUS_INTVL_ADJ_DEV_NOTIF 3U /** @< */

◆ DWC_DGCMD_HOST_ROLE_REQ_DEV_NOTIF

#define DWC_DGCMD_HOST_ROLE_REQ_DEV_NOTIF 4U

◆ DWC_DGCMDPAR_DEV_NOTIF_PARAM_BITS

#define DWC_DGCMDPAR_DEV_NOTIF_PARAM_BITS 0xfffffff0U

Notification Parameters - for DWC_DGCMD_XMIT_DEV_NOTIF command

◆ DWC_DGCMDPAR_DEV_NOTIF_PARAM_SHIFT

#define DWC_DGCMDPAR_DEV_NOTIF_PARAM_SHIFT 4U

◆ DWC_DGCMDPAR_BELT_VALUE_BITS

#define DWC_DGCMDPAR_BELT_VALUE_BITS 0x000003ffU

Best Effort Latency Tolerance Value - for DWC_DGCMD_LATENCY_TOL_DEV_NOTIF command type

◆ DWC_DGCMDPAR_BELT_VALUE_SHIFT

#define DWC_DGCMDPAR_BELT_VALUE_SHIFT 0U

◆ DWC_DGCMDPAR_BELT_SCALE_BITS

#define DWC_DGCMDPAR_BELT_SCALE_BITS 0x00000c00U

Best Effort Latency Tolerance Scale - for DWC_DGCMD_LATENCY_TOL_DEV_NOTIF command type

◆ DWC_DGCMDPAR_BELT_SCALE_SHIFT

#define DWC_DGCMDPAR_BELT_SCALE_SHIFT 10U

◆ DWC_LATENCY_VALUE_MULT_1024

#define DWC_LATENCY_VALUE_MULT_1024 1U /** @< */

Latency Scale values (ns)

◆ DWC_LATENCY_VALUE_MULT_32768

#define DWC_LATENCY_VALUE_MULT_32768 2U /** @< */

◆ DWC_LATENCY_VALUE_MULT_1048576

#define DWC_LATENCY_VALUE_MULT_1048576 3U

◆ DWC_DGCMD_TYP_BITS

#define DWC_DGCMD_TYP_BITS 0x0ffU

Command Type Access: R_W

◆ DWC_DGCMD_TYP_SHIFT

#define DWC_DGCMD_TYP_SHIFT 0U

◆ DWC_DGCMD_SET_PERIODIC_PARAMS

#define DWC_DGCMD_SET_PERIODIC_PARAMS 2U /** @< */

Command Type values

◆ DWC_DGCMD_XMIT_FUNC_WAKE_DEV_NOTIF

#define DWC_DGCMD_XMIT_FUNC_WAKE_DEV_NOTIF 3U /** @< */

◆ DWC_DGCMD_SET_SCRATCHPAD_ARRAY_ADR_LO

#define DWC_DGCMD_SET_SCRATCHPAD_ARRAY_ADR_LO 4U /** @< */

◆ DWC_DGCMD_SET_SCRATCHPAD_ARRAY_ADR_HI

#define DWC_DGCMD_SET_SCRATCHPAD_ARRAY_ADR_HI 5U /** @< */

◆ DWC_DGCMD_XMIT_HOST_ROLE_REQUEST

#define DWC_DGCMD_XMIT_HOST_ROLE_REQUEST 6U /** @< */

◆ DWC_DGCMD_XMIT_DEV_NOTIF

#define DWC_DGCMD_XMIT_DEV_NOTIF 7U /** @< */

◆ DWC_DGCMD_SELECTED_FIFO_FLUSH

#define DWC_DGCMD_SELECTED_FIFO_FLUSH 9U /** @< */

◆ DWC_DGCMD_ALL_FIFO_FLUSH

#define DWC_DGCMD_ALL_FIFO_FLUSH 10U /** @< */

◆ DWC_DGCMD_SET_EP_NRDY

#define DWC_DGCMD_SET_EP_NRDY 12U /** @< */

◆ DWC_DGCMD_RUN_SOC_BUS_LOOPBK_TST

#define DWC_DGCMD_RUN_SOC_BUS_LOOPBK_TST 16U

◆ DWC_DGCMD_IOC_BIT

#define DWC_DGCMD_IOC_BIT 0x100U

Command Interrupt on Complete Access: R_W

◆ DWC_DGCMD_IOC_SHIFT

#define DWC_DGCMD_IOC_SHIFT 8U

◆ DWC_DGCMD_ACT_BIT

#define DWC_DGCMD_ACT_BIT 0x400U

Command Active Access: R_W

◆ DWC_DGCMD_ACT_SHIFT

#define DWC_DGCMD_ACT_SHIFT 10U

◆ DWC_DGCMD_STS_BITS

#define DWC_DGCMD_STS_BITS 0xf000U

Command Status Access: R_W

◆ DWC_DGCMD_STS_SHIFT

#define DWC_DGCMD_STS_SHIFT 12U

◆ DWC_DGCMD_STS_ERROR

#define DWC_DGCMD_STS_ERROR 15U

Command Status values

◆ DWC_EPMAP_RES_NUM_BITS

#define DWC_EPMAP_RES_NUM_BITS 0x1fU

This enum represents the bit fields in the Device Endpoint Mapping Registers (DEPMAPn). Resource Number Access: R_W / RO

◆ DWC_EPMAP_RES_NUM_SHIFT

#define DWC_EPMAP_RES_NUM_SHIFT 0U

◆ DWC_DEV_GLOBAL_REG_OFFSET

#define DWC_DEV_GLOBAL_REG_OFFSET 0x700U

◆ DWC_EPCFG1_INTRNUM_BITS

#define DWC_EPCFG1_INTRNUM_BITS 0x0000003fU

This enum represents the bit fields in the Device Endpoint Command Parameter 1 Register (DEPCMDPAR1n) for the Set Endpoint Configuration (DEPCFG) command. Interrupt number

◆ DWC_EPCFG1_INTRNUM_SHIFT

#define DWC_EPCFG1_INTRNUM_SHIFT 0U

◆ DWC_EPCFG1_XFER_CMPL_BIT

#define DWC_EPCFG1_XFER_CMPL_BIT 0x00000100U

Stream Completed

◆ DWC_EPCFG1_XFER_CMPL_SHIFT

#define DWC_EPCFG1_XFER_CMPL_SHIFT 8U

◆ DWC_EPCFG1_XFER_IN_PROG_BIT

#define DWC_EPCFG1_XFER_IN_PROG_BIT 0x00000200U

Stream In Progress

◆ DWC_EPCFG1_XFER_IN_PROG_SHIFT

#define DWC_EPCFG1_XFER_IN_PROG_SHIFT 9U

◆ DWC_EPCFG1_XFER_NRDY_BIT

#define DWC_EPCFG1_XFER_NRDY_BIT 0x00000400U

Stream Not Ready

◆ DWC_EPCFG1_XFER_NRDY_SHIFT

#define DWC_EPCFG1_XFER_NRDY_SHIFT 10U

◆ DWC_EPCFG1_FIFOXRUN_BIT

#define DWC_EPCFG1_FIFOXRUN_BIT 0x00000800U

Rx FIFO Underrun / Tx FIFO Overrun

◆ DWC_EPCFG1_FIFOXRUN_SHIFT

#define DWC_EPCFG1_FIFOXRUN_SHIFT 11U

◆ DWC_EPCFG1_SETUP_PNDG_BIT

#define DWC_EPCFG1_SETUP_PNDG_BIT 0x00001000U

Back-to-Back Setup Packets Received

◆ DWC_EPCFG1_SETUP_PNDG_SHIFT

#define DWC_EPCFG1_SETUP_PNDG_SHIFT 12U

◆ DWC_EPCFG1_EPCMD_CMPL_BIT

#define DWC_EPCFG1_EPCMD_CMPL_BIT 0x00002000U

Endpoint Command Complete

◆ DWC_EPCFG1_EPCMD_CMPL_SHIFT

#define DWC_EPCFG1_EPCMD_CMPL_SHIFT 13U

◆ DWC_EPCFG1_BINTERVAL_BITS

#define DWC_EPCFG1_BINTERVAL_BITS 0x00ff0000U

Endpoint bInterval

◆ DWC_EPCFG1_BINTERVAL_SHIFT

#define DWC_EPCFG1_BINTERVAL_SHIFT 16U

◆ DWC_EPCFG1_STRM_CAP_BIT

#define DWC_EPCFG1_STRM_CAP_BIT 0x01000000U

Endpoint Stream Capability

◆ DWC_EPCFG1_STRM_CAP_SHIFT

#define DWC_EPCFG1_STRM_CAP_SHIFT 24U

◆ DWC_EPCFG1_EP_DIR_BIT

#define DWC_EPCFG1_EP_DIR_BIT 0x02000000U

Endpoint Direction

◆ DWC_EPCFG1_EP_DIR_SHIFT

#define DWC_EPCFG1_EP_DIR_SHIFT 25U

◆ DWC_EPCFG1_EP_NUM_BITS

#define DWC_EPCFG1_EP_NUM_BITS 0x3c000000U

Endpoint Number

◆ DWC_EPCFG1_EP_NUM_SHIFT

#define DWC_EPCFG1_EP_NUM_SHIFT 26

◆ DWC_EPCFG0_EPTYPE_BITS

#define DWC_EPCFG0_EPTYPE_BITS 0x00000006U

This enum represents the bit fields in the Device Endpoint Command Parameter 0 Register (DEPCMDPAR0n) for the Set Endpoint Configuration (DWC_EPCMD_SET_EP_CFG) command. Endpoint Type Access: R_W

◆ DWC_EPCFG0_EPTYPE_SHIFT

#define DWC_EPCFG0_EPTYPE_SHIFT 1U

◆ DWC_USB3_EP_TYPE_CONTROL

#define DWC_USB3_EP_TYPE_CONTROL 0U /** @< */

Endpoint Type values

◆ DWC_USB3_EP_TYPE_ISOC

#define DWC_USB3_EP_TYPE_ISOC 1U /** @< */

◆ DWC_USB3_EP_TYPE_BULK

#define DWC_USB3_EP_TYPE_BULK 2U /** @< */

◆ DWC_USB3_EP_TYPE_INTR

#define DWC_USB3_EP_TYPE_INTR 3U

◆ DWC_EPCFG0_MPS_BITS

#define DWC_EPCFG0_MPS_BITS 0x00003ff8U

Maximum Packet Size Access: R_W

◆ DWC_EPCFG0_MPS_SHIFT

#define DWC_EPCFG0_MPS_SHIFT 3U

◆ DWC_EPCFG0_FLOW_CTRL_STATE_BIT

#define DWC_EPCFG0_FLOW_CTRL_STATE_BIT 0x00010000U

Flow Control State Access: R_W

◆ DWC_EPCFG0_FLOW_CTRL_STATE_SHIFT

#define DWC_EPCFG0_FLOW_CTRL_STATE_SHIFT 16U

◆ DWC_EPCFG0_TXFNUM_BITS

#define DWC_EPCFG0_TXFNUM_BITS 0x003e0000U

Tx Fifo Number (IN endpoints only) Access: R_W

◆ DWC_EPCFG0_TXFNUM_SHIFT

#define DWC_EPCFG0_TXFNUM_SHIFT 17U

◆ DWC_EPCFG0_BRSTSIZ_BITS

#define DWC_EPCFG0_BRSTSIZ_BITS 0x03c00000U

Burst Size Access: R_W

◆ DWC_EPCFG0_BRSTSIZ_SHIFT

#define DWC_EPCFG0_BRSTSIZ_SHIFT 22U

◆ DWC_EPCFG0_DSNUM_BITS

#define DWC_EPCFG0_DSNUM_BITS 0x7c000000U

Data Sequence Num (old) Access: R_W

◆ DWC_EPCFG0_DSNUM_SHIFT

#define DWC_EPCFG0_DSNUM_SHIFT 26U

◆ DWC_EPCFG0_IGN_DSNUM_BIT

#define DWC_EPCFG0_IGN_DSNUM_BIT 0x80000000U

Ignore Data Sequence Num (old) Access: R_W

◆ DWC_EPCFG0_IGN_DSNUM_SHIFT

#define DWC_EPCFG0_IGN_DSNUM_SHIFT 31U

◆ DWC_EPCFG0_CFG_ACTION_BITS

#define DWC_EPCFG0_CFG_ACTION_BITS 0xc0000000U

Config Action (new) Access: R_W

◆ DWC_EPCFG0_CFG_ACTION_SHIFT

#define DWC_EPCFG0_CFG_ACTION_SHIFT 30U

◆ DWC_CFG_ACTION_INIT

#define DWC_CFG_ACTION_INIT 0U /** @< */

Config Action values (new)

◆ DWC_CFG_ACTION_RESTORE

#define DWC_CFG_ACTION_RESTORE 1U /** @< */

◆ DWC_CFG_ACTION_MODIFY

#define DWC_CFG_ACTION_MODIFY 2U

◆ DWC_EPCMD_TYP_BITS

#define DWC_EPCMD_TYP_BITS 0x0ffU

Command Type Access: R_W

◆ DWC_EPCMD_TYP_SHIFT

#define DWC_EPCMD_TYP_SHIFT 0U

◆ DWC_EPCMD_SET_EP_CFG

#define DWC_EPCMD_SET_EP_CFG 1U /** @< */

Command Type values

◆ DWC_EPCMD_SET_XFER_CFG

#define DWC_EPCMD_SET_XFER_CFG 2U /** @< */

◆ DWC_EPCMD_GET_EP_STATE

#define DWC_EPCMD_GET_EP_STATE 3U /** @< */

◆ DWC_EPCMD_SET_STALL

#define DWC_EPCMD_SET_STALL 4U /** @< */

◆ DWC_EPCMD_CLR_STALL

#define DWC_EPCMD_CLR_STALL 5U /** @< */

◆ DWC_EPCMD_START_XFER

#define DWC_EPCMD_START_XFER 6U /** @< */

◆ DWC_EPCMD_UPDATE_XFER

#define DWC_EPCMD_UPDATE_XFER 7U /** @< */

◆ DWC_EPCMD_END_XFER

#define DWC_EPCMD_END_XFER 8U /** @< */

◆ DWC_EPCMD_START_NEW_CFG

#define DWC_EPCMD_START_NEW_CFG 9U

◆ DWC_EPCMD_IOC_BIT

#define DWC_EPCMD_IOC_BIT 0x100U

Command Interrupt on Complete Access: R_W

◆ DWC_EPCMD_IOC_SHIFT

#define DWC_EPCMD_IOC_SHIFT 8U

◆ DWC_EPCMD_ACT_BIT

#define DWC_EPCMD_ACT_BIT 0x400U

Command Active Access: R_W

◆ DWC_EPCMD_ACT_SHIFT

#define DWC_EPCMD_ACT_SHIFT 10U

◆ DWC_EPCMD_HP_FRM_BIT

#define DWC_EPCMD_HP_FRM_BIT 0x800U

High Priority / Force RM Bit Access: R_W

◆ DWC_EPCMD_HP_FRM_SHIFT

#define DWC_EPCMD_HP_FRM_SHIFT 11U

◆ DWC_EPCMD_CMPL_STS_BITS

#define DWC_EPCMD_CMPL_STS_BITS 0xf000U

Command Completion Status Access: R_W

◆ DWC_EPCMD_CMPL_STS_SHIFT

#define DWC_EPCMD_CMPL_STS_SHIFT 12U

◆ DWC_EPCMD_STR_NUM_OR_UF_BITS

#define DWC_EPCMD_STR_NUM_OR_UF_BITS 0xffff0000U

Stream Number or uFrame (input) Access: R_W

◆ DWC_EPCMD_STR_NUM_OR_UF_SHIFT

#define DWC_EPCMD_STR_NUM_OR_UF_SHIFT 16U

◆ DWC_EPCMD_XFER_RSRC_IDX_BITS

#define DWC_EPCMD_XFER_RSRC_IDX_BITS 0x007f0000U

Transfer Resource Index (output) Access: R_W

◆ DWC_EPCMD_XFER_RSRC_IDX_SHIFT

#define DWC_EPCMD_XFER_RSRC_IDX_SHIFT 16U

◆ DWC_DEV_OUT_EP_REG_OFFSET

#define DWC_DEV_OUT_EP_REG_OFFSET 0x800U

◆ DWC_DEV_IN_EP_REG_OFFSET

#define DWC_DEV_IN_EP_REG_OFFSET 0x810U

◆ DWC_EP_REG_OFFSET

#define DWC_EP_REG_OFFSET 0x20U

◆ DWC_DSCSTS_XFRCNT_BITS

#define DWC_DSCSTS_XFRCNT_BITS 0x00ffffffU

Transfer Count

◆ DWC_DSCSTS_XFRCNT_SHIFT

#define DWC_DSCSTS_XFRCNT_SHIFT 0U

◆ DWC_DSCSTS_PCM1_BITS

#define DWC_DSCSTS_PCM1_BITS 0x03000000U

Packet Count Minus 1 (for HS IN transfers)

◆ DWC_DSCSTS_PCM1_SHIFT

#define DWC_DSCSTS_PCM1_SHIFT 24U

◆ DWC_DSCSTS_TRBRSP_BITS

#define DWC_DSCSTS_TRBRSP_BITS 0xf0000000U

Transfer Request Block Response

◆ DWC_DSCSTS_TRBRSP_SHIFT

#define DWC_DSCSTS_TRBRSP_SHIFT 28U

◆ DWC_TRBRSP_MISSED_ISOC_IN

#define DWC_TRBRSP_MISSED_ISOC_IN 1U /** @< */

Response values

◆ DWC_TRBRSP_SETUP_PEND

#define DWC_TRBRSP_SETUP_PEND 2U /** @< */

◆ DWC_TRBRSP_XFER_IN_PROG

#define DWC_TRBRSP_XFER_IN_PROG 4U

◆ DWC_DSCCTL_HWO_BIT

#define DWC_DSCCTL_HWO_BIT 0x00000001U

Hardware-Owned bit

◆ DWC_DSCCTL_HWO_SHIFT

#define DWC_DSCCTL_HWO_SHIFT 0U

◆ DWC_DSCCTL_LST_BIT

#define DWC_DSCCTL_LST_BIT 0x00000002U

Last Descriptor bit

◆ DWC_DSCCTL_LST_SHIFT

#define DWC_DSCCTL_LST_SHIFT 1U

◆ DWC_DSCCTL_CHN_BIT

#define DWC_DSCCTL_CHN_BIT 0x00000004U

Chain Buffer bit

◆ DWC_DSCCTL_CHN_SHIFT

#define DWC_DSCCTL_CHN_SHIFT 2U

◆ DWC_DSCCTL_CSP_BIT

#define DWC_DSCCTL_CSP_BIT 0x00000008U

Continue on Short Packet bit

◆ DWC_DSCCTL_CSP_SHIFT

#define DWC_DSCCTL_CSP_SHIFT 3U

◆ DWC_DSCCTL_TRBCTL_BITS

#define DWC_DSCCTL_TRBCTL_BITS 0x000003f0U

Transfer Request Block Control field

◆ DWC_DSCCTL_TRBCTL_SHIFT

#define DWC_DSCCTL_TRBCTL_SHIFT 4U

◆ DWC_DSCCTL_TRBCTL_NORMAL

#define DWC_DSCCTL_TRBCTL_NORMAL 1 /** @< */

Transfer Request Block Control types

◆ DWC_DSCCTL_TRBCTL_SETUP

#define DWC_DSCCTL_TRBCTL_SETUP 2 /** @< */

◆ DWC_DSCCTL_TRBCTL_STATUS_2

#define DWC_DSCCTL_TRBCTL_STATUS_2 3 /** @< */

◆ DWC_DSCCTL_TRBCTL_STATUS_3

#define DWC_DSCCTL_TRBCTL_STATUS_3 4 /** @< */

◆ DWC_DSCCTL_TRBCTL_CTLDATA_1ST

#define DWC_DSCCTL_TRBCTL_CTLDATA_1ST 5 /** @< */

◆ DWC_DSCCTL_TRBCTL_ISOC_1ST

#define DWC_DSCCTL_TRBCTL_ISOC_1ST 6 /** @< */

◆ DWC_DSCCTL_TRBCTL_ISOC

#define DWC_DSCCTL_TRBCTL_ISOC 7 /** @< */

◆ DWC_DSCCTL_TRBCTL_LINK

#define DWC_DSCCTL_TRBCTL_LINK 8

◆ DWC_DSCCTL_ISP_BIT

#define DWC_DSCCTL_ISP_BIT 0x00000400U

Interrupt on Short Packet bit

◆ DWC_DSCCTL_ISP_SHIFT

#define DWC_DSCCTL_ISP_SHIFT 10U

◆ DWC_DSCCTL_IMI_BIT

#define DWC_DSCCTL_IMI_BIT DWC_DSCCTL_ISP_BIT

◆ DWC_DSCCTL_IMI_SHIFT

#define DWC_DSCCTL_IMI_SHIFT DWC_DSCCTL_ISP_SHIFT

◆ DWC_DSCCTL_IOC_BIT

#define DWC_DSCCTL_IOC_BIT 0x00000800U

Interrupt on Completion bit

◆ DWC_DSCCTL_IOC_SHIFT

#define DWC_DSCCTL_IOC_SHIFT 11U

◆ DWC_DSCCTL_STRMID_SOFN_BITS

#define DWC_DSCCTL_STRMID_SOFN_BITS 0x3fffc000U

Stream ID / SOF Number

◆ DWC_DSCCTL_STRMID_SOFN_SHIFT

#define DWC_DSCCTL_STRMID_SOFN_SHIFT 14U