hw.h

Go to the documentation of this file.

/* ==========================================================================
 * $File: //dwh/usb_iip/dev/software/DWC_usb3/driver/hw.h $
 * $Revision: #60 $
 * $Date: 2013/12/17 $
 * $Change: 2392669 $
 *
 * Synopsys SS USB3 Linux Software Driver and documentation (hereinafter,
 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
 * otherwise expressly agreed to in writing between Synopsys and you.
 *
 * The Software IS NOT an item of Licensed Software or Licensed Product under
 * any End User Software License Agreement or Agreement for Licensed Product
 * with Synopsys or any supplement thereto. You are permitted to use and
 * redistribute this Software in source and binary forms, with or without
 * modification, provided that redistributions of source code must retain this
 * notice. You may not view, use, disclose, copy or distribute this file or
 * any information contained herein except pursuant to this license grant from
 * Synopsys. If you do not agree with this notice, including the disclaimer
 * below, then you are not authorized to use the Software.
 *
 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
 * DAMAGE.
 * ========================================================================== */
 
#ifndef _DWC_USB3_REGS_H_
#define _DWC_USB3_REGS_H_
 
#ifdef __cplusplus
extern "C" {
#endif
 
/****************************************************************************/
/* Core Global Registers */
 
#define DWC_SBUSCFG0_HBURSTLEN_BITS 0x000000ffU 
#define DWC_SBUSCFG0_HBURSTLEN_SHIFT        0U  
#define DWC_SBUSCFG0_INT_DMA_BURST_SINGLE   0U   
#define DWC_SBUSCFG0_INT_DMA_BURST_INCR     1U   
#define DWC_SBUSCFG0_INT_DMA_BURST_INCR4    3U   
#define DWC_SBUSCFG0_INT_DMA_BURST_INCR8    7U   
#define DWC_SBUSCFG0_INT_DMA_BURST_INCR16   15U  
#define DWC_SBUSCFG0_INT_DMA_BURST_INCR32   31U  
#define DWC_SBUSCFG0_INT_DMA_BURST_INCR64   63U  
#define DWC_SBUSCFG0_INT_DMA_BURST_INCR128  127U 
#define DWC_SBUSCFG0_INT_DMA_BURST_INCR256  255U 
#define DWC_SBUSCFG0_DES_WR_POST_BIT            0x00000100U
#define DWC_SBUSCFG0_DES_WR_POST_SHIFT          8U
 
#define DWC_SBUSCFG0_DAT_WR_POST_BIT            0x00000200U
#define DWC_SBUSCFG0_DAT_WR_POST_SHIFT          9U
 
#define DWC_SBUSCFG0_DES_BIG_END_BIT            0x00000400U
#define DWC_SBUSCFG0_DES_BIG_END_SHIFT          10U
 
#define DWC_SBUSCFG0_DAT_BIG_END_BIT            0x00000800U
#define DWC_SBUSCFG0_DAT_BIG_END_SHIFT          11U
 
#define DWC_SBUSCFG0_STORE_AND_FORWARD_BIT      0x00001000U
#define DWC_SBUSCFG0_STORE_AND_FORWARD_SHIFT    12U
 
#define DWC_SBUSCFG0_SING_REQ_BIT               0x00004000U
#define DWC_SBUSCFG0_SING_REQ_SHIFT             14U
 
#define DWC_SBUSCFG0_READ_AFTER_WRITE_BIT       0x00008000U
#define DWC_SBUSCFG0_READ_AFTER_WRITE_SHIFT     15U
 
#define DWC_SBUSCFG0_DES_WR_REQ_INFO_BITS       0x000f0000U
#define DWC_SBUSCFG0_DES_WR_REQ_INFO_SHIFT      16U
 
#define DWC_SBUSCFG0_DAT_WR_REQ_INFO_BITS       0x00f00000U
#define DWC_SBUSCFG0_DAT_WR_REQ_INFO_SHIFT      20U
 
#define DWC_SBUSCFG0_DES_RD_REQ_INFO_BITS       0x0f000000U
#define DWC_SBUSCFG0_DES_RD_REQ_INFO_SHIFT      24U
 
#define DWC_SBUSCFG0_DAT_RD_REQ_INFO_BITS       0xf0000000U
#define DWC_SBUSCFG0_DAT_RD_REQ_INFO_SHIFT      28U
 
#define DWC_SBUSCFG1_DES_ADDR_SPC_BITS          0x0000000fU
#define DWC_SBUSCFG1_DES_ADDR_SPC_SHIFT         0U
 
#define DWC_SBUSCFG1_DAT_ADDR_SPC_BITS          0x000000f0U
#define DWC_SBUSCFG1_DAT_ADDR_SPC_SHIFT         4U
 
#define DWC_TXTHRCTL_USB_MAX_TX_BURST_SIZE_BITS     0x00ff0000U
#define DWC_TXTHRCTL_USB_MAX_TX_BURST_SIZE_SHIFT    16U
 
#define DWC_TXTHRCTL_USB_TX_PKT_CNT_BITS            0x1f000000U
#define DWC_TXTHRCTL_USB_TX_PKT_CNT_SHIFT           24U
 
#define DWC_TXTHRCTL_USB_TX_PKT_CNT_EN_BIT          0x20000000U
#define DWC_TXTHRCTL_USB_TX_PKT_CNT_EN_SHIFT        29U
 
#define DWC_RXTHRCTL_USB_MAX_RX_BURST_SIZE_BITS     0x00f80000U
#define DWC_RXTHRCTL_USB_MAX_RX_BURST_SIZE_SHIFT    19U
 
#define DWC_RXTHRCTL_USB_RX_PKT_CNT_BITS            0x0f000000U
#define DWC_RXTHRCTL_USB_RX_PKT_CNT_SHIFT           24U
 
#define DWC_RXTHRCTL_USB_RX_PKT_CNT_EN_BIT          0x20000000U
#define DWC_RXTHRCTL_USB_RX_PKT_CNT_EN_SHIFT        29U
 
#define DWC_GCTL_DSBL_CLCK_GTNG_BIT         0x00000001U
#define DWC_GCTL_DSBL_CLCK_GTNG_SHIFT       0U
 
#define DWC_GCTL_GBL_HIBER_EN_BIT           0x00000002U
#define DWC_GCTL_GBL_HIBER_EN_SHIFT         1U
 
#define DWC_GCTL_DIS_SCRAMBLE_BIT           0x00000008U
#define DWC_GCTL_DIS_SCRAMBLE_SHIFT         3U
 
#define DWC_GCTL_SCALE_DOWN_BITS            0x00000030U
#define DWC_GCTL_SCALE_DOWN_SHIFT           4U
 
#define DWC_GCTL_RAM_CLK_SEL_BITS           0x000000c0U
#define DWC_GCTL_RAM_CLK_SEL_SHIFT          6U
 
#define DWC_GCTL_DEBUG_ATTACH_BIT           0x00000100U
#define DWC_GCTL_DEBUG_ATTACH_SHIFT         8U
 
#define DWC_GCTL_U1U2_TIMER_SCALE_BIT       0x00000200U
#define DWC_GCTL_U1U2_TIMER_SCALE_SHIFT     9U
 
#define DWC_GCTL_SOFITPSYNC_BIT             0x00000400U
#define DWC_GCTL_SOFITPSYNC_SHIFT           10U
 
#define DWC_GCTL_CORE_SOFT_RST_BIT          0x00000800U
#define DWC_GCTL_CORE_SOFT_RST_SHIFT        11U
 
#define DWC_GCTL_PRT_CAP_DIR_BITS           0x00003000U
#define DWC_GCTL_PRT_CAP_DIR_SHIFT          12U
 
#define DWC_GCTL_PRT_CAP_HOST           1U
#define DWC_GCTL_PRT_CAP_DEVICE         2U
#define DWC_GCTL_PRT_CAP_OTG            3U
 
#define DWC_GCTL_FRMSCLDWN_BITS             0x0000c000U
#define DWC_GCTL_FRMSCLDWN_SHIFT            14U
 
#define DWC_GCTL_U2RSTECN_BIT               0x00010000U
#define DWC_GCTL_U2RSTECN_SHIFT             16U
 
#define DWC_GCTL_BYPSSETADDR_BIT            0x00020000U
#define DWC_GCTL_BYPSSETADDR_SHIFT          17U
 
#define DWC_GCTL_MASTERFILTBYPASS_BIT       0x00040000U
#define DWC_GCTL_MASTERFILTBYPASS_SHIFT     18U
 
#define DWC_GCTL_PWR_DN_SCALE_BITS          0xfff80000U
#define DWC_GCTL_PWR_DN_SCALE_SHIFT         19U
 
#define DWC_GEVTEN_ULPI_CK_EVT_EN_BIT       0x00000001U
#define DWC_GEVTEN_ULPI_CK_EVT_SHIFT        0U
 
#define DWC_GEVTEN_I2C_EVT_EN_BIT           0x00000002U
#define DWC_GEVTEN_I2C_EVT_EN_SHIFT         1U
 
#define DWC_GSTS_CURMODE_BITS       0x00000003U
#define DWC_GSTS_CURMODE_SHIFT      0U
 
#define DWC_GSTS_DEVICE_MODE        0U
#define DWC_GSTS_HOST_MODE          1U
#define DWC_GSTS_DRD_MODE           2U
 
#define DWC_GSTS_BUS_ERR_ADDR_VLD_BIT       0x00000010U
#define DWC_GSTS_BUS_ERR_ADDR_VLD_SHIFT     4U
 
#define DWC_GSTS_CSR_TIMEOUT_BIT            0x00000020U
#define DWC_GSTS_CSR_TIMEOUT_SHIFT          5U
 
#define DWC_GSTS_DEV_EVT_PENDING_BIT        0x00000040U
#define DWC_GSTS_DEV_EVT_PENDING_SHIFT      6U
 
#define DWC_GSTS_HOST_EVT_PENDING_BIT       0x00000080U
#define DWC_GSTS_HOST_EVT_PENDING_SHIFT     7U
 
#define DWC_GSTS_ADP_EVT_PENDING_BIT        0x00000100U
#define DWC_GSTS_ADP_EVT_PENDING_SHIFT      8U
 
#define DWC_GSTS_BC_EVT_PENDING_BIT         0x00000200U
#define DWC_GSTS_BC_EVT_PENDING_SHIFT       9U
 
#define DWC_GSTS_OTG_EVT_PENDING_BIT        0x00000400U
#define DWC_GSTS_OTG_EVT_PENDING_SHIFT      10U
 
#define DWC_GSTS_SSIC_IP_BIT        0x00000800U
#define DWC_GSTS_SSIC_IP_SHIFT      11U
 
#define DWC_GSTS_CBELT_BITS         0xfff00000U
#define DWC_GSTS_CBELT_SHIFT        20U
 
#define DWC_HWP0_MODE_BITS          0x00000007U
#define DWC_HWP0_MODE_SHIFT         0U
 
#define DWC_HWP0_MBUS_TYPE_BITS     0x00000038U
#define DWC_HWP0_MBUS_TYPE_SHIFT    3U
 
#define DWC_HWP0_SBUS_TYPE_BITS     0x000000c0U
#define DWC_HWP0_SBUS_TYPE_SHIFT    6U
 
#define DWC_HWP0_MDWIDTH_BITS       0x0000ff00U
#define DWC_HWP0_MDWIDTH_SHIFT      8U
 
#define DWC_HWP0_SDWIDTH_BITS       0x00ff0000U
#define DWC_HWP0_SDWIDTH_SHIFT      16U
 
#define DWC_HWP0_AWIDTH_BITS        0x3f000000U
#define DWC_HWP0_AWIDTH_SHIFT       24U
 
#define DWC_HWP1_IDWIDTH_M1_BITS        0x00000007U
#define DWC_HWP1_IDWIDTH_M1_SHIFT       0U
 
#define DWC_HWP1_BURSTWIDTH_M1_BITS     0x00000038U
#define DWC_HWP1_BURSTWIDTH_M1_SHIFT    3U
 
#define DWC_HWP1_DATAINFOWIDTH_BITS     0x000001c0U
#define DWC_HWP1_DATAINFOWIDTH_SHIFT    6U
 
#define DWC_HWP1_REQINFOWIDTH_BITS      0x00000e00U
#define DWC_HWP1_REQINFOWIDTH_SHIFT     9U
 
#define DWC_HWP1_ASPACEWIDTH_BITS       0x00007000U
#define DWC_HWP1_ASPACEWIDTH_SHIFT      12U
 
#define DWC_HWP1_DEV_NUM_INT_BITS       0x001f8000U
#define DWC_HWP1_DEV_NUM_INT_SHIFT      15U
 
#define DWC_HWP1_NUM_RAMS_BITS          0x00600000U
#define DWC_HWP1_NUM_RAMS_SHIFT         21U
 
#define DWC_HWP1_SPRAM_TYP_BIT          0x00800000U
#define DWC_HWP1_SPRAM_TYP_SHIFT        23U
 
#define DWC_HWP1_EN_PWROPT_BITS         0x03000000U
#define DWC_HWP1_EN_PWROPT_SHIFT        24U
 
#define DWC_EN_PWROPT_NONE              0U
#define DWC_EN_PWROPT_CLK_GATING_ONLY   1U
#define DWC_EN_PWROPT_HIBERNATION       2U
 
#define DWC_HWP1_MAC_PHY_CLKS_SYNC_BIT      0x04000000U
#define DWC_HWP1_MAC_PHY_CLKS_SYNC_SHIFT    26U
 
#define DWC_HWP1_MAC_RAM_CLKS_SYNC_BIT      0x08000000U
#define DWC_HWP1_MAC_RAM_CLKS_SYNC_SHIFT    27U
 
#define DWC_HWP1_RAM_BUS_CLKS_SYNC_BIT      0x10000000U
#define DWC_HWP1_RAM_BUS_CLKS_SYNC_SHIFT    28U
 
#define DWC_HWP1_RM_OPT_FEATURES_BIT        0x40000000U
#define DWC_HWP1_RM_OPT_FEATURES_SHIFT      30U
 
#define DWC_HWP2_USERID_BITS    0xffffffffU
#define DWC_HWP2_USERID_SHIFT   0U
 
#define DWC_HWP3_SSPHY_IFC_BITS         0x00000003U
#define DWC_HWP3_SSPHY_IFC_SHIFT        0U
 
#define DWC_HWP3_HSPHY_IFC_BITS         0x0000000cU
#define DWC_HWP3_HSPHY_IFC_SHIFT        2U
 
#define DWC_HWP3_FSPHY_IFC_BITS         0x00000030U
#define DWC_HWP3_FSPHY_IFC_SHIFT        4U
 
#define DWC_HWP3_HSPHY_DWIDTH_BITS      0x000000c0U
#define DWC_HWP3_HSPHY_DWIDTH_SHIFT     6U
 
#define DWC_HWP3_VEND_CTL_IFC_BIT       0x00000400U
#define DWC_HWP3_VEND_CTL_IFC_SHIFT     10U
 
#define DWC_HWP3_ULPI_CARKIT_BIT        0x00000800U
#define DWC_HWP3_ULPI_CARKIT_SHIFT      11U
 
#define DWC_HWP3_NUM_EPS_BITS           0x0003f000U
#define DWC_HWP3_NUM_EPS_SHIFT          12U
 
#define DWC_HWP3_NUM_IN_EPS_BITS        0x007c0000U
#define DWC_HWP3_NUM_IN_EPS_SHIFT       18U
 
#define DWC_HWP3_TOT_XFR_RSRC_BITS      0x7f800000U
#define DWC_HWP3_TOT_XFR_RSRC_SHIFT     23U
 
#define DWC_HWP4_TRBS_PER_XFER_BITS         0x0000003fU
#define DWC_HWP4_TRBS_PER_XFER_SHIFT        0U
 
#define DWC_HWP4_HIBER_SPAD_BITS            0x0001e000U
#define DWC_HWP4_HIBER_SPAD_SHIFT           13U
 
#define DWC_HWP4_NUM_SS_USB_INST_BITS       0x001e0000U
#define DWC_HWP4_NUM_SS_USB_INST_SHIFT      17U
 
#define DWC_HWP4_EN_ISOC_SUPT_BIT           0x00800000U
#define DWC_HWP4_EN_ISOC_SUPT_SHIFT         23U
 
#define DWC_HWP4_BMU_PTL_DEPTH_BITS         0x0f000000U
#define DWC_HWP4_BMU_PTL_DEPTH_SHIFT        24U
 
#define DWC_HWP4_BMU_LSP_DEPTH_BITS         0xf0000000U
#define DWC_HWP4_BMU_LSP_DEPTH_SHIFT        28U
 
#define DWC_HWP5_BMU_BUSGM_DEPTH_BITS       0x0000000fU
#define DWC_HWP5_BMU_BUSGM_DEPTH_SHIFT      0U
 
#define DWC_HWP5_RXQ_FIFO_DEPTH_BITS        0x000003f0U
#define DWC_HWP5_RXQ_FIFO_DEPTH_SHIFT       4U
 
#define DWC_HWP5_TXQ_FIFO_DEPTH_BITS        0x0000fc00U
#define DWC_HWP5_TXQ_FIFO_DEPTH_SHIFT       10U
 
#define DWC_HWP5_DWQ_FIFO_DEPTH_BITS        0x003f0000U
#define DWC_HWP5_DWQ_FIFO_DEPTH_SHIFT       16U
 
#define DWC_HWP5_DFQ_FIFO_DEPTH_BITS        0x0fc00000U
#define DWC_HWP5_DFQ_FIFO_DEPTH_SHIFT       22U
 
#define DWC_HWP6_PSQ_FIFO_DEPTH_BITS    0x0000003fU
#define DWC_HWP6_PSQ_FIFO_DEPTH_SHIFT   0U
 
#define DWC_HWP6_EN_DBG_PORTS_BIT       0x00000040U
#define DWC_HWP6_EN_DBG_PORTS_SHIFT     6U
 
#define DWC_HWP6_EN_FPGA_BIT            0x00000080U
#define DWC_HWP6_EN_FPGA_SHIFT          7U
 
#define DWC_HWP6_EN_SRP_BIT             0x00000400U
#define DWC_HWP6_EN_SRP_SHIFT           10U
 
#define DWC_HWP6_EN_HNP_BIT             0x00000800U
#define DWC_HWP6_EN_HNP_SHIFT           11U
 
#define DWC_HWP6_EN_ADP_BIT             0x00001000U
#define DWC_HWP6_EN_ADP_SHIFT           12U
 
#define DWC_HWP6_EN_OTG_BIT             0x00002000U
#define DWC_HWP6_EN_OTG_SHIFT           13U
 
#define DWC_HWP6_EN_BC_BIT              0x00004000U
#define DWC_HWP6_EN_BC_SHIFT            14U
 
#define DWC_HWP6_EN_BUS_FILTERS_BIT     0x00008000U
#define DWC_HWP6_EN_BUS_FILTERS_SHIFT   15U
 
#define DWC_HWP6_RAM0_DEPTH_BITS        0xffff0000U
#define DWC_HWP6_RAM0_DEPTH_SHIFT       16U
 
#define DWC_HWP7_RAM1_DEPTH_BITS        0x0000ffffU
#define DWC_HWP7_RAM1_DEPTH_SHIFT       0U
 
#define DWC_HWP7_RAM2_DEPTH_BITS        0xffff0000U
#define DWC_HWP7_RAM2_DEPTH_SHIFT       16U
 
#define DWC_HWP8_DCACHE_DEPTH_BITS      0xffffffffU
#define DWC_HWP8_DCACHE_DEPTH_SHIFT     0U
 
#define DWC_DBGFIFOSPACE_FIFO_QUEUE_SEL_BITS    0x000000ffU
#define DWC_DBGFIFOSPACE_FIFO_QUEUE_SEL_SHIFT   0U
 
#define DWC_DBGFIFOSPACE_SPACE_AVAIL_BITS   0xffff0000U
#define DWC_DBGFIFOSPACE_SPACE_AVAIL_SHIFT  16U
 
#define DWC_DBGLTSSM_PIPE_STATUS_BITS       0x0003ffffU
#define DWC_DBGLTSSM_PIPE_STATUS_SHIFT      0U
 
#define DWC_DBGLTSSM_LTDB_SUB_STATE_BITS    0x003c0000U
#define DWC_DBGLTSSM_LTDB_SUB_STATE_SHIFT   18U
 
#define DWC_DBGLTSSM_LTDB_STATE_BITS        0x03c00000U
#define DWC_DBGLTSSM_LTDB_STATE_SHIFT       22U
 
#define DWC_DBGLTSSM_LTDB_TIMEOUT_BIT       0x04000000U
#define DWC_DBGLTSSM_LTDB_TIMEOUT_SHIFT     26U
 
#define DWC_RMMICTL_MPHY_STATE_BITS     0x0e000000U
#define DWC_RMMICTL_MPHY_STATE_SHIFT    25U
 
#define DWC_MPHY_STATE_DISABLED     0U
#define DWC_MPHY_STATE_HIBERN8      1U
#define DWC_MPHY_STATE_SLEEP        2U
#define DWC_MPHY_STATE_STALL        3U
#define DWC_MPHY_STATE_PWM_BURST    4U
#define DWC_MPHY_STATE_HS_BURST     5U
#define DWC_MPHY_STATE_LINE_CFG     6U
#define DWC_MPHY_STATE_LINE_RESET   7U
 
#define DWC_RMMICTL_AUTO_EXIT_RRAP_BIT      0x10000000U
#define DWC_RMMICTL_AUTO_EXIT_RRAP_SHIFT    28U
 
#define DWC_RMMICTL_AUTO_ROM_RRAP_BIT       0x20000000U
#define DWC_RMMICTL_AUTO_ROM_RRAP_SHIFT     29U
 
#define DWC_RMMICTL_AUTO_EXIT_H8_BIT        0x40000000U
#define DWC_RMMICTL_AUTO_EXIT_H8_SHIFT      30U
 
#define DWC_RMMICTL_AUTO_ROM_H8_BIT         0x80000000U
#define DWC_RMMICTL_AUTO_ROM_H8_SHIFT       31U
 
#define DWC_USB2PHYCFG_TOUT_CAL_BITS        0x00000007U
#define DWC_USB2PHYCFG_TOUT_CAL_SHIFT       0U
 
#define DWC_USB2PHYCFG_16B_PHY_IF_BIT       0x00000008U
#define DWC_USB2PHYCFG_16B_PHY_IF_SHIFT     3U
    /*--------*/
#define DWC_USB2PHYCFG_DDR_SEL_BIT          0x00000008U
#define DWC_USB2PHYCFG_DDR_SEL_SHIFT        3U
 
#define DWC_USB2PHYCFG_UTMI_ULPI_BIT        0x00000010U
#define DWC_USB2PHYCFG_UTMI_ULPI_SHIFT      4U
 
#define DWC_USB2PHYCFG_FSINTF_BIT           0x00000020U
#define DWC_USB2PHYCFG_FSINTF_SHIFT         5U
 
#define DWC_USB2PHYCFG_SUS_PHY_BIT          0x00000040U
#define DWC_USB2PHYCFG_SUS_PHY_SHIFT        6U
 
#define DWC_USB2PHYCFG_PHY_SEL_BIT          0x00000080U
#define DWC_USB2PHYCFG_PHY_SEL_SHIFT        7U
 
#define DWC_USB2PHYCFG_ENBL_SLP_M_BIT       0x00000100U
#define DWC_USB2PHYCFG_ENBL_SLP_M_SHIFT     8U
 
#define DWC_USB2PHYCFG_USB_TRD_TIM_BITS     0x00003c00U
#define DWC_USB2PHYCFG_USB_TRD_TIM_SHIFT    10U
 
#define DWC_USB2PHYCFG_PHY_LPWR_CLK_SEL_BIT     0x00004000U
#define DWC_USB2PHYCFG_PHY_LPWR_CLK_SEL_SHIFT   14U
 
#define DWC_USB2PHYCFG_ULPI_AUTO_RES_BIT        0x0000800U
#define DWC_USB2PHYCFG_ULPI_AUTO_RES_SHIFT      15U
 
#define DWC_USB2PHYCFG_ULPI_CLK_SUS_M_BIT       0x00010000U
#define DWC_USB2PHYCFG_ULPI_CLK_SUS_M_SHIFT     16U
 
#define DWC_USB2PHYCFG_ULPI_EXT_VBUS_DRV_BIT     0x00020000U
#define DWC_USB2PHYCFG_ULPI_EXT_VBUS_DRV_SHIFT   17U
 
#define DWC_USB2PHYCFG_ULPI_EXT_VBUS_IND_BIT     0x00040000U
#define DWC_USB2PHYCFG_ULPI_EXT_VBUS_IND_SHIFT   18U
 
#define DWC_USB2PHYCFG_PHY_INTR_NUM_BITS     0x01f80000U
#define DWC_USB2PHYCFG_PHY_INTR_NUM_SHIFT    19U
 
#define DWC_USB2PHYCFG_OTG_INTR_NUM_BITS     0x7e000000U
#define DWC_USB2PHYCFG_OTG_INTR_NUM_SHIFT    25U
 
#define DWC_USB2PHYCFG_PHY_SOFT_RST_BIT      0x80000000U
#define DWC_USB2PHYCFG_PHY_SOFT_RST_SHIFT    31U
 
#define DWC_USB2I2C_RSVD_BITS       0xffffffffU
#define DWC_USB2I2C_RSVD_SHIFT      0U
 
#define DWC_USB2PHY_REGDATA_BITS            0x000000ffU
#define DWC_USB2PHY_REGDATA_SHIFT           0U
 
#define DWC_USB2PHY_VCTRL_BITS              0x0000ff00U
#define DWC_USB2PHY_VCTRL_SHIFT             8U
    /*--------*/
#define DWC_USB2PHY_EXTREGADDR_BITS         0x00003f00U
#define DWC_USB2PHY_EXTREGADDR_SHIFT        8U
 
#define DWC_USB2PHY_REGADDR_BITS            0x003f0000U
#define DWC_USB2PHY_REGADDR_SHIFT           16U
 
#define DWC_USB2PHY_REGWR_BIT               0x00400000U
#define DWC_USB2PHY_REGWR_SHIFT             22U
 
#define DWC_USB2PHY_VSTSBSY_BIT             0x00800000U
#define DWC_USB2PHY_VSTSBSY_SHIFT           23U
 
#define DWC_USB2PHY_VSTSDONE_BIT            0x01000000U
#define DWC_USB2PHY_VSTSDONE_SHIFT          24U
 
#define DWC_USB2PHY_NEWREGREQ_BIT           0x02000000U
#define DWC_USB2PHY_NEWREGREQ_SHIFT         25U
 
#define DWC_USB2PHY_DIS_ULPI_DRVR_BIT       0x04000000U
#define DWC_USB2PHY_DIS_ULPI_DRVR_SHIFT     26U
 
#define DWC_PIPECTL_ELAS_BUF_MODE_BIT       0x00000001U
#define DWC_PIPECTL_ELAS_BUF_MODE_SHIFT     0U
 
#define DWC_PIPECTL_TX_DEMPH_BITS           0x00000006U
#define DWC_PIPECTL_TX_DEMPH_SHIFT          1U
 
#define DWC_PIPECTL_TX_MARGIN_BITS          0x00000038U
#define DWC_PIPECTL_TX_MARGIN_SHIFT         3U
 
#define DWC_PIPECTL_TX_SWING_BIT            0x00000040U
#define DWC_PIPECTL_TX_SWING_SHIFT          6U
 
#define DWC_PIPECTL_SSIC_EN_BIT             0x00000080U
#define DWC_PIPECTL_SSIC_EN_SHIFT           7U
 
#define DWC_PIPECTL_LFPS_FILTER_BIT         0x00000200U
#define DWC_PIPECTL_LFPS_FILTER_SHIFT       9U
 
#define DWC_PIPECTL_P3_EX_SIG_P2_BIT        0x00000400U
#define DWC_PIPECTL_P3_EX_SIG_P2_SHIFT      10U
 
#define DWC_PIPECTL_P3_P2_TRAN_OK_BIT       0x00000800U
#define DWC_PIPECTL_P3_P2_TRAN_OK_SHIFT     11U
 
#define DWC_PIPECTL_LFPS_P0_ALGN_BIT        0x00001000U
#define DWC_PIPECTL_LFPS_P0_ALGN_SHIFT      12U
 
#define DWC_PIPECTL_DATA_WIDTH_BITS         0x00018000U
#define DWC_PIPECTL_DATA_WIDTH_SHIFT        15U
 
#define DWC_PIPECTL_SUS_PHY_BIT             0x00020000U
#define DWC_PIPECTL_SUS_PHY_SHIFT           17U
 
#define DWC_PIPECTL_PHY_SOFT_RST_BIT        0x80000000U
#define DWC_PIPECTL_PHY_SOFT_RST_SHIFT      31U
 
#define DWC_FIFOSZ_DEPTH_BITS           0x0000ffffU
#define DWC_FIFOSZ_DEPTH_SHIFT          0U
 
#define DWC_FIFOSZ_STARTADDR_BITS       0xffff0000U
#define DWC_FIFOSZ_STARTADDR_SHIFT      16U
 
#define DWC_EVENTSIZ_SIZ_BITS           0x0000ffffU
#define DWC_EVENTSIZ_SIZ_SHIFT          0U
 
#define DWC_EVENTSIZ_INT_MSK_BIT        0x80000000U
#define DWC_EVENTSIZ_INT_MSK_SHIFT      31U
 
#define DWC_EVENTCNT_CNT_BITS           0x0000ffffU
#define DWC_EVENTCNT_CNT_SHIFT          0U
 
#define DWC_EVENT_NON_EP_BIT            0x01U
#define DWC_EVENT_NON_EP_SHIFT          0U
 
#define DWC_EVENT_INTTYPE_BITS          0xfeU
#define DWC_EVENT_INTTYPE_SHIFT         1U
 
#define DWC_EVENT_DEV_INT       0U  
#define DWC_EVENT_OTG_INT       1U  
#define DWC_EVENT_CARKIT_INT    3U  
#define DWC_EVENT_I2C_INT       4U
 
#define DWC_DEVT_BITS       0x00000f00U
#define DWC_DEVT_SHIFT      8U
 
#define DWC_DEVT_DISCONN                0U  
#define DWC_DEVT_USBRESET               1U  
#define DWC_DEVT_CONNDONE               2U  
#define DWC_DEVT_ULST_CHNG              3U  
#define DWC_DEVT_WKUP                   4U  
#define DWC_DEVT_HIBER_REQ              5U  
#define DWC_DEVT_U3_L2L1_SUSP           6U  
#define DWC_DEVT_SOF                    7U  
#define DWC_DEVT_ERRATICERR             9U  
#define DWC_DEVT_CMD_CMPL               10U 
#define DWC_DEVT_OVERFLOW               11U 
#define DWC_DEVT_VNDR_DEV_TST_RCVD      12U 
#define DWC_DEVT_INACT_TIMEOUT_RCVD     13U
 
#define DWC_DEVT_EVT_INFO_BITS          0xffff0000U
#define DWC_DEVT_EVT_INFO_SHIFT         16U
 
#define DWC_DEVT_ULST_STATE_BITS        0x000f0000U
#define DWC_DEVT_ULST_STATE_SHIFT       16U
 
#define DWC_LINK_STATE_U0           0U  
#define DWC_LINK_STATE_U1           1U  
#define DWC_LINK_STATE_U2           2U  
#define DWC_LINK_STATE_U3           3U  
#define DWC_LINK_STATE_SS_DIS       4U  
#define DWC_LINK_STATE_RX_DET       5U  
#define DWC_LINK_STATE_SS_INACT     6U  
#define DWC_LINK_STATE_POLL         7U  
#define DWC_LINK_STATE_RECOV        8U  
#define DWC_LINK_STATE_HRESET       9U  
#define DWC_LINK_STATE_CMPLY        10U 
#define DWC_LINK_STATE_LPBK         11U 
#define DWC_LINK_STATE_RESET        14U 
#define DWC_LINK_STATE_RESUME       15U
 
#define DWC_LINK_STATE_ON               0U  
#define DWC_LINK_STATE_SLEEP            2U  
#define DWC_LINK_STATE_SUSPEND          3U  
#define DWC_LINK_STATE_EARLY_SUSPEND    5U
 
#define DWC_DEVT_ULST_SS_BIT            0x00100000U
#define DWC_DEVT_ULST_SS_SHIFT          20U
 
#define DWC_DEVT_HIBER_STATE_BITS       DWC_DEVT_ULST_STATE_BITS
#define DWC_DEVT_HIBER_STATE_SHIFT      DWC_DEVT_ULST_STATE_SHIFT
 
#define DWC_DEVT_HIBER_SS_BIT           DWC_DEVT_ULST_SS_BIT
#define DWC_DEVT_HIBER_SS_SHIFT         DWC_DEVT_ULST_SS_SHIFT
 
#define DWC_DEVT_HIBER_HIRD_BITS        0x0f000000U
#define DWC_DEVT_HIBER_HIRD_SHIFT       24U
 
#define DWC_DEPEVT_EPNUM_BITS           0x0000003eU
#define DWC_DEPEVT_EPNUM_SHIFT          1U
 
#define DWC_DEPEVT_INTTYPE_BITS         0x000003c0U
#define DWC_DEPEVT_INTTYPE_SHIFT        6U
 
#define DWC_DEPEVT_XFER_CMPL        1U  
#define DWC_DEPEVT_XFER_IN_PROG     2U  
#define DWC_DEPEVT_XFER_NRDY        3U  
#define DWC_DEPEVT_FIFOXRUN         4U  
#define DWC_DEPEVT_STRM_EVT         6U  
#define DWC_DEPEVT_EPCMD_CMPL       7U
 
#define DWC_DEPEVT_NO_MORE_RSCS_BIT         0x00001000U
#define DWC_DEPEVT_NO_MORE_RSCS_SHIFT       12U
#define DWC_DEPEVT_ISOC_TIME_PASSED_BIT     0x00002000U
#define DWC_DEPEVT_ISOC_TIME_PASSED_SHIFT   13U
 
#define DWC_DEPEVT_STRM_EVT_BITS            0x0000f000U
#define DWC_DEPEVT_STRM_EVT_SHIFT           12U
 
#define DWC_DEPEVT_STRM_FOUND       1U  
#define DWC_DEPEVT_STRM_NOT_FOUND   2U
 
#define DWC_DEPEVT_BUS_ERR_BIT          0x00001000U
#define DWC_DEPEVT_BUS_ERR_SHIFT        12U
#define DWC_DEPEVT_SHORT_PKT_BIT        0x00002000U
#define DWC_DEPEVT_SHORT_PKT_SHIFT      13U
#define DWC_DEPEVT_IOC_BIT              0x00004000U
#define DWC_DEPEVT_IOC_SHIFT            14U
#define DWC_DEPEVT_LST_BIT              0x00008000U
#define DWC_DEPEVT_LST_SHIFT            15U
#define DWC_DEPEVT_MISSED_ISOC_BIT      DWC_DEPEVT_LST_BIT
#define DWC_DEPEVT_MISSED_ISOC_SHIFT    DWC_DEPEVT_LST_SHIFT
 
#define DWC_DEPEVT_CTRL_BITS            0x00003000U
#define DWC_DEPEVT_CTRL_SHIFT           12U
#define DWC_DEPEVT_XFER_ACTIVE_BIT      0x00008000U
#define DWC_DEPEVT_XFER_ACTIVE_SHIFT    15U
 
#define DWC_DEPEVT_CTRL_SETUP       0U  
#define DWC_DEPEVT_CTRL_DATA        1U  
#define DWC_DEPEVT_CTRL_STATUS      2U
 
#define DWC_DEPEVT_STRM_ID_BITS             0xffff0000U
#define DWC_DEPEVT_STRM_ID_SHIFT            16U
 
#define DWC_DEPEVT_ISOC_UFRAME_NUM_BITS     0xffff0000U
#define DWC_DEPEVT_ISOC_UFRAME_NUM_SHIFT    16U
 
#define DWC_DEPEVT_XFER_RSC_IDX_BITS        0x007f0000U
#define DWC_DEPEVT_XFER_RSC_IDX_SHIFT       16U
 
#define DWC_DEPEVT_CUR_DAT_SEQ_NUM_BITS     0x001f0000U
#define DWC_DEPEVT_CUR_DAT_SEQ_NUM_SHIFT    16U
 
#define DWC_DEPEVT_FLOW_CTRL_BIT            0x00200000U
#define DWC_DEPEVT_FLOW_CTRL_SHIFT          21U
 
#define DWC_GINT_PHY_PORT_BITS      0xf00U
#define DWC_GINT_PHY_PORT_SHIFT     8U
 
typedef struct geventbuf_data {
    volatile u32 geventadr_lo;
 
    volatile u32 geventadr_hi;
 
    volatile u32 geventsiz;
 
    volatile u32 geventcnt;
} geventbuf_data_t;
 
typedef struct dwc_usb3_core_global_regs {
 
#define DWC_CORE_GLOBAL_REG_OFFSET  0x100U
 
    volatile u32 gsbuscfg0;
 
    volatile u32 gsbuscfg1;
 
    volatile u32 gtxthrcfg;
 
    volatile u32 grxthrcfg;
 
    volatile u32 gctl;
 
    volatile u32 gevten;
 
    volatile u32 gsts;
 
    volatile u32 reserved0;
 
    volatile u32 gsnpsid;
 
    volatile u32 ggpio;
 
    volatile u32 guid;
 
    volatile u32 reserved1;
 
    volatile u32 gbuserraddrlo;
 
    volatile u32 gbuserraddrhi;
 
    volatile u32 gprtbimap_lo;
 
    volatile u32 gprtbimap_hi;
 
    volatile u32 ghwparams0;
 
    volatile u32 ghwparams1;
 
    volatile u32 ghwparams2;
 
    volatile u32 ghwparams3;
 
    volatile u32 ghwparams4;
 
    volatile u32 ghwparams5;
 
    volatile u32 ghwparams6;
 
    volatile u32 ghwparams7;
 
    volatile u32 gdbgfifospace;
 
    volatile u32 gdbgltssm;
 
    volatile u32 gdbglnmcc;
 
    volatile u32 gdbgbmu;
 
    volatile u32 gdbglspmux;
 
    volatile u32 gdbglsp;
 
    volatile u32 gdbgepinfo0;
 
    volatile u32 gdbgepinfo1;
 
    volatile u32 gprtbimap_hs_lo;
 
    volatile u32 gprtbimap_hs_hi;
 
    volatile u32 gprtbimap_fs_lo;
 
    volatile u32 gprtbimap_fs_hi;
 
    volatile u32 reserved4[12];
 
    volatile u32 gusb3rmmictl[16];
 
    volatile u32 gusb2phycfg[16];
 
    volatile u32 gusb2i2cctl[16];
 
    volatile u32 gusb2phyacc[16];
 
    volatile u32 gusb3pipectl[16];
 
    volatile u32 gtxfifosiz[32];
 
    volatile u32 grxfifosiz[32];
 
    struct geventbuf_data geventbuf[32];
 
    volatile u32 ghwparams8;
} dwc_usb3_core_global_regs_t;
 
 
/****************************************************************************/
/* Device Global Registers */
 
#define DWC_DCFG_DEVSPD_BITS        0x000007U
#define DWC_DCFG_DEVSPD_SHIFT       0U
 
#define DWC_SPEED_HS_PHY_30MHZ_OR_60MHZ     0U  
#define DWC_SPEED_FS_PHY_30MHZ_OR_60MHZ     1U  
#define DWC_SPEED_LS_PHY_6MHZ               2U  
#define DWC_SPEED_FS_PHY_48MHZ              3U  
#define DWC_SPEED_SS_PHY_125MHZ_OR_250MHZ   4U
 
#define DWC_DCFG_DEVADDR_BITS       0x0003f8U
#define DWC_DCFG_DEVADDR_SHIFT      3U
 
#define DWC_DCFG_PER_FR_INTVL_BITS      0x000c00U
#define DWC_DCFG_PER_FR_INTVL_SHIFT     10U
 
#define DWC_DCFG_PER_FR_INTVL_80        0U  
#define DWC_DCFG_PER_FR_INTVL_85        1U  
#define DWC_DCFG_PER_FR_INTVL_90        2U  
#define DWC_DCFG_PER_FR_INTVL_95        3U
 
#define DWC_DCFG_DEV_INTR_NUM_BITS      0x01f000U
#define DWC_DCFG_DEV_INTR_NUM_SHIFT     12U
 
#define DWC_DCFG_NUM_RCV_BUF_BITS       0x3e0000U
#define DWC_DCFG_NUM_RCV_BUF_SHIFT      17U
 
#define DWC_DCFG_LPM_CAP_BIT            0x400000U
#define DWC_DCFG_LPM_CAP_SHIFT          22U
 
#define DWC_DCTL_SFT_DISCONN_BIT        0x00000001U
#define DWC_DCTL_SFT_DISCONN_SHIFT      0U
 
#define DWC_DCTL_TSTCTL_BITS            0x0000001eU
#define DWC_DCTL_TSTCTL_SHIFT           1U
 
#define DWC_DCTL_ULST_CHNG_REQ_BITS         0x000001e0U
#define DWC_DCTL_ULST_CHNG_REQ_SHIFT        5U
 
#define DWC_LINK_STATE_REQ_NO_ACTION        0U  
#define DWC_LINK_STATE_REQ_SS_DISABLED      4U  
#define DWC_LINK_STATE_REQ_RX_DETECT        5U  
#define DWC_LINK_STATE_REQ_INACTIVE         6U  
#define DWC_LINK_STATE_REQ_RECOVERY         8U  
#define DWC_LINK_STATE_REQ_COMPLIANCE       10U 
#define DWC_LINK_STATE_REQ_LOOPBACK         11U 
#define DWC_LINK_STATE_REQ_HOST_MODE_ONLY   15U
 
#define DWC_LINK_STATE_REQ_REMOTE_WAKEUP    8U
 
#define DWC_DCTL_ACCEPT_U1_EN_BIT       0x00000200U
#define DWC_DCTL_ACCEPT_U1_EN_SHIFT     9U
#define DWC_DCTL_INIT_U1_EN_BIT         0x00000400U
#define DWC_DCTL_INIT_U1_EN_SHIFT       10U
#define DWC_DCTL_ACCEPT_U2_EN_BIT       0x00000800U
#define DWC_DCTL_ACCEPT_U2_EN_SHIFT     11U
#define DWC_DCTL_INIT_U2_EN_BIT         0x00001000U
#define DWC_DCTL_INIT_U2_EN_SHIFT       12U
 
#define DWC_DCTL_CSS_BIT                    0x00010000U
#define DWC_DCTL_CSS_SHIFT                  16U
 
#define DWC_DCTL_CRS_BIT                    0x00020000U
#define DWC_DCTL_CRS_SHIFT                  17U
 
#define DWC_DCTL_L1_HIBER_EN_BIT            0x00040000U
#define DWC_DCTL_L1_HIBER_EN_RES_SHIFT      18U
 
#define DWC_DCTL_KEEP_CONNECT_BIT           0x00080000U
#define DWC_DCTL_KEEP_CONNECT_SHIFT         19U
 
#define DWC_DCTL_LPM_NYET_THRESH_BITS       0x00f00000U
#define DWC_DCTL_LPM_NYET_THRESH_SHIFT      20U
 
#define DWC_DCTL_APP_L1_RES_BIT             0x00800000U
#define DWC_DCTL_APP_L1_RES_SHIFT           23U
 
    /* HIRD Threshold           <i>Access: R_W</i> */
#define DWC_DCTL_HIRD_THR_BITS              0x1f000000U
#define DWC_DCTL_HIRD_THR_SHIFT             24U
 
#define DWC_DCTL_LSFT_RST_BIT               0x20000000U
#define DWC_DCTL_LSFT_RST_SHIFT             29U
 
#define DWC_DCTL_CSFT_RST_BIT               0x40000000U
#define DWC_DCTL_CSFT_RST_SHIFT             30U
 
#define DWC_DCTL_RUN_STOP_BIT               0x80000000U
#define DWC_DCTL_RUN_STOP_SHIFT             31U
 
#define DWC_DEVTEN_DISCONN_BIT              0x0001U
#define DWC_DEVTEN_DISCONN_SHIFT            0U
 
#define DWC_DEVTEN_USBRESET_BIT             0x0002U
#define DWC_DEVTEN_USBRESET_SHIFT           1U
 
#define DWC_DEVTEN_CONNDONE_BIT             0x0004U
#define DWC_DEVTEN_CONNDONE_SHIFT           2U
 
#define DWC_DEVTEN_ULST_CHNG_BIT            0x0008U
#define DWC_DEVTEN_ULST_CHNG_SHIFT          3U
 
#define DWC_DEVTEN_WKUP_BIT                 0x0010U
#define DWC_DEVTEN_WKUP_SHIFT               4U
 
#define DWC_DEVTEN_HIBER_REQ_BIT            0x0020U
#define DWC_DEVTEN_HIBER_REQ_SHIFT          5U
 
#define DWC_DEVTEN_U3_L2L1_SUSP_BIT         0x0040U
#define DWC_DEVTEN_U3_L2L1_SUSP_SHIFT       6U
 
#define DWC_DEVTEN_SOF_BIT                  0x0080U
#define DWC_DEVTEN_SOF_SHIFT                7U
 
#define DWC_DEVTEN_ERRATICERR_BIT           0x0200U
#define DWC_DEVTEN_ERRATICERR_SHIFT         9U
 
#define DWC_DEVTEN_INACT_TIMEOUT_BIT        0x2000U
#define DWC_DEVTEN_INACT_TIMEOUT_SHIFT      13U
 
#define DWC_DSTS_CONNSPD_BITS           0x00000007U
#define DWC_DSTS_CONNSPD_SHIFT          0U
 
#define DWC_DSTS_SOF_FN_BITS            0x0001fff8U
#define DWC_DSTS_SOF_FN_SHIFT           3U
 
#define DWC_DSTS_RXFIFO_EMPTY_BIT       0x00020000U
#define DWC_DSTS_RXFIFO_EMPTY_SHIFT     17U
 
#define DWC_DSTS_USBLNK_STATE_BITS      0x003c0000U
#define DWC_DSTS_USBLNK_STATE_SHIFT     18U
 
#define DWC_DSTS_DEV_CTRL_HLT_BIT       0x00400000U
#define DWC_DSTS_DEV_CTRL_HLT_SHIFT     22U
 
#define DWC_DSTS_CORE_IDLE_BIT          0x00800000U
#define DWC_DSTS_CORE_IDLE_SHIFT        23U
 
#define DWC_DSTS_SSS_BIT                0x01000000U
#define DWC_DSTS_SSS_SHIFT              24U
 
#define DWC_DSTS_RSS_BIT                0x02000000U
#define DWC_DSTS_RSS_SHIFT              25U
 
#define DWC_DSTS_SRE_BIT                0x10000000U
#define DWC_DSTS_SRE_SHIFT              28U
 
#define DWC_DSTS_LNR_BIT                0x20000000U
#define DWC_DSTS_LNR_SHIFT              29U
 
#define DWC_DGCMD_PER_PARAM_SEL_BITS            0x000003ffU
#define DWC_DGCMD_PER_PARAM_SEL_SHIFT           0U
 
#define DWC_DGCMDPAR_HOST_ROLE_REQ_BITS         0x00000003U
#define DWC_DGCMDPAR_HOST_ROLE_REQ_SHIFT        0U
 
#define DWC_DGCMDPAR_HOST_ROLE_REQ_INITIATE     1U  
#define DWC_DGCMDPAR_HOST_ROLE_REQ_CONFIRM      2U
 
#define DWC_DGCMDPAR_DEV_NOTIF_TYPE_BITS        0x0000000fU
#define DWC_DGCMDPAR_DEV_NOTIF_TYPE_SHIFT       0U
 
#define DWC_DGCMD_FUNCTION_WAKE_DEV_NOTIF       1U      
#define DWC_DGCMD_LATENCY_TOL_DEV_NOTIF         2U      
#define DWC_DGCMD_BUS_INTVL_ADJ_DEV_NOTIF       3U      
#define DWC_DGCMD_HOST_ROLE_REQ_DEV_NOTIF       4U
 
#define DWC_DGCMDPAR_DEV_NOTIF_PARAM_BITS       0xfffffff0U
#define DWC_DGCMDPAR_DEV_NOTIF_PARAM_SHIFT      4U
 
#define DWC_DGCMDPAR_BELT_VALUE_BITS            0x000003ffU
#define DWC_DGCMDPAR_BELT_VALUE_SHIFT           0U
 
#define DWC_DGCMDPAR_BELT_SCALE_BITS            0x00000c00U
#define DWC_DGCMDPAR_BELT_SCALE_SHIFT           10U
 
#define DWC_LATENCY_VALUE_MULT_1024         1U  
#define DWC_LATENCY_VALUE_MULT_32768        2U  
#define DWC_LATENCY_VALUE_MULT_1048576      3U
 
#define DWC_DGCMD_TYP_BITS          0x0ffU
#define DWC_DGCMD_TYP_SHIFT         0U
 
#define DWC_DGCMD_SET_PERIODIC_PARAMS               2U  
#define DWC_DGCMD_XMIT_FUNC_WAKE_DEV_NOTIF          3U  
#define DWC_DGCMD_SET_SCRATCHPAD_ARRAY_ADR_LO       4U  
#define DWC_DGCMD_SET_SCRATCHPAD_ARRAY_ADR_HI       5U  
#define DWC_DGCMD_XMIT_HOST_ROLE_REQUEST            6U  
#define DWC_DGCMD_XMIT_DEV_NOTIF                    7U  
#define DWC_DGCMD_SELECTED_FIFO_FLUSH               9U  
#define DWC_DGCMD_ALL_FIFO_FLUSH                    10U 
#define DWC_DGCMD_SET_EP_NRDY                       12U 
#define DWC_DGCMD_RUN_SOC_BUS_LOOPBK_TST            16U
 
#define DWC_DGCMD_IOC_BIT           0x100U
#define DWC_DGCMD_IOC_SHIFT         8U
 
#define DWC_DGCMD_ACT_BIT           0x400U
#define DWC_DGCMD_ACT_SHIFT         10U
 
#define DWC_DGCMD_STS_BITS          0xf000U
#define DWC_DGCMD_STS_SHIFT         12U
 
#define DWC_DGCMD_STS_ERROR         15U
 
#define DWC_EPMAP_RES_NUM_BITS      0x1fU
#define DWC_EPMAP_RES_NUM_SHIFT     0U
 
typedef struct dwc_usb3_dev_global_regs {
 
#define DWC_DEV_GLOBAL_REG_OFFSET   0x700U
 
    volatile u32 dcfg;
 
    volatile u32 dctl;
 
    volatile u32 devten;
 
    volatile u32 dsts;
 
    volatile u32 dgcmdpar;
 
    volatile u32 dgcmd;
 
    volatile u32 reserved[2];
 
    volatile u32 dalepena;
} dwc_usb3_dev_global_regs_t;
 
 
/****************************************************************************/
/* Device Endpoint Specific Registers */
 
#define DWC_EPCFG1_INTRNUM_BITS         0x0000003fU
#define DWC_EPCFG1_INTRNUM_SHIFT        0U
 
#define DWC_EPCFG1_XFER_CMPL_BIT        0x00000100U
#define DWC_EPCFG1_XFER_CMPL_SHIFT      8U
 
#define DWC_EPCFG1_XFER_IN_PROG_BIT     0x00000200U
#define DWC_EPCFG1_XFER_IN_PROG_SHIFT   9U
 
#define DWC_EPCFG1_XFER_NRDY_BIT        0x00000400U
#define DWC_EPCFG1_XFER_NRDY_SHIFT      10U
 
#define DWC_EPCFG1_FIFOXRUN_BIT         0x00000800U
#define DWC_EPCFG1_FIFOXRUN_SHIFT       11U
 
#define DWC_EPCFG1_SETUP_PNDG_BIT       0x00001000U
#define DWC_EPCFG1_SETUP_PNDG_SHIFT     12U
 
#define DWC_EPCFG1_EPCMD_CMPL_BIT       0x00002000U
#define DWC_EPCFG1_EPCMD_CMPL_SHIFT     13U
 
#define DWC_EPCFG1_BINTERVAL_BITS       0x00ff0000U
#define DWC_EPCFG1_BINTERVAL_SHIFT      16U
 
#define DWC_EPCFG1_STRM_CAP_BIT         0x01000000U
#define DWC_EPCFG1_STRM_CAP_SHIFT       24U
 
#define DWC_EPCFG1_EP_DIR_BIT           0x02000000U
#define DWC_EPCFG1_EP_DIR_SHIFT         25U
 
#define DWC_EPCFG1_EP_NUM_BITS          0x3c000000U
#define DWC_EPCFG1_EP_NUM_SHIFT         26
 
#define DWC_EPCFG0_EPTYPE_BITS          0x00000006U
#define DWC_EPCFG0_EPTYPE_SHIFT         1U
 
#define DWC_USB3_EP_TYPE_CONTROL    0U  
#define DWC_USB3_EP_TYPE_ISOC       1U  
#define DWC_USB3_EP_TYPE_BULK       2U  
#define DWC_USB3_EP_TYPE_INTR       3U
 
#define DWC_EPCFG0_MPS_BITS                 0x00003ff8U
#define DWC_EPCFG0_MPS_SHIFT                3U
 
#define DWC_EPCFG0_FLOW_CTRL_STATE_BIT      0x00010000U
#define DWC_EPCFG0_FLOW_CTRL_STATE_SHIFT    16U
 
#define DWC_EPCFG0_TXFNUM_BITS              0x003e0000U
#define DWC_EPCFG0_TXFNUM_SHIFT             17U
 
#define DWC_EPCFG0_BRSTSIZ_BITS             0x03c00000U
#define DWC_EPCFG0_BRSTSIZ_SHIFT            22U
 
#define DWC_EPCFG0_DSNUM_BITS               0x7c000000U
#define DWC_EPCFG0_DSNUM_SHIFT              26U
 
#define DWC_EPCFG0_IGN_DSNUM_BIT            0x80000000U
#define DWC_EPCFG0_IGN_DSNUM_SHIFT          31U
 
#define DWC_EPCFG0_CFG_ACTION_BITS          0xc0000000U
#define DWC_EPCFG0_CFG_ACTION_SHIFT         30U
 
#define DWC_CFG_ACTION_INIT         0U  
#define DWC_CFG_ACTION_RESTORE      1U  
#define DWC_CFG_ACTION_MODIFY       2U
 
#define DWC_EPCMD_TYP_BITS          0x0ffU
#define DWC_EPCMD_TYP_SHIFT         0U
 
#define DWC_EPCMD_SET_EP_CFG        1U  
#define DWC_EPCMD_SET_XFER_CFG      2U  
#define DWC_EPCMD_GET_EP_STATE      3U  
#define DWC_EPCMD_SET_STALL         4U  
#define DWC_EPCMD_CLR_STALL         5U  
#define DWC_EPCMD_START_XFER        6U  
#define DWC_EPCMD_UPDATE_XFER       7U  
#define DWC_EPCMD_END_XFER          8U  
#define DWC_EPCMD_START_NEW_CFG     9U
 
#define DWC_EPCMD_IOC_BIT                   0x100U
#define DWC_EPCMD_IOC_SHIFT                 8U
 
#define DWC_EPCMD_ACT_BIT                   0x400U
#define DWC_EPCMD_ACT_SHIFT                 10U
 
#define DWC_EPCMD_HP_FRM_BIT                0x800U
#define DWC_EPCMD_HP_FRM_SHIFT              11U
 
#define DWC_EPCMD_CMPL_STS_BITS             0xf000U
#define DWC_EPCMD_CMPL_STS_SHIFT            12U
 
#define DWC_EPCMD_STR_NUM_OR_UF_BITS        0xffff0000U
#define DWC_EPCMD_STR_NUM_OR_UF_SHIFT       16U
 
#define DWC_EPCMD_XFER_RSRC_IDX_BITS        0x007f0000U
#define DWC_EPCMD_XFER_RSRC_IDX_SHIFT       16U
 
typedef struct dwc_usb3_dev_ep_regs {
 
#define DWC_DEV_OUT_EP_REG_OFFSET   0x800U
#define DWC_DEV_IN_EP_REG_OFFSET    0x810U
#define DWC_EP_REG_OFFSET           0x20U
 
    volatile u32 depcmdpar2;
 
    volatile u32 depcmdpar1;
 
    volatile u32 depcmdpar0;
 
    volatile u32 depcmd;
 
    volatile u32 reserved[4];
} dwc_usb3_dev_ep_regs_t;
 
 
/****************************************************************************/
/* DMA Descriptor Specific Structures */
 
#define DWC_DSCSTS_XFRCNT_BITS      0x00ffffffU
#define DWC_DSCSTS_XFRCNT_SHIFT     0U
 
#define DWC_DSCSTS_PCM1_BITS        0x03000000U
#define DWC_DSCSTS_PCM1_SHIFT       24U
 
#define DWC_DSCSTS_TRBRSP_BITS      0xf0000000U
#define DWC_DSCSTS_TRBRSP_SHIFT     28U
 
#define DWC_TRBRSP_MISSED_ISOC_IN   1U  
#define DWC_TRBRSP_SETUP_PEND       2U  
#define DWC_TRBRSP_XFER_IN_PROG     4U
 
#define DWC_DSCCTL_HWO_BIT          0x00000001U
#define DWC_DSCCTL_HWO_SHIFT        0U
 
#define DWC_DSCCTL_LST_BIT          0x00000002U
#define DWC_DSCCTL_LST_SHIFT        1U
 
#define DWC_DSCCTL_CHN_BIT          0x00000004U
#define DWC_DSCCTL_CHN_SHIFT        2U
 
#define DWC_DSCCTL_CSP_BIT          0x00000008U
#define DWC_DSCCTL_CSP_SHIFT        3U
 
#define DWC_DSCCTL_TRBCTL_BITS      0x000003f0U
#define DWC_DSCCTL_TRBCTL_SHIFT     4U
 
#define DWC_DSCCTL_TRBCTL_NORMAL        1   
#define DWC_DSCCTL_TRBCTL_SETUP         2   
#define DWC_DSCCTL_TRBCTL_STATUS_2      3   
#define DWC_DSCCTL_TRBCTL_STATUS_3      4   
#define DWC_DSCCTL_TRBCTL_CTLDATA_1ST   5   
#define DWC_DSCCTL_TRBCTL_ISOC_1ST      6   
#define DWC_DSCCTL_TRBCTL_ISOC          7   
#define DWC_DSCCTL_TRBCTL_LINK          8
 
#define DWC_DSCCTL_ISP_BIT              0x00000400U
#define DWC_DSCCTL_ISP_SHIFT            10U
#define DWC_DSCCTL_IMI_BIT              DWC_DSCCTL_ISP_BIT
#define DWC_DSCCTL_IMI_SHIFT            DWC_DSCCTL_ISP_SHIFT
 
#define DWC_DSCCTL_IOC_BIT              0x00000800U
#define DWC_DSCCTL_IOC_SHIFT            11U
 
#define DWC_DSCCTL_STRMID_SOFN_BITS     0x3fffc000U
#define DWC_DSCCTL_STRMID_SOFN_SHIFT    14U
 
typedef struct dwc_usb3_dma_desc {
    u32 bptl;
 
    u32 bpth;
 
    u32 status;
 
    u32 control;
} dwc_usb3_dma_desc_t;
 
#ifdef SSIC
 
/* SSIC Registers */
typedef struct dwc_usb3_ssic_regs {
 
#define DWC_SSIC_REG_OFFSET 0xc40
 
    volatile u32 sctl[16];
    volatile u32 sevt[16];
    volatile u32 sevten[16];
    volatile u32 gscfg;
    volatile u32 gsser;
    volatile u32 gsdbg;
} dwc_usb3_ssic_regs_t;
 
#define DWC_SEVTEN_ROM_INIT_CMPLT_EN_BIT    0x00000001U
#define DWC_SEVTEN_ROM_INIT_CMPLT_EN_SHIFT  0U
 
#define DWC_SEVTEN_LACC_CMPLT_EN_BIT        0x00000002U
#define DWC_SEVTEN_LACC_CMPLT_EN_SHIFT      1U
 
#define DWC_SEVTEN_RCMD_RES_RCVD_EN_BIT     0x00000004U
#define DWC_SEVTEN_RCMD_RES_RCVD_EN_SHIFT   2U
 
#define DWC_SEVTEN_RCMD_RES_SENT_EN_BIT     0x00000008U
#define DWC_SEVTEN_RCMD_RES_SENT_EN_SHIFT   3U
 
#define DWC_SEVTEN_MPHY_ST_CHNGD_EN_BIT     0x00000010U
#define DWC_SEVTEN_MPHY_ST_CHNGD_EN_SHIFT   4U
 
#define DWC_SEVTEN_OK_STRT_RRAP_EN_BIT      0x00000020U
#define DWC_SEVTEN_OK_STRT_RRAP_EN_SHIFT    5U
 
#define DWC_SEVTEN_RRAP_ERROR_EN_BIT        0x00000040U
#define DWC_SEVTEN_RRAP_ERROR_EN_SHIFT      6U
 
#define DWC_SEVT_ROM_INIT_CMPLT_BIT         0x00000001U
#define DWC_SEVT_ROM_INIT_CMPLT_SHIFT       0U
 
#define DWC_SEVT_LACC_CMPLT_BIT             0x00000002U
#define DWC_SEVT_LACC_CMPLT_SHIFT           1U
 
#define DWC_SEVT_RCMD_RES_RCVD_BIT          0x00000004U
#define DWC_SEVT_RCMD_RES_RCVD_SHIFT        2U
 
#define DWC_SEVT_RCMD_RES_SENT_BIT          0x00000008U
#define DWC_SEVT_RCMD_RES_SENT_SHIFT        3U
 
#define DWC_SEVT_MPHY_ST_CHNG_BIT           0x00000010U
#define DWC_SEVT_MPHY_ST_CHNG_SHIFT         4U
 
#define DWC_SEVT_OK_STRT_RRAP_BIT           0x00000020U
#define DWC_SEVT_OK_STRT_RRAP_SHIFT         5U
 
#define DWC_SEVT_RRAP_ERROR_BIT             0x00000040U
#define DWC_SEVT_RRAP_ERROR_SHIFT           6U
 
#define DWC_SEVT_RACC_RESULT_BITS           0x00000300U
#define DWC_SEVT_RACC_RESULT_SHIFT          8U
 
#define DWC_SEVT_LACC_RESULT_BIT            0x00000400U
#define DWC_SEVT_LACC_RESULT_SHIFT          10U
 
#define DWC_SEVT_READ_RCVD_BIT              0x00000800U
#define DWC_SEVT_READ_RCVD_SHIFT            11U
 
#define DWC_SEVT_RUADDR_RCVD_BITS           0x0000f000U
#define DWC_SEVT_RUADDR_RCVD_SHIFT          12U
 
#define DWC_SEVT_RLADDR_RCVD_BITS           0x00ff0000U
#define DWC_SEVT_RLADDR_RCVD_SHIFT          16U
 
#define DWC_SEVT_RDATA_RCVD_BITS            0xff000000U
#define DWC_SEVT_RDATA_RCVD_SHIFT           24U
 
#define DWC_SCTL_GO_ACC_BIT                 0x00000001U
#define DWC_SCTL_GO_ACC_SHIFT               0U
 
#define DWC_SCTL_RACC_BIT                   0x00000002U
#define DWC_SCTL_RACC_SHIFT                 1U
 
#define DWC_SCTL_RD_WR_N_BIT                0x00000004U
#define DWC_SCTL_RD_WR_N_SHIFT              2U
 
#define DWC_SCTL_BCW_BIT                    0x00000008U
#define DWC_SCTL_BCW_SHIFT                  3U
 
#define DWC_SCTL_IN_LN_CFG_BIT              0x00000010U
#define DWC_SCTL_IN_LN_CFG_SHIFT            4U
 
#define DWC_SCTL_CFG_DONE_BIT               0x00000020U
#define DWC_SCTL_CFG_DEON_SHIFT             5U
 
#define DWC_SCTL_CBS_ACC_BIT                0x00000040U
#define DWC_SCTL_CBS_ACC_SHIFT              6U
 
#define DWC_SCTL_RXS_ACC_BIT                0x00000080U
#define DWC_SCTL_RXS_ACC_SHIFT              7U
 
#define DWC_SCTL_EAID_BITS                  0x0000f000U
#define DWC_SCTL_EAID_SHIFT                 12U
 
#define DWC_SCTL_AID_BITS                   0x00ff0000U
#define DWC_SCTL_AID_SHIFT                  16U
 
#define DWC_SCTL_ADATA_BITS                 0xff000000U
#define DWC_SCTL_ADATA_SHIFT                24U
 
#endif /* SSIC */
 
#ifdef __cplusplus
}
#endif
 
#endif /* _DWC_USB3_REGS_H_ */