AM243x MCU+ SDK  08.04.00
hdsl_drv.h
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31  */
32 
33 #ifndef HDSL_DRV_H_
34 #define HDSL_DRV_H_
35 
44 #ifdef __cplusplus
45 extern "C" {
46 #endif
47 
48 #include <stdio.h>
49 #include <string.h>
50 #include <math.h>
51 
53 #include <stdlib.h>
54 
55 #include <stdbool.h>
56 
57 #include <kernel/dpl/DebugP.h>
58 
59 #include <drivers/pruicss.h>
60 #include <drivers/hw_include/cslr_soc.h>
61 #include "hdsl_interface.h"
62 #include <drivers/hw_include/hw_types.h>
63 
64 
65 #define MAX_WAIT 20000
66 #define HWREG(x) \
67  (*((volatile uint32_t *)(x)))
68 #define HWREGB(x) \
69  (*((volatile uint8_t *)(x)))
70 #define HWREGH(x) \
71  (*((volatile uint16_t *)(x)))
72 /*TSR configuration:*/
73 
74 /*inEvent value:*/
75 /* ICSSG_0_EDC1_SYNC0 ICSSG0 IEP1 sync event 0 Pulse */
76 #define SYNCEVENT_INTRTR_IN_27 27
77 
78 /*outEvent values:*/
79 /*SYNC0_OUT Pin Selectable timesync event 24 Edge (4+(24*4)) */
80 #define SYNCEVT_RTR_SYNC28_EVT 0x64
81 /* SYNC1_OUT Pin Selectable timesync event 25 Edge (4+(25*4)) */
82 #define SYNCEVT_RTR_SYNC29_EVT 0x68
83 /* SYNC2_OUT Pin Selectable timesync event 26 Edge (4+(26*4)) */
84 #define SYNCEVT_RTR_SYNC30_EVT 0x6C
85 /* SYNC3_OUT Pin Selectable timesync event 27 Edge (4+(27*4)) */
86 #define SYNCEVT_RTR_SYNC31_EVT 0x70
87 /* ICSSG0_PR1_EDC1_LATCH0_IN PRU_ICSSG0 (4+(10*4)) */
88 #define SYNCEVT_RTR_SYNC10_EVT 0x2C
89 
90 
91 enum {
111 };
112 
122 void HDSL_iep_init(PRUICSS_Handle gPruIcss0Handle, void *gPru_cfg,void *gPru_dramx);
123 
124 
137 int HDSL_enable_sync_signal(uint8_t ES,uint32_t period);
138 
146 uint64_t HDSL_get_pos(int position_id);
147 
148 
155 uint8_t HDSL_get_qm();
156 
165 uint16_t HDSL_get_events();
166 
175 uint8_t HDSL_get_sum();
176 
194 uint8_t HDSL_get_rssi();
204 int HDSL_write_pc_short_msg(uint32_t gPc_addr,uint32_t gPc_data);
205 
214 uint32_t HDSL_read_pc_short_msg(uint32_t gPc_addr);
215 
226 void HDSL_set_pc_addr(uint8_t gPc_addrh,uint8_t gPc_addrl,uint8_t gPc_offh,uint8_t gPc_offl);
227 
228 
235 void HDSL_set_pc_ctrl(uint8_t value);
236 
250 void HDSL_write_pc_buffer(uint8_t gPc_buf0,uint8_t gPc_buf1,uint8_t gPc_buf2,uint8_t gPc_buf3,uint8_t gPc_buf4,uint8_t gPc_buf5,uint8_t gPc_buf6,uint8_t gPc_buf7);
251 
259 uint8_t HDSL_read_pc_buffer(uint8_t buff_off);
260 
269 
277 void HDSL_set_sync_ctrl(uint8_t val );
278 
288 
296 uint8_t HDSL_get_edges();
304 uint8_t HDSL_get_delay();
312 uint8_t HDSL_get_enc_id(int byte);
313 
315 
317 
318 uint32_t HDSL_get_length();
319 
320 
321 
322 #ifdef __cplusplus
323 }
324 #endif
325 
327 #endif
HDSL_get_events
uint16_t HDSL_get_events()
taking values of High bytes event(EVENT_H),Low bytes event(EVENT_L)
HDSL_get_edges
uint8_t HDSL_get_edges()
read Cable bit sampling time control
HDSL_write_pc_buffer
void HDSL_write_pc_buffer(uint8_t gPc_buf0, uint8_t gPc_buf1, uint8_t gPc_buf2, uint8_t gPc_buf3, uint8_t gPc_buf4, uint8_t gPc_buf5, uint8_t gPc_buf6, uint8_t gPc_buf7)
Write Parameters channel buffer for different bytes(bytes 0-7)
HDSL_generate_memory_image
void HDSL_generate_memory_image(void)
MENU_SAFE_POSITION
@ MENU_SAFE_POSITION
Definition: hdsl_drv.h:92
HDSL_get_qm
uint8_t HDSL_get_qm()
Taking quality monitoring value.
MENU_HDSL_REG_INTO_DDR_GPIO
@ MENU_HDSL_REG_INTO_DDR_GPIO
Definition: hdsl_drv.h:102
HDSL_get_acc_err_cnt
uint8_t HDSL_get_acc_err_cnt()
Acceleration error counter.
MENU_DIRECT_READ_RID81_LENGTH8
@ MENU_DIRECT_READ_RID81_LENGTH8
Definition: hdsl_drv.h:104
HDSL_enable_sync_signal
int HDSL_enable_sync_signal(uint8_t ES, uint32_t period)
Enable IEP *Enable SYNC0 and program pulse width Enable cyclic mod Program CMP1 TSR configura...
HDSL_get_delay
uint8_t HDSL_get_delay()
read Run time delay of system cable and signal strength
HDSL_get_length
uint32_t HDSL_get_length()
MENU_PC_SHORT_MSG_WRITE
@ MENU_PC_SHORT_MSG_WRITE
Definition: hdsl_drv.h:98
HDSL_get_sum
uint8_t HDSL_get_sum()
Getting Summarized slave status.
hdsl_interface.h
pruicss.h
HDSL_read_pc_short_msg
uint32_t HDSL_read_pc_short_msg(uint32_t gPc_addr)
Read Response of Short message parameters channel Read for safe1 channel(S_PC_DATA) and write Short m...
HDSL_write_pc_short_msg
int HDSL_write_pc_short_msg(uint32_t gPc_addr, uint32_t gPc_data)
Write Response of Short message parameters channel Read for safe1 channel(S_PC_DATA) with gPc_data an...
MENU_HDSL_REG_INTO_DDR
@ MENU_HDSL_REG_INTO_DDR
Definition: hdsl_drv.h:101
MENU_PC_LONG_MSG_WRITE
@ MENU_PC_LONG_MSG_WRITE
Definition: hdsl_drv.h:100
MENU_DIRECT_READ_RID0_LENGTH8
@ MENU_DIRECT_READ_RID0_LENGTH8
Definition: hdsl_drv.h:103
MENU_EVENTS
@ MENU_EVENTS
Definition: hdsl_drv.h:94
HDSL_get_sync_ctrl
uint8_t HDSL_get_sync_ctrl()
read Synchronization control value
MENU_INVALID
@ MENU_INVALID
Definition: hdsl_drv.h:110
value
uint32_t value
Definition: tisci_otp_revision.h:2
MENU_INDIRECT_WRITE_RID0_LENGTH8
@ MENU_INDIRECT_WRITE_RID0_LENGTH8
Definition: hdsl_drv.h:107
HDSL_get_src_loc
void * HDSL_get_src_loc()
MENU_INDIRECT_WRITE_RID0_LENGTH8_OFFSET0
@ MENU_INDIRECT_WRITE_RID0_LENGTH8_OFFSET0
Definition: hdsl_drv.h:106
MENU_DIRECT_READ_RID0_LENGTH8_OFFSET6
@ MENU_DIRECT_READ_RID0_LENGTH8_OFFSET6
Definition: hdsl_drv.h:108
HDSL_set_pc_ctrl
void HDSL_set_pc_ctrl(uint8_t value)
To set the direction read/write for long message communication.
HDSL_get_rssi
uint8_t HDSL_get_rssi()
Read RSSI value.
HDSL_get_master_qm
uint8_t HDSL_get_master_qm()
read Quality monitoring value
DebugP.h
HDSL_get_enc_id
uint8_t HDSL_get_enc_id(int byte)
Read encoder id bytes(byte no. 0-2)
HDSL_set_sync_ctrl
void HDSL_set_sync_ctrl(uint8_t val)
write Synchronization control value
HDSL_get_pos
uint64_t HDSL_get_pos(int position_id)
Calculate fast position,safe position1,safe position2.
HDSL_set_pc_addr
void HDSL_set_pc_addr(uint8_t gPc_addrh, uint8_t gPc_addrl, uint8_t gPc_offh, uint8_t gPc_offl)
Write PC_AAD_L ,PC_ADD_H ,PC_OFF_L,PC_OFF_H and PC_CTRL values in hdsl interface.
MENU_SUMMARY
@ MENU_SUMMARY
Definition: hdsl_drv.h:95
MENU_LIMIT
@ MENU_LIMIT
Definition: hdsl_drv.h:109
MENU_DIRECT_READ_RID81_LENGTH2
@ MENU_DIRECT_READ_RID81_LENGTH2
Definition: hdsl_drv.h:105
MENU_RSSI
@ MENU_RSSI
Definition: hdsl_drv.h:97
pruicss.h
MENU_QUALITY_MONITORING
@ MENU_QUALITY_MONITORING
Definition: hdsl_drv.h:93
MENU_ACC_ERR_CNT
@ MENU_ACC_ERR_CNT
Definition: hdsl_drv.h:96
HDSL_read_pc_buffer
uint8_t HDSL_read_pc_buffer(uint8_t buff_off)
read Parameters channel buffer for different bytes(bytes 0-7)
PRUICSS_Handle
struct PRUICSS_Config_s * PRUICSS_Handle
A handle that is returned from a PRUICSS_open() call. This handle is required for calling other APIs.
Definition: pruicss/g_v0/pruicss.h:235
MENU_PC_SHORT_MSG_READ
@ MENU_PC_SHORT_MSG_READ
Definition: hdsl_drv.h:99
HDSL_iep_init
void HDSL_iep_init(PRUICSS_Handle gPruIcss0Handle, void *gPru_cfg, void *gPru_dramx)
Initialize IEP and Use OCP as IEP CLK src.