AM243x MCU+ SDK  08.04.00
APIs for HDSL Encoder

Introduction

Here is the list of APIs used for EnDAT encoder communication protocol

Functions

void HDSL_iep_init (PRUICSS_Handle gPruIcss0Handle, void *gPru_cfg, void *gPru_dramx)
 Initialize IEP and Use OCP as IEP CLK src. More...
 
int HDSL_enable_sync_signal (uint8_t ES, uint32_t period)
 Enable IEP
*Enable SYNC0 and program pulse width
Enable cyclic mod
Program CMP1
TSR configuration
More...
 
uint64_t HDSL_get_pos (int position_id)
 Calculate fast position,safe position1,safe position2. More...
 
uint8_t HDSL_get_qm ()
 Taking quality monitoring value. More...
 
uint16_t HDSL_get_events ()
 taking values of High bytes event(EVENT_H),Low bytes event(EVENT_L) More...
 
uint8_t HDSL_get_sum ()
 Getting Summarized slave status. More...
 
uint8_t HDSL_get_acc_err_cnt ()
 Acceleration error counter. More...
 
uint8_t HDSL_get_rssi ()
 Read RSSI value. More...
 
int HDSL_write_pc_short_msg (uint32_t gPc_addr, uint32_t gPc_data)
 Write Response of Short message parameters channel Read for safe1 channel(S_PC_DATA) with gPc_data and Short message control value(SLAVE_REG_CTRL) in hdsl interface. More...
 
uint32_t HDSL_read_pc_short_msg (uint32_t gPc_addr)
 Read Response of Short message parameters channel Read for safe1 channel(S_PC_DATA) and write Short message control value(SLAVE_REG_CTRL) with gPc_addr in hdsl interface. More...
 
void HDSL_set_pc_addr (uint8_t gPc_addrh, uint8_t gPc_addrl, uint8_t gPc_offh, uint8_t gPc_offl)
 Write PC_AAD_L ,PC_ADD_H ,PC_OFF_L,PC_OFF_H and PC_CTRL values in hdsl interface. More...
 
void HDSL_set_pc_ctrl (uint8_t value)
 To set the direction read/write for long message communication. More...
 
void HDSL_write_pc_buffer (uint8_t gPc_buf0, uint8_t gPc_buf1, uint8_t gPc_buf2, uint8_t gPc_buf3, uint8_t gPc_buf4, uint8_t gPc_buf5, uint8_t gPc_buf6, uint8_t gPc_buf7)
 Write Parameters channel buffer for different bytes(bytes 0-7) More...
 
uint8_t HDSL_read_pc_buffer (uint8_t buff_off)
 read Parameters channel buffer for different bytes(bytes 0-7) More...
 
uint8_t HDSL_get_sync_ctrl ()
 read Synchronization control value More...
 
void HDSL_set_sync_ctrl (uint8_t val)
 write Synchronization control value More...
 
uint8_t HDSL_get_master_qm ()
 read Quality monitoring value More...
 
uint8_t HDSL_get_edges ()
 read Cable bit sampling time control More...
 
uint8_t HDSL_get_delay ()
 read Run time delay of system cable and signal strength More...
 
uint8_t HDSL_get_enc_id (int byte)
 Read encoder id bytes(byte no. 0-2) More...
 
void HDSL_generate_memory_image (void)
 
void * HDSL_get_src_loc ()
 
uint32_t HDSL_get_length ()
 

Enumerations

enum  {
  linear, rotary, MENU_SAFE_POSITION, MENU_QUALITY_MONITORING,
  MENU_EVENTS, MENU_SUMMARY, MENU_ACC_ERR_CNT, MENU_RSSI,
  MENU_PC_SHORT_MSG_WRITE, MENU_PC_SHORT_MSG_READ, MENU_PC_LONG_MSG_WRITE, MENU_HDSL_REG_INTO_DDR,
  MENU_HDSL_REG_INTO_DDR_GPIO, MENU_DIRECT_READ_RID0_LENGTH8, MENU_DIRECT_READ_RID81_LENGTH8, MENU_DIRECT_READ_RID81_LENGTH2,
  MENU_INDIRECT_WRITE_RID0_LENGTH8_OFFSET0, MENU_INDIRECT_WRITE_RID0_LENGTH8, MENU_DIRECT_READ_RID0_LENGTH8_OFFSET6, MENU_LIMIT,
  MENU_INVALID
}
 

Macros

#define MAX_WAIT   20000
 
#define HWREG(x)    (*((volatile uint32_t *)(x)))
 
#define HWREGB(x)    (*((volatile uint8_t *)(x)))
 
#define HWREGH(x)    (*((volatile uint16_t *)(x)))
 
#define SYNCEVENT_INTRTR_IN_27   27
 
#define SYNCEVT_RTR_SYNC28_EVT   0x64
 
#define SYNCEVT_RTR_SYNC29_EVT   0x68
 
#define SYNCEVT_RTR_SYNC30_EVT   0x6C
 
#define SYNCEVT_RTR_SYNC31_EVT   0x70
 
#define SYNCEVT_RTR_SYNC10_EVT   0x2C
 

Macro Definition Documentation

◆ MAX_WAIT

#define MAX_WAIT   20000

◆ HWREG

#define HWREG (   x)     (*((volatile uint32_t *)(x)))

◆ HWREGB

#define HWREGB (   x)     (*((volatile uint8_t *)(x)))

◆ HWREGH

#define HWREGH (   x)     (*((volatile uint16_t *)(x)))

◆ SYNCEVENT_INTRTR_IN_27

#define SYNCEVENT_INTRTR_IN_27   27

◆ SYNCEVT_RTR_SYNC28_EVT

#define SYNCEVT_RTR_SYNC28_EVT   0x64

◆ SYNCEVT_RTR_SYNC29_EVT

#define SYNCEVT_RTR_SYNC29_EVT   0x68

◆ SYNCEVT_RTR_SYNC30_EVT

#define SYNCEVT_RTR_SYNC30_EVT   0x6C

◆ SYNCEVT_RTR_SYNC31_EVT

#define SYNCEVT_RTR_SYNC31_EVT   0x70

◆ SYNCEVT_RTR_SYNC10_EVT

#define SYNCEVT_RTR_SYNC10_EVT   0x2C

Enumeration Type Documentation

◆ anonymous enum

anonymous enum
Enumerator
linear 
rotary 
MENU_SAFE_POSITION 
MENU_QUALITY_MONITORING 
MENU_EVENTS 
MENU_SUMMARY 
MENU_ACC_ERR_CNT 
MENU_RSSI 
MENU_PC_SHORT_MSG_WRITE 
MENU_PC_SHORT_MSG_READ 
MENU_PC_LONG_MSG_WRITE 
MENU_HDSL_REG_INTO_DDR 
MENU_HDSL_REG_INTO_DDR_GPIO 
MENU_DIRECT_READ_RID0_LENGTH8 
MENU_DIRECT_READ_RID81_LENGTH8 
MENU_DIRECT_READ_RID81_LENGTH2 
MENU_INDIRECT_WRITE_RID0_LENGTH8_OFFSET0 
MENU_INDIRECT_WRITE_RID0_LENGTH8 
MENU_DIRECT_READ_RID0_LENGTH8_OFFSET6 
MENU_LIMIT 
MENU_INVALID 

Function Documentation

◆ HDSL_iep_init()

void HDSL_iep_init ( PRUICSS_Handle  gPruIcss0Handle,
void *  gPru_cfg,
void *  gPru_dramx 
)

Initialize IEP and Use OCP as IEP CLK src.

Parameters
[in]gPruIcss0Handle
[in]gPru_cfg
[in]gPru_dramx

◆ HDSL_enable_sync_signal()

int HDSL_enable_sync_signal ( uint8_t  ES,
uint32_t  period 
)

Enable IEP
*Enable SYNC0 and program pulse width
Enable cyclic mod
Program CMP1
TSR configuration

Parameters
[in]ES
[in]period
Return values
1for successful enable sync signal

◆ HDSL_get_pos()

uint64_t HDSL_get_pos ( int  position_id)

Calculate fast position,safe position1,safe position2.

Parameters
[in]position_id
Return values
positionvalue in integer for successful position return, -1 for error in position return

◆ HDSL_get_qm()

uint8_t HDSL_get_qm ( )

Taking quality monitoring value.

Parameters
[in]None
Return values
8bit integer QM value

◆ HDSL_get_events()

uint16_t HDSL_get_events ( )

taking values of High bytes event(EVENT_H),Low bytes event(EVENT_L)

Parameters
[in]None
Return values
16bit integer concatenated values of both EVENT_H,EVENT_L

◆ HDSL_get_sum()

uint8_t HDSL_get_sum ( )

Getting Summarized slave status.

Parameters
[in]None
Return values
8bit integer value of summarized status

◆ HDSL_get_acc_err_cnt()

uint8_t HDSL_get_acc_err_cnt ( )

Acceleration error counter.

Parameters
[in]None
Return values
8bit integer value of acceleration error counter

◆ HDSL_get_rssi()

uint8_t HDSL_get_rssi ( )

Read RSSI value.

Parameters
[in]None
Return values
8bit RSSI integer value

◆ HDSL_write_pc_short_msg()

int HDSL_write_pc_short_msg ( uint32_t  gPc_addr,
uint32_t  gPc_data 
)

Write Response of Short message parameters channel Read for safe1 channel(S_PC_DATA) with gPc_data and Short message control value(SLAVE_REG_CTRL) in hdsl interface.

Parameters
[in]gPc_addr
[in]gPc_data
Return values
1for successfully write of pc short messege in hdsl interface

◆ HDSL_read_pc_short_msg()

uint32_t HDSL_read_pc_short_msg ( uint32_t  gPc_addr)

Read Response of Short message parameters channel Read for safe1 channel(S_PC_DATA) and write Short message control value(SLAVE_REG_CTRL) with gPc_addr in hdsl interface.

Parameters
[in]gPc_addr
Return values
S_PC_DATAfrom hdsl interface

◆ HDSL_set_pc_addr()

void HDSL_set_pc_addr ( uint8_t  gPc_addrh,
uint8_t  gPc_addrl,
uint8_t  gPc_offh,
uint8_t  gPc_offl 
)

Write PC_AAD_L ,PC_ADD_H ,PC_OFF_L,PC_OFF_H and PC_CTRL values in hdsl interface.

Parameters
[in]gPc_addrh
[in]gPc_addrl
[in]gPc_offh
[in]gPc_offl

◆ HDSL_set_pc_ctrl()

void HDSL_set_pc_ctrl ( uint8_t  value)

To set the direction read/write for long message communication.

Parameters
[in]value

◆ HDSL_write_pc_buffer()

void HDSL_write_pc_buffer ( uint8_t  gPc_buf0,
uint8_t  gPc_buf1,
uint8_t  gPc_buf2,
uint8_t  gPc_buf3,
uint8_t  gPc_buf4,
uint8_t  gPc_buf5,
uint8_t  gPc_buf6,
uint8_t  gPc_buf7 
)

Write Parameters channel buffer for different bytes(bytes 0-7)

Parameters
[in]gPc_buf0
[in]gPc_buf1
[in]gPc_buf2
[in]gPc_buf3
[in]gPc_buf4
[in]gPc_buf5
[in]gPc_buf6
[in]gPc_buf7

◆ HDSL_read_pc_buffer()

uint8_t HDSL_read_pc_buffer ( uint8_t  buff_off)

read Parameters channel buffer for different bytes(bytes 0-7)

Parameters
[in]buff_off
Return values
8bit integer value of PC_BUFFER from hdsl interface

◆ HDSL_get_sync_ctrl()

uint8_t HDSL_get_sync_ctrl ( )

read Synchronization control value

Return values
8bit integer value of SYNC_CTRL from hdsl interface

◆ HDSL_set_sync_ctrl()

void HDSL_set_sync_ctrl ( uint8_t  val)

write Synchronization control value

Parameters
[in]val

◆ HDSL_get_master_qm()

uint8_t HDSL_get_master_qm ( )

read Quality monitoring value

Parameters
[in]None
Return values
8bit integer value of MASTER_QM from hdsl interface

◆ HDSL_get_edges()

uint8_t HDSL_get_edges ( )

read Cable bit sampling time control

Parameters
[in]None
Return values
8bit integer value of EDGES from hdsl interface

◆ HDSL_get_delay()

uint8_t HDSL_get_delay ( )

read Run time delay of system cable and signal strength

Parameters
[in]buff
Return values
8bit integer value of DELAY from hdsl interface

◆ HDSL_get_enc_id()

uint8_t HDSL_get_enc_id ( int  byte)

Read encoder id bytes(byte no. 0-2)

Parameters
[in]byte
Return values
8bit encoder bytes data from hdsl interface

◆ HDSL_generate_memory_image()

void HDSL_generate_memory_image ( void  )

◆ HDSL_get_src_loc()

void* HDSL_get_src_loc ( )

◆ HDSL_get_length()

uint32_t HDSL_get_length ( )