4.18. SPI¶

4.18.1. Introduction¶

SPI driver enables communication for general SPI, MCSPI (Multichannel SPI) on board through common API to application. MCSPI is a generic full-duplex interface supporting transmit and receive of data over SPI bus.

4.18.1.1. Modes of Operation¶

Following modes of operations are supported:

SPI_MODE_BLOCKING SPI_transfer() API blocks code execution until transaction has completed. By default, SPI driver operates in blocking mode. This ensures only one SPI transaction operates at a given time. This mode is supported in both interrupt or non-interrupt configurations.

SPI_MODE_CALLBACK SPI_transfer() API returns without waiting for completion of transaction in this case. Callback function registered by application is invoked once transaction is complete.This mode is supported only in interrupt configuration.

4.18.2. Driver Configuration¶

4.18.2.1. Board Specific Configuration¶

All board specific configurations eg:enabling clock and pin-mux for SPI pins are required before calling any driver APIs.By default Board_Init() API supports all initialization sequence for TI supported EVMs. In addition it initializes UART instance for Console/STDIO.Refer PDK Board Support for additional details.Once board specific configuration is complete SPI_init() API should be called to initialize driver.

4.18.2.2. SoC Specific Configuration¶

All SoC specific configurations (eg: SPI module registers base address, interrupt configurations, etc.) can be set using SPI_socSetInitCfg() SoC driver API before calling any SPI driver APIs. The default SoC specific configurations can be retrieved using SPI_socGetInitCfg() SoC driver API.

4.18.2.3. SPI Configuration Structure¶

The SPI_soc.c file binds driver with hardware attributes on the board through SPI_config[] structure. This structure must be provided to the SPI driver. It must be initialized before the SPI_init() function is called and cannot be changed afterwards.

Driver requires common SPI_config[] to configure hardware attributes of MCSPI peripherals on SOC and board. Application will need to include appropriate offset to instance while invoking SPI_open() API..

For details about individual fields of this library structure, see the PDK doxygen documentation

4.18.3. APIs¶

API Reference for application:

#include <ti/drv/spi/SPI.h>

SPI IP V1 driver also supports multi-channel API’s:

#include <ti/drv/spi/MCSPI.h>

Description

4.18.3.1. Open SPI¶

...
Board_init(boardCfg);
...
SPI_socGetInitCfg(SPI_MCSPI_DOMAIN_MCU, peripheralNum, &spi_cfg);
...
SPI_socSetInitCfg(SPI_MCSPI_DOMAIN_MCU, peripheralNum, &spi_cfg);
SPI_Params_init(&spiParams);
spiParams.transferMode = SPI_MODE_BLOCKING;
spiParams.transferCallbackFxn = NULL;
handle = SPI_open(SPI_MCSPI_DOMAIN_MCU, peripheralNum, &spiParams);

SPI IP V1 driver also supports multi-channel open API’s:

...
Board_init(boardCfg);
...
MCSPI_Params_init(&spiParams);
spiParams.transferMode = SPI_MODE_BLOCKING;
spiParams.transferCallbackFxn = NULL;
handle = MCSPI_open(SPI_MCSPI_DOMAIN_MCU, peripheralNum, channel, &spiParams);

At this point SPI driver is ready for data transfer in blocking mode on specific instance identified by handle. Pseudo/Sample code for SPI read/write transaction is included below. Refer example for additional details

...
spiTransaction.count = n;    /* Transfer Length */
spiTransaction. txBuf = transmitBuffer; /* Buffer to be written */
spiTransaction.rxBuf = NULL;  /* Buffer holding the received data */
transferOK = SPI_transfer(spi, &spiTransaction); /* Perform SPI transfer */
if (!transferOK) {
/* SPI transaction failed */
}

SPI IP V1 driver also supports multi-channel transfer API’s:

...
spiTransaction.count = n;    /* Transfer Length */
spiTransaction. txBuf = transmitBuffer; /* Buffer to be written */
spiTransaction.rxBuf = NULL;  /* Buffer holding the received data */
transferOK = MCSPI_transfer(spi, &spiTransaction); /* Perform SPI transfer */
if (!transferOK) {
/* SPI transaction failed */
}

Note

SPI_open API supports configuration of data word length in the SPI_Params. Currently IP V1 driver supports 8/16/32-bit word length. 8/16-bit word length.

4.18.4. Examples¶

4.18.4.1. MCSPI¶

Name

Description

Additional EVM Configuration

Expected Results

SoC Supported

Build Type

MCSPI_slavemode example application

Application demonstrates slave recieve and transmit features of McSPI. Application use case requires two cores. One acts as Master and Another as slave. connections information and addtional details are as follows.

Note: Run the slave mode test and then master mode test for proper execution of the test.

Core usage:

J721E EVM:
MCU2_0 (master) ====== MCU2_1(slave)

J7200 EVM:
MCU2_0 (master) ====== MCU2_1(slave)

J721S2 EVM:
MCU2_0 (master) ====== MCU2_1(slave)

J784S4 EVM:
MCU2_0 (master) ====== MCU2_1(slave)

On slave Core console: Starting SPI Slave test.

All tests have passed.

On Master Core console: Starting SPI Master test

All tests have passed.

j721e
j7200
j721s2
j784s4

makefile