 |
TIOVX User Guide
|
|
TIOVX User Guide
|
TI Targets (for vxSetNodeTarget)
The following list of defines are the list of targets supported for the call to vxSetNodeTarget
Defines | |
| #define | TIVX_TARGET_A72_0 "A72-0" |
| Target name for A72_0. | |
| #define | TIVX_TARGET_A72_1 "A72-1" |
| Target name for A72_1. | |
| #define | TIVX_TARGET_A72_2 "A72-2" |
| Target name for A72_2. | |
| #define | TIVX_TARGET_A72_3 "A72-3" |
| Target name for A72_3. | |
| #define | TIVX_TARGET_DSP_C7_1 "DSP_C7-1" |
| Target name for DSP_C7_1 This target task is first in priority. Each of the C7X targets are assigned a different task priority. Subsequent C7X targets are assigned lower priority than the preceding target (i.e., TIVX_TARGET_DSP_C7_1_PRI_2 is lower priority than TIVX_TARGET_DSP_C7_1_PRI_1). Therefore, the TIVX_TARGET_DSP_C7_1_PRI_2 target will be preempted by TIVX_TARGET_DSP_C7_1_PRI_1 once the higher priority target is unblocked to execute. | |
| #define | TIVX_TARGET_DSP_C7_1_PRI_1 TIVX_TARGET_DSP_C7_1 |
| Target name for DSP_C7_1 This target task is first in priority. This aliases to the same task as TIVX_TARGET_DSP_C7_1. | |
| #define | TIVX_TARGET_DSP_C7_1_PRI_2 "DSP_C7-1_PRI_2" |
| Target name for DSP_C7-1_PRI_2 This target task is second in priority. | |
| #define | TIVX_TARGET_DSP_C7_1_PRI_3 "DSP_C7-1_PRI_3" |
| Target name for DSP_C7-1_PRI_3 This target task is third in priority. | |
| #define | TIVX_TARGET_DSP_C7_1_PRI_4 "DSP_C7-1_PRI_4" |
| Target name for DSP_C7-1_PRI_4 This target task is fourth in priority. | |
| #define | TIVX_TARGET_DSP_C7_1_PRI_5 "DSP_C7-1_PRI_5" |
| Target name for DSP_C7-1_PRI_5 This target task is fifth in priority. | |
| #define | TIVX_TARGET_DSP_C7_1_PRI_6 "DSP_C7-1_PRI_6" |
| Target name for DSP_C7-1_PRI_6 This target task is sixth in priority. | |
| #define | TIVX_TARGET_DSP_C7_1_PRI_7 "DSP_C7-1_PRI_7" |
| Target name for DSP_C7-1_PRI_7 This target task is seventh in priority. | |
| #define | TIVX_TARGET_DSP_C7_1_PRI_8 "DSP_C7-1_PRI_8" |
| Target name for DSP_C7-1_PRI_8 This target task is eighth in priority. | |
| #define | TIVX_TARGET_DSP1 TIVX_TARGET_DSP_C7_1 |
| Name for DSP target class, instance 1. More... | |
| #define | TIVX_TARGET_MCU1_0 "MCU1-0" |
| Name for MCU1 target class, core 0. More... | |
| #define | TIVX_TARGET_IPU1_0 "MCU1-0" |
| Name for IPU1 target class, core 0. More... | |
| #define | TIVX_TARGET_VPAC_LDC1 "VPAC_LDC1" |
| Target name for VPAC LDC1. | |
| #define | TIVX_TARGET_VPAC_MSC1 "VPAC_MSC1" |
| Target name for VPAC MSC1. | |
| #define | TIVX_TARGET_VPAC_MSC2 "VPAC_MSC2" |
| Target name for VPAC MSC2. | |
| #define | TIVX_TARGET_VPAC_VISS1 "VPAC_VISS1" |
| Target name for VPAC VISS1. | |
| #define | TIVX_TARGET_A72_0 "A72-0" |
| Target name for A72_0. | |
| #define | TIVX_TARGET_A72_1 "A72-1" |
| Target name for A72_1. | |
| #define | TIVX_TARGET_A72_2 "A72-2" |
| Target name for A72_2. | |
| #define | TIVX_TARGET_A72_3 "A72-3" |
| Target name for A72_3. | |
| #define | TIVX_TARGET_DSP1 "DSP-1" |
| Name for DSP target class, instance 1. More... | |
| #define | TIVX_TARGET_DSP2 "DSP-2" |
| Name for DSP target class, instance 2. More... | |
| #define | TIVX_TARGET_DSP_C7_1 "DSP_C7-1" |
| Target name for DSP_C7_1 This target task is first in priority. Each of the C7X targets are assigned a different task priority. Subsequent C7X targets are assigned lower priority than the preceding target (i.e., TIVX_TARGET_DSP_C7_1_PRI_2 is lower priority than TIVX_TARGET_DSP_C7_1_PRI_1). Therefore, the TIVX_TARGET_DSP_C7_1_PRI_2 target will be preempted by TIVX_TARGET_DSP_C7_1_PRI_1 once the higher priority target is unblocked to execute. | |
| #define | TIVX_TARGET_DSP_C7_1_PRI_1 TIVX_TARGET_DSP_C7_1 |
| Target name for DSP_C7_1 This target task is first in priority. This aliases to the same task as TIVX_TARGET_DSP_C7_1. | |
| #define | TIVX_TARGET_DSP_C7_1_PRI_2 "DSP_C7-1_PRI_2" |
| Target name for DSP_C7-1_PRI_2 This target task is second in priority. | |
| #define | TIVX_TARGET_DSP_C7_1_PRI_3 "DSP_C7-1_PRI_3" |
| Target name for DSP_C7-1_PRI_3 This target task is third in priority. | |
| #define | TIVX_TARGET_DSP_C7_1_PRI_4 "DSP_C7-1_PRI_4" |
| Target name for DSP_C7-1_PRI_4 This target task is fourth in priority. | |
| #define | TIVX_TARGET_DSP_C7_1_PRI_5 "DSP_C7-1_PRI_5" |
| Target name for DSP_C7-1_PRI_5 This target task is fifth in priority. | |
| #define | TIVX_TARGET_DSP_C7_1_PRI_6 "DSP_C7-1_PRI_6" |
| Target name for DSP_C7-1_PRI_6 This target task is sixth in priority. | |
| #define | TIVX_TARGET_DSP_C7_1_PRI_7 "DSP_C7-1_PRI_7" |
| Target name for DSP_C7-1_PRI_7 This target task is seventh in priority. | |
| #define | TIVX_TARGET_DSP_C7_1_PRI_8 "DSP_C7-1_PRI_8" |
| Target name for DSP_C7-1_PRI_8 This target task is eighth in priority. | |
| #define | TIVX_TARGET_MCU2_0 "MCU2-0" |
| Name for MCU2 target class, core 0. More... | |
| #define | TIVX_TARGET_IPU1_0 "MCU2-0" |
| Name for IPU1 target class, core 0. More... | |
| #define | TIVX_TARGET_MCU2_1 "MCU2-1" |
| Name for MCU2 target class, core 1. More... | |
| #define | TIVX_TARGET_IPU1_1 "MCU2-1" |
| Name for IPU1 target class, core 1. More... | |
| #define | TIVX_TARGET_MCU3_0 "MCU3-0" |
| Name for MCU3_0 target class, core 0. More... | |
| #define | TIVX_TARGET_MCU3_1 "MCU3-1" |
| Name for MCU3_1 target class, core 1. More... | |
| #define | TIVX_TARGET_CAPTURE1 "CAPTURE1" |
| Target name for Capture. | |
| #define | TIVX_TARGET_CAPTURE2 "CAPTURE2" |
| Target name for Capture. | |
| #define | TIVX_TARGET_CAPTURE3 "CAPTURE3" |
| Target name for Capture Node Instance 3. | |
| #define | TIVX_TARGET_CAPTURE4 "CAPTURE4" |
| Target name for Capture Node Instance 4. | |
| #define | TIVX_TARGET_CAPTURE5 "CAPTURE5" |
| Target name for Capture Node Instance 5. | |
| #define | TIVX_TARGET_CAPTURE6 "CAPTURE6" |
| Target name for Capture Node Instance 6. | |
| #define | TIVX_TARGET_CAPTURE7 "CAPTURE7" |
| Target name for Capture Node Instance 7. | |
| #define | TIVX_TARGET_CAPTURE8 "CAPTURE8" |
| Target name for Capture Node Instance 8. | |
| #define | TIVX_TARGET_CSITX "CSITX" |
| Target name for CSITX. | |
| #define | TIVX_TARGET_DISPLAY_M2M1 "DSS_M2M1" |
| Target name for Display M2M Node Instance 1. | |
| #define | TIVX_TARGET_DISPLAY_M2M2 "DSS_M2M2" |
| Target name for Display M2M Node Instance 2. | |
| #define | TIVX_TARGET_DISPLAY_M2M3 "DSS_M2M3" |
| Target name for Display M2M Node Instance 3. | |
| #define | TIVX_TARGET_DISPLAY_M2M4 "DSS_M2M4" |
| Target name for Display M2M Node Instance 4. | |
| #define | TIVX_TARGET_DISPLAY1 "DISPLAY1" |
| Target name for Display. | |
| #define | TIVX_TARGET_DISPLAY2 "DISPLAY2" |
| Target name for Display. | |
| #define | TIVX_TARGET_DMPAC_DOF "DMPAC_DOF" |
| Target name for DMPAC DOF. | |
| #define | TIVX_TARGET_DMPAC_SDE "DMPAC_SDE" |
| Target name for DMPAC SDE. | |
| #define | TIVX_TARGET_VPAC_LDC1 "VPAC_LDC1" |
| Target name for VPAC LDC1. | |
| #define | TIVX_TARGET_VPAC_MSC1 "VPAC_MSC1" |
| Target name for VPAC MSC1. | |
| #define | TIVX_TARGET_VPAC_MSC2 "VPAC_MSC2" |
| Target name for VPAC MSC2. | |
| #define | TIVX_TARGET_VPAC_NF "VPAC_NF" |
| Target name for VPAC NF. | |
| #define | TIVX_TARGET_VPAC_VISS1 "VPAC_VISS1" |
| Target name for VPAC VISS1. | |
| #define TIVX_TARGET_DSP1 TIVX_TARGET_DSP_C7_1 |
Name for DSP target class, instance 1.
Assigned to DSP_C7_1 core
Definition at line 179 of file tivx_soc_am62a.h.
| #define TIVX_TARGET_MCU1_0 "MCU1-0" |
Name for MCU1 target class, core 0.
Assigned to MCU1_0 core
Definition at line 187 of file tivx_soc_am62a.h.
| #define TIVX_TARGET_IPU1_0 "MCU1-0" |
Name for IPU1 target class, core 0.
Assigned to IPU1_0 core
Definition at line 201 of file tivx_soc_am62a.h.
| #define TIVX_TARGET_DSP1 "DSP-1" |
Name for DSP target class, instance 1.
Assigned to C66_0 core
Definition at line 123 of file tivx_soc_j721e.h.
| #define TIVX_TARGET_DSP2 "DSP-2" |
Name for DSP target class, instance 2.
Assigned to C66_1 core
Definition at line 131 of file tivx_soc_j721e.h.
| #define TIVX_TARGET_MCU2_0 "MCU2-0" |
Name for MCU2 target class, core 0.
Assigned to MCU2_0 core
Definition at line 202 of file tivx_soc_j721e.h.
| #define TIVX_TARGET_IPU1_0 "MCU2-0" |
Name for IPU1 target class, core 0.
Assigned to IPU1_0 core
Definition at line 210 of file tivx_soc_j721e.h.
| #define TIVX_TARGET_MCU2_1 "MCU2-1" |
Name for MCU2 target class, core 1.
Assigned to MCU2_1 core
Definition at line 218 of file tivx_soc_j721e.h.
| #define TIVX_TARGET_IPU1_1 "MCU2-1" |
Name for IPU1 target class, core 1.
Assigned to IPU1_1 core
Definition at line 226 of file tivx_soc_j721e.h.
| #define TIVX_TARGET_MCU3_0 "MCU3-0" |
Name for MCU3_0 target class, core 0.
Assigned to MCU3_0 core
Definition at line 234 of file tivx_soc_j721e.h.
| #define TIVX_TARGET_MCU3_1 "MCU3-1" |
Name for MCU3_1 target class, core 1.
Assigned to MCU3_1 core
Definition at line 242 of file tivx_soc_j721e.h.
1.8.14