Csitx_DPhyCfg Struct Reference

Detailed Description

D-PHY configuration structure.

Data Fields
uint32_t	inst
uint32_t	psmClkFreqDiv
uint32_t	pllByteClkDiv
uint32_t	pwmCtrlDivLow
uint32_t	pwmCtrlDivHigh
uint32_t	pllLockThreshold
uint32_t	pllLockStart
uint32_t	pllIpDiv
uint32_t	pllOpDiv
uint32_t	pllFbDiv
uint32_t	pllPd
uint32_t	laneBandSpeed
uint32_t	waitBurstTime
uint32_t	txClkExitTime
uint32_t	dlWkupTime
uint32_t	clWkupTime
uint32_t	clkMode
uint32_t	dphyMode
uint32_t	clSlewRateCtrl
uint32_t	dlSlewRateCtrl
uint32_t	laneSpeedMbps

Field Documentation

inst

uint32_t Csitx_DPhyCfg::inst

CSITX istance. See CSITX_InstanceId for details

psmClkFreqDiv

uint32_t Csitx_DPhyCfg::psmClkFreqDiv

PMA state machine clock frequency divider control. Valid values: 1 to 255

pllByteClkDiv

uint32_t Csitx_DPhyCfg::pllByteClkDiv

Selects the byte clock divider value, by driving the cmnda_pll_byteclk_div signal to the analog. Valid values: 0x01: Div 1 0x02: Div 2 0x04: Div 4 0x08: Div 8 0x10: Div 16 0x20: Div 32

pwmCtrlDivLow

uint32_t Csitx_DPhyCfg::pwmCtrlDivLow

Low division value setting for the gm PWM control divider. Valid values: 1 to 1023

pwmCtrlDivHigh

uint32_t Csitx_DPhyCfg::pwmCtrlDivHigh

High division value setting for the gm PWM control divider. Valid values: 1 to 1023

pllLockThreshold

uint32_t Csitx_DPhyCfg::pllLockThreshold

pllcnt lock threshold value for PLL lock detect module. Valid values: 1 to 65535

pllLockStart

uint32_t Csitx_DPhyCfg::pllLockStart

pllcnt start value for PLL lock detect module. Valid values: 1 to 65535

pllIpDiv

uint32_t Csitx_DPhyCfg::pllIpDiv

PLL IP Divider value. This value is calculated in the driver.

pllOpDiv

uint32_t Csitx_DPhyCfg::pllOpDiv

PLL OP Divider value. This value is calculated in the driver

pllFbDiv

uint32_t Csitx_DPhyCfg::pllFbDiv

PLL IP Divider value. This value is calculated in the driver

pllPd

uint32_t Csitx_DPhyCfg::pllPd

PLL PD value. 0: Disable and 1: Enable

laneBandSpeed

uint32_t Csitx_DPhyCfg::laneBandSpeed

Data rates for lane band control. This parameter is optional if valid value for 'laneSpeedMbps' is provided by the application i.e. 'laneSpeedMbps' is updated by the application after init to a valid value. See Csitx_LaneBandSpeed for details

waitBurstTime

uint32_t Csitx_DPhyCfg::waitBurstTime

Tx clock exit time - Number of tx_byte_clk cycles corresponding to the HS clock exit time. Valid values: 1 to 255

txClkExitTime

uint32_t Csitx_DPhyCfg::txClkExitTime

Wait Burst Time - Number of tx_byte_clk cycles corresponding to the inter HS burst gap. Valid values: 1 to 255

dlWkupTime

uint32_t Csitx_DPhyCfg::dlWkupTime

D-PHY data lane wakeup time in ppi_tx_esc_clk cycles. Valid values: 1 to 65535

clWkupTime

uint32_t Csitx_DPhyCfg::clWkupTime

D-PHY clock lane wakeup time in ppi_tx_esc_clk cycles. Valid values: 1 to 65535

clkMode

uint32_t Csitx_DPhyCfg::clkMode

DPHY Clock Mode. See Csitx_ClkMode for details

dphyMode

uint32_t Csitx_DPhyCfg::dphyMode

DPHY Mode. See Csitx_DphyMode for details This parameter is only valid when 'clkMode' is 'CSITX_CLK_MODE_NON_CONTINUOUS'.

clSlewRateCtrl

uint32_t Csitx_DPhyCfg::clSlewRateCtrl

Slew Rate: Slew rate control for clock lane. Range [0-31] Slew Rate Control Values: value 0 is for minimum slew cap i.e faster slew rate value 31 is for maximum slew cap i.e slowest slew rate Default Slew Rate Control Values: For 80M to 1Gbps : 27 For 1Gbps to 1.5Gbps : 7 For 1.5Gbps to 2.5Gbps : 1

dlSlewRateCtrl

uint32_t Csitx_DPhyCfg::dlSlewRateCtrl

Slew Rate: Slew rate control for data lane. Range [0-31] Slew Rate Control Values: value 0 is for minimum slew cap i.e faster slew rate value 31 is for maximum slew cap i.e slowest slew rate Default Slew Rate Control Values: For 80M to 1Gbps : 27 For 1Gbps to 1.5Gbps : 7 For 1.5Gbps to 2.5Gbps : 1

laneSpeedMbps

uint32_t Csitx_DPhyCfg::laneSpeedMbps

Exact DPHY lane speed from the selected speed band in Megabits per sec. This parameter is set to default value during init time. If updated in the application after init, newly set value will be used for DPHY clock configurations. If this parameter is set by the application, then application need not to set 'laneBandSpeed' parameter as it will be auto-calculated in the driver during create time.