 |
PDK API Guide for J721E
|
|
PDK API Guide for J721E
|
This is CSITX documentation specific to J7ES SoC
Files | |
| file | csitx_soc.h |
| CSITX Low Level Driver SOC specific file. | |
Data Structures | |
| struct | Csitx_DPhyCfg |
| D-PHY configuration structure. More... | |
Functions | |
| void | Csitx_initDPhyCfgParams (Csitx_DPhyCfg *dphyCfg) |
| Csitx_DPhyCfg structure init function. More... | |
Macros | |
| #define | CSITX_NUM_STREAM (1U) |
| CSITX DRV Numbers: Number of stream per CSI TX module. More... | |
CSITX Module Instance ID | |
| #define | CSITX_INSTANCE_ID_0 ((uint32_t) 0x0U) |
| CSITX Module Instance ID: CSI2TX Module 0. More... | |
| #define | CSITX_INSTANCE_ID_MAX ((uint32_t)CSITX_INSTANCE_ID_0 + 1U) |
| Maximum value of CSITX Module Instance. More... | |
CSITX SoC integration details | |
Different instances of CSI Tx transmit module supported in the Instance and their configuration/integration supported in the Instance. | |
| #define | CSITX_NUM_STRMS_TX ((uint32_t) 1U) |
| Total number of transmit processing streams available in the Instance. More... | |
| #define | CSITX_NUM_STRMS_COLORBAR ((uint32_t) 1U) |
| Total number of COLORBAR streams available in the Instance. Note: COLORBAR stream is only supported on 'CSITX_INSTANCE_ID_0' only. More... | |
| #define | CSITX_NUM_STRMS_LPBK ((uint32_t) 2U) |
| Total number of Loop-back streams available in the Instance. More... | |
| #define | CSITX_NUM_CH_TX ((uint32_t) 32U) |
| Number of transmit channels per CSITX instance. More... | |
| #define | CSITX_NUM_CH_LPBK ((uint32_t) 1U) |
| Number of transmit channels per CSITX instance. More... | |
| #define | CSITX_NUM_CH_TX_MAX |
| Number of transmit channels that can run in parallel in the Instance. More... | |
| #define | CSITX_NUM_CH_COLORBAR_MAX ((uint32_t) 1U) |
| Number of COLORBAR channels that can run in parallel in the Instance. More... | |
| #define | CSITX_NUM_CH_LPBK_MAX |
| Number of Loop-back channels that can run in parallel in the Instance. Note: Though each CSI instance have one loop-back stream, only one can be used in the Instance which can be configured on any instance. More... | |
| #define | CSITX_NUM_CH_MAX |
| Maximum number of channels that can be processed per CSITX module These many valid channel configurations can exists per CSITX DRV instance. More... | |
| #define | CSITX_TX_DATA_LANES_MAX ((uint32_t)4U) |
| Defines total number of physical data lanes that can be used per CSITX instance. More... | |
| #define | CSITX_TX_CLK_LANES_MAX ((uint32_t)1U) |
| Defines total number of physical clock lanes that can be used per CSITX instance. More... | |
| #define | CSITX_TX_VC_CFG_MAX ((uint32_t)16U) |
| Defines total number of VC configurations available CSITX instance. More... | |
| #define | CSITX_TX_DT_CFG_MAX ((uint32_t)16U) |
| Defines total number of DT configurations available CSITX instance. More... | |
| #define | CSITX_TX_STRM_NUM_MAX ((uint32_t)4U) |
| Defines total number of streams available CSITX instance. More... | |
| #define | CSITX_TX_STRM_FIFO_FILL_LVL ((uint32_t)960U) |
| Defines total number of words for stream FIFO fill level 1920 RAW12 format, 1920 * 12 / 32 = 720. More... | |
| #define | CSITX_NUM_STRMS_TX_ID ((uint32_t) 0U) |
| Tx Stream ID. More... | |
| #define | CSITX_NUM_STRMS_TX_COLORBAR ((uint32_t) 1U) |
| Color-bar Stream ID. More... | |
| #define | CSITX_NUM_STRMS_TX_RETRANS_0 ((uint32_t) 2U) |
| Re-transmit Stream 0 ID. More... | |
| #define | CSITX_NUM_STRMS_TX_RETRANS_1 ((uint32_t) 3U) |
| Re-transmit Stream 1 ID. More... | |
CSITX D-PHY lane band speed | |
| #define | CSITX_LANE_BAND_SPEED_80_TO_100_MBPS ((uint32_t) 0x00U) |
| Lane Band Speed: 80 Mbps to 100 Mbps. More... | |
| #define | CSITX_LANE_BAND_SPEED_100_TO_120_MBPS ((uint32_t) 0x01U) |
| Lane Band Speed: 100 Mbps to 120 Mbps. More... | |
| #define | CSITX_LANE_BAND_SPEED_120_TO_160_MBPS ((uint32_t) 0x02U) |
| Lane Band Speed: 120 Mbps to 160 Mbps. More... | |
| #define | CSITX_LANE_BAND_SPEED_160_TO_200_MBPS ((uint32_t) 0x03U) |
| Lane Band Speed: 160 Mbps to 200 Mbps. More... | |
| #define | CSITX_LANE_BAND_SPEED_200_TO_240_MBPS ((uint32_t) 0x04U) |
| Lane Band Speed: 200 Mbps to 240 Mbps. More... | |
| #define | CSITX_LANE_BAND_SPEED_240_TO_320_MBPS ((uint32_t) 0x05U) |
| Lane Band Speed: 240 Mbps to 320 Mbps. More... | |
| #define | CSITX_LANE_BAND_SPEED_320_TO_390_MBPS ((uint32_t) 0x06U) |
| Lane Band Speed: 320 Mbps to 390 Mbps. More... | |
| #define | CSITX_LANE_BAND_SPEED_390_TO_450_MBPS ((uint32_t) 0x07U) |
| Lane Band Speed: 390 Mbps to 450 Mbps. More... | |
| #define | CSITX_LANE_BAND_SPEED_450_TO_510_MBPS ((uint32_t) 0x08U) |
| Lane Band Speed: 450 Mbps to 520 Mbps. More... | |
| #define | CSITX_LANE_BAND_SPEED_510_TO_560_MBPS ((uint32_t) 0x09U) |
| Lane Band Speed: 510 Mbps to 560 Mbps. More... | |
| #define | CSITX_LANE_BAND_SPEED_560_TO_640_MBPS ((uint32_t) 0x0AU) |
| Lane Band Speed: 560 Mbps to 640 Mbps. More... | |
| #define | CSITX_LANE_BAND_SPEED_640_TO_690_MBPS ((uint32_t) 0x0BU) |
| Lane Band Speed: 640 Mbps to 690 Mbps. More... | |
| #define | CSITX_LANE_BAND_SPEED_690_TO_770_MBPS ((uint32_t) 0x0CU) |
| Lane Band Speed: 690 Mbps to 770 Mbps. More... | |
| #define | CSITX_LANE_BAND_SPEED_770_TO_870_MBPS ((uint32_t) 0x0DU) |
| Lane Band Speed: 770 Mbps to 870 Mbps. More... | |
| #define | CSITX_LANE_BAND_SPEED_870_TO_950_MBPS ((uint32_t) 0x0EU) |
| Lane Band Speed: 870 Mbps to 950 Mbps. More... | |
| #define | CSITX_LANE_BAND_SPEED_950_TO_1000_MBPS ((uint32_t) 0x0FU) |
| Lane Band Speed: 950 Mbps to 1000 Mbps. More... | |
| #define | CSITX_LANE_BAND_SPEED_1000_TO_1200_MBPS ((uint32_t) 0x10U) |
| Lane Band Speed: 1000 Mbps to 1200 Mbps. More... | |
| #define | CSITX_LANE_BAND_SPEED_1200_TO_1400_MBPS ((uint32_t) 0x11U) |
| Lane Band Speed: 1200 Mbps to 1400 Mbps. More... | |
| #define | CSITX_LANE_BAND_SPEED_1400_TO_1600_MBPS ((uint32_t) 0x12U) |
| Lane Band Speed: 1400 Mbps to 1600 Mbps. More... | |
| #define | CSITX_LANE_BAND_SPEED_1600_TO_1800_MBPS ((uint32_t) 0x13U) |
| Lane Band Speed: 1600 Mbps to 1800 Mbps. More... | |
| #define | CSITX_LANE_BAND_SPEED_1800_TO_2000_MBPS ((uint32_t) 0x14U) |
| Lane Band Speed: 1800 Mbps to 2000 Mbps. More... | |
| #define | CSITX_LANE_BAND_SPEED_2000_TO_2200_MBPS ((uint32_t) 0x15U) |
| Lane Band Speed: 2000 Mbps to 2200 Mbps. More... | |
| #define | CSITX_LANE_BAND_SPEED_2200_TO_2500_MBPS ((uint32_t) 0x16U) |
| Lane Band Speed: 2200 Mbps to 2500 Mbps. More... | |
| #define | CSITX_LANE_BAND_SPEED_RESERVED ((uint32_t) 0x17U) |
| Lane Band Speed: Reserved. More... | |
CSITX D-PHY clock mode | |
| #define | CSITX_CLK_MODE_CONTINUOUS ((uint32_t) 0x0U) |
| DPHY Clock Mode: Continuous. More... | |
| #define | CSITX_CLK_MODE_NON_CONTINUOUS ((uint32_t) 0x1U) |
| DPHY Clock Mode: Non-continuous. More... | |
CSITX D-PHY mode | |
| #define | CSITX_DPHY_MODE_ULP ((uint32_t) 0x0U) |
| DPHY Clock Mode: ultra low power. More... | |
| #define | CSITX_DPHY_MODE_HIGH_SPEED ((uint32_t) 0x1U) |
| DPHY Clock Mode: high speed. More... | |
| #define | CSITX_DPHY_MODE_LOW_POWER ((uint32_t) 0x2U) |
| DPHY Clock Mode: low power stop state. More... | |
CSITX Stream ID | |
CSI2 TX streams are hw entities that processes incoming frames and sends it to particular destination like DDR, VISS/VP and CSI2 TX. Mapping of streams to destination is fixed in the design and can not be changes runtime. | |
| #define | CSITX_STREAM_ID_INST_0_STRM_0 ((uint32_t) 0x0U) |
| CSITX Instance ID: transmit stream0 0 on CSI2TX Module 0. More... | |
| #define | CSITX_STREAM_ID_INST_0_STRM_1 ((uint32_t) 0x1U) |
| CSITX Instance ID: Color-bar stream on CSI2TX Module 0. More... | |
| #define | CSITX_STREAM_ID_INST_0_STRM_2 ((uint32_t) 0x2U) |
| CSITX Instance ID: CSI2RX loop-back 0 on CSI2TX Module 0. More... | |
| #define | CSITX_STREAM_ID_INST_0_STRM_3 ((uint32_t) 0x3U) |
| CSITX Instance ID: CSI2RX loop-back 1 on CSI2TX Module 0. More... | |
| #define CSITX_INSTANCE_ID_0 ((uint32_t) 0x0U) |
CSITX Module Instance ID: CSI2TX Module 0.
| #define CSITX_INSTANCE_ID_MAX ((uint32_t)CSITX_INSTANCE_ID_0 + 1U) |
Maximum value of CSITX Module Instance.
| #define CSITX_NUM_STRMS_TX ((uint32_t) 1U) |
Total number of transmit processing streams available in the Instance.
| #define CSITX_NUM_STRMS_COLORBAR ((uint32_t) 1U) |
Total number of COLORBAR streams available in the Instance. Note: COLORBAR stream is only supported on 'CSITX_INSTANCE_ID_0' only.
| #define CSITX_NUM_STRMS_LPBK ((uint32_t) 2U) |
Total number of Loop-back streams available in the Instance.
| #define CSITX_NUM_CH_TX ((uint32_t) 32U) |
Number of transmit channels per CSITX instance.
| #define CSITX_NUM_CH_LPBK ((uint32_t) 1U) |
Number of transmit channels per CSITX instance.
| #define CSITX_NUM_CH_TX_MAX |
Number of transmit channels that can run in parallel in the Instance.
| #define CSITX_NUM_CH_COLORBAR_MAX ((uint32_t) 1U) |
Number of COLORBAR channels that can run in parallel in the Instance.
| #define CSITX_NUM_CH_LPBK_MAX |
Number of Loop-back channels that can run in parallel in the Instance. Note: Though each CSI instance have one loop-back stream, only one can be used in the Instance which can be configured on any instance.
| #define CSITX_NUM_CH_MAX |
Maximum number of channels that can be processed per CSITX module These many valid channel configurations can exists per CSITX DRV instance.
| #define CSITX_TX_DATA_LANES_MAX ((uint32_t)4U) |
Defines total number of physical data lanes that can be used per CSITX instance.
| #define CSITX_TX_CLK_LANES_MAX ((uint32_t)1U) |
Defines total number of physical clock lanes that can be used per CSITX instance.
| #define CSITX_TX_VC_CFG_MAX ((uint32_t)16U) |
Defines total number of VC configurations available CSITX instance.
| #define CSITX_TX_DT_CFG_MAX ((uint32_t)16U) |
Defines total number of DT configurations available CSITX instance.
| #define CSITX_TX_STRM_NUM_MAX ((uint32_t)4U) |
Defines total number of streams available CSITX instance.
| #define CSITX_TX_STRM_FIFO_FILL_LVL ((uint32_t)960U) |
Defines total number of words for stream FIFO fill level 1920 RAW12 format, 1920 * 12 / 32 = 720.
| #define CSITX_NUM_STRMS_TX_ID ((uint32_t) 0U) |
Tx Stream ID.
| #define CSITX_NUM_STRMS_TX_COLORBAR ((uint32_t) 1U) |
Color-bar Stream ID.
| #define CSITX_NUM_STRMS_TX_RETRANS_0 ((uint32_t) 2U) |
Re-transmit Stream 0 ID.
| #define CSITX_NUM_STRMS_TX_RETRANS_1 ((uint32_t) 3U) |
Re-transmit Stream 1 ID.
| #define CSITX_LANE_BAND_SPEED_80_TO_100_MBPS ((uint32_t) 0x00U) |
Lane Band Speed: 80 Mbps to 100 Mbps.
| #define CSITX_LANE_BAND_SPEED_100_TO_120_MBPS ((uint32_t) 0x01U) |
Lane Band Speed: 100 Mbps to 120 Mbps.
| #define CSITX_LANE_BAND_SPEED_120_TO_160_MBPS ((uint32_t) 0x02U) |
Lane Band Speed: 120 Mbps to 160 Mbps.
| #define CSITX_LANE_BAND_SPEED_160_TO_200_MBPS ((uint32_t) 0x03U) |
Lane Band Speed: 160 Mbps to 200 Mbps.
| #define CSITX_LANE_BAND_SPEED_200_TO_240_MBPS ((uint32_t) 0x04U) |
Lane Band Speed: 200 Mbps to 240 Mbps.
| #define CSITX_LANE_BAND_SPEED_240_TO_320_MBPS ((uint32_t) 0x05U) |
Lane Band Speed: 240 Mbps to 320 Mbps.
| #define CSITX_LANE_BAND_SPEED_320_TO_390_MBPS ((uint32_t) 0x06U) |
Lane Band Speed: 320 Mbps to 390 Mbps.
| #define CSITX_LANE_BAND_SPEED_390_TO_450_MBPS ((uint32_t) 0x07U) |
Lane Band Speed: 390 Mbps to 450 Mbps.
| #define CSITX_LANE_BAND_SPEED_450_TO_510_MBPS ((uint32_t) 0x08U) |
Lane Band Speed: 450 Mbps to 520 Mbps.
| #define CSITX_LANE_BAND_SPEED_510_TO_560_MBPS ((uint32_t) 0x09U) |
Lane Band Speed: 510 Mbps to 560 Mbps.
| #define CSITX_LANE_BAND_SPEED_560_TO_640_MBPS ((uint32_t) 0x0AU) |
Lane Band Speed: 560 Mbps to 640 Mbps.
| #define CSITX_LANE_BAND_SPEED_640_TO_690_MBPS ((uint32_t) 0x0BU) |
Lane Band Speed: 640 Mbps to 690 Mbps.
| #define CSITX_LANE_BAND_SPEED_690_TO_770_MBPS ((uint32_t) 0x0CU) |
Lane Band Speed: 690 Mbps to 770 Mbps.
| #define CSITX_LANE_BAND_SPEED_770_TO_870_MBPS ((uint32_t) 0x0DU) |
Lane Band Speed: 770 Mbps to 870 Mbps.
| #define CSITX_LANE_BAND_SPEED_870_TO_950_MBPS ((uint32_t) 0x0EU) |
Lane Band Speed: 870 Mbps to 950 Mbps.
| #define CSITX_LANE_BAND_SPEED_950_TO_1000_MBPS ((uint32_t) 0x0FU) |
Lane Band Speed: 950 Mbps to 1000 Mbps.
| #define CSITX_LANE_BAND_SPEED_1000_TO_1200_MBPS ((uint32_t) 0x10U) |
Lane Band Speed: 1000 Mbps to 1200 Mbps.
| #define CSITX_LANE_BAND_SPEED_1200_TO_1400_MBPS ((uint32_t) 0x11U) |
Lane Band Speed: 1200 Mbps to 1400 Mbps.
| #define CSITX_LANE_BAND_SPEED_1400_TO_1600_MBPS ((uint32_t) 0x12U) |
Lane Band Speed: 1400 Mbps to 1600 Mbps.
| #define CSITX_LANE_BAND_SPEED_1600_TO_1800_MBPS ((uint32_t) 0x13U) |
Lane Band Speed: 1600 Mbps to 1800 Mbps.
| #define CSITX_LANE_BAND_SPEED_1800_TO_2000_MBPS ((uint32_t) 0x14U) |
Lane Band Speed: 1800 Mbps to 2000 Mbps.
| #define CSITX_LANE_BAND_SPEED_2000_TO_2200_MBPS ((uint32_t) 0x15U) |
Lane Band Speed: 2000 Mbps to 2200 Mbps.
| #define CSITX_LANE_BAND_SPEED_2200_TO_2500_MBPS ((uint32_t) 0x16U) |
Lane Band Speed: 2200 Mbps to 2500 Mbps.
| #define CSITX_LANE_BAND_SPEED_RESERVED ((uint32_t) 0x17U) |
Lane Band Speed: Reserved.
| #define CSITX_CLK_MODE_CONTINUOUS ((uint32_t) 0x0U) |
DPHY Clock Mode: Continuous.
| #define CSITX_CLK_MODE_NON_CONTINUOUS ((uint32_t) 0x1U) |
DPHY Clock Mode: Non-continuous.
| #define CSITX_DPHY_MODE_ULP ((uint32_t) 0x0U) |
DPHY Clock Mode: ultra low power.
| #define CSITX_DPHY_MODE_HIGH_SPEED ((uint32_t) 0x1U) |
DPHY Clock Mode: high speed.
| #define CSITX_DPHY_MODE_LOW_POWER ((uint32_t) 0x2U) |
DPHY Clock Mode: low power stop state.
| #define CSITX_NUM_STREAM (1U) |
CSITX DRV Numbers: Number of stream per CSI TX module.
| #define CSITX_STREAM_ID_INST_0_STRM_0 ((uint32_t) 0x0U) |
CSITX Instance ID: transmit stream0 0 on CSI2TX Module 0.
| #define CSITX_STREAM_ID_INST_0_STRM_1 ((uint32_t) 0x1U) |
CSITX Instance ID: Color-bar stream on CSI2TX Module 0.
| #define CSITX_STREAM_ID_INST_0_STRM_2 ((uint32_t) 0x2U) |
CSITX Instance ID: CSI2RX loop-back 0 on CSI2TX Module 0.
| #define CSITX_STREAM_ID_INST_0_STRM_3 ((uint32_t) 0x3U) |
CSITX Instance ID: CSI2RX loop-back 1 on CSI2TX Module 0.
| void Csitx_initDPhyCfgParams | ( | Csitx_DPhyCfg * | dphyCfg | ) |
Csitx_DPhyCfg structure init function.
| dphyCfg | [IN] Pointer to Csitx_DPhyCfg structure. |
Note: If given 'dphyCfg.laneBandSpeed' does no match with pre-defined configurations, this API will default the DPHY parameters for 800 Mbps. Application should change the DPHY parameters (if needed) prior to calling 'Fvid2_create()'. Pre-defined configurations are supported for following lane-speeds:
1.8.15