PDK API Guide for J721E
CSL_CPGMAC_SL_MACSTATUS Struct Reference

Detailed Description

Holds MAC status register contents.

Data Fields

Uint32 txFlowActive
 
Uint32 rxFlowActive
 
Uint32 extFullDuplexEnabled
 
Uint32 extGigabitEnabled
 
Uint32 extRxFlowEnabled
 
Uint32 extTxFlowEnabled
 
Uint32 rxPfcFlowAct
 
Uint32 txPfcFlowAct
 
Uint32 torfPri
 
Uint32 torf
 
Uint32 macTxIdle
 
Uint32 expressMacIdle
 
Uint32 preemptMacIdle
 
Uint32 idle
 

Field Documentation

◆ txFlowActive

Uint32 CSL_CPGMAC_SL_MACSTATUS::txFlowActive

Transmit Flow Control Active - When asserted, this bit indicates that the pause time period is being observed for a received pause frame. No new transmissions will begin while this bit is asserted except for the transmission of pause frames. Any transmission in progress when this bit is asserted will complete.

◆ rxFlowActive

Uint32 CSL_CPGMAC_SL_MACSTATUS::rxFlowActive

Receive Flow Control Active - When asserted, indicates that receive flow control is enabled and triggered

◆ extFullDuplexEnabled

Uint32 CSL_CPGMAC_SL_MACSTATUS::extFullDuplexEnabled

External Fullduplex - Value of the EXT_FULLDUPLEX input bit.

◆ extGigabitEnabled

Uint32 CSL_CPGMAC_SL_MACSTATUS::extGigabitEnabled

External GIG - This is the value of the EXT_GIG input bit.

◆ extRxFlowEnabled

Uint32 CSL_CPGMAC_SL_MACSTATUS::extRxFlowEnabled

External Receive Flow Control Enable - This is the value of the EXT_RX_FLOW_EN input bit.

◆ extTxFlowEnabled

Uint32 CSL_CPGMAC_SL_MACSTATUS::extTxFlowEnabled

External Transmit Flow Control Enable - This is the value of the EXT_TX_FLOW_EN input bit

◆ rxPfcFlowAct

Uint32 CSL_CPGMAC_SL_MACSTATUS::rxPfcFlowAct

Receive Priority Based Flow Control Active (priority 7 down to 0)

◆ txPfcFlowAct

Uint32 CSL_CPGMAC_SL_MACSTATUS::txPfcFlowAct

Transmit Priority Based Flow Control Active (priority 7 down to 0)

◆ torfPri

Uint32 CSL_CPGMAC_SL_MACSTATUS::torfPri

The lowest priority that caused top of receive FIFO flow control trigger since the last write to clear.

◆ torf

Uint32 CSL_CPGMAC_SL_MACSTATUS::torf

Top of receive FIFO flow control trigger occurred.

◆ macTxIdle

Uint32 CSL_CPGMAC_SL_MACSTATUS::macTxIdle

Mac Transmit Idle - Both Prempt and Express MAC Transmit in idle state.

◆ expressMacIdle

Uint32 CSL_CPGMAC_SL_MACSTATUS::expressMacIdle

Express MAC is idle .If IET is not enabled all traffic is express traffic

◆ preemptMacIdle

Uint32 CSL_CPGMAC_SL_MACSTATUS::preemptMacIdle

Prempt MAC is idle

◆ idle

Uint32 CSL_CPGMAC_SL_MACSTATUS::idle

The Ethernet port (express and preempt (if present)) are in idle state