SDL API Guide for J7200
sdl_esm_core.h
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1 /*
2  * SDL ESM
3  *
4  * Software Diagnostics Reference module for Error Signaling Module
5  *
6  * Copyright (c) Texas Instruments Incorporated 2021
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  *
12  * Redistributions of source code must retain the above copyright
13  * notice, this list of conditions and the following disclaimer.
14  *
15  * Redistributions in binary form must reproduce the above copyright
16  * notice, this list of conditions and the following disclaimer in the
17  * documentation and/or other materials provided with the
18  * distribution.
19  *
20  * Neither the name of Texas Instruments Incorporated nor the names of
21  * its contributors may be used to endorse or promote products derived
22  * from this software without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35  *
36  */
37 
38 #ifndef INCLUDE_SDL_ESM_CORE_H_
39 #define INCLUDE_SDL_ESM_CORE_H_
40 #include <src/ip/sdl_esm.h>
41 
42 #if defined (SOC_J721E)
43 #include <include/soc/j721e/sdlr_intr_mcu_esm0.h>
44 #include <include/soc/j721e/sdlr_intr_esm0.h>
45 #endif /* SOC_J721E */
46 
47 #if defined (SOC_J7200)
48 #include <include/soc/j7200/sdlr_intr_mcu_esm0.h>
49 #include <include/soc/j7200/sdlr_intr_esm0.h>
50 #endif /* SOC_J7200 */
51 
52 #ifdef __cplusplus
53 extern "C" {
54 #endif
55 
56 /* Enumerate Interrupt number for the different esm interrupts */
57 #define SDL_MCU_ESM_HI_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_MCU_ESM0_ESM_INT_HI_LVL_0
58 #define SDL_MCU_ESM_LO_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_MCU_ESM0_ESM_INT_LOW_LVL_0
59 #define SDL_MCU_ESM_CFG_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_MCU_ESM0_ESM_INT_CFG_LVL_0
60 
61 #define SDL_WKUP_ESM_HI_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_WKUP_ESM0_ESM_INT_HI_LVL_0
62 #define SDL_WKUP_ESM_LO_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_WKUP_ESM0_ESM_INT_LOW_LVL_0
63 #define SDL_WKUP_ESM_CFG_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_WKUP_ESM0_ESM_INT_CFG_LVL_0
64 
65 #define SDL_MAIN_ESM_HI_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_ESM0_ESM_INT_HI_LVL_0
66 #define SDL_MAIN_ESM_LO_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_ESM0_ESM_INT_LOW_LVL_0
67 #define SDL_MAIN_ESM_CFG_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_ESM0_ESM_INT_CFG_LVL_0
68 
69 /* Enumerate ESM events for R5F core handled by SDL */
70 #define SDL_ESM_MCU_R5_CORE0_SEC_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CORE0_ECC_CORRECTED_LEVEL_0
71 #define SDL_ESM_MCU_R5_CORE0_DED_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CORE0_ECC_UNCORRECTED_LEVEL_0
72 #define SDL_ESM_MCU_R5_CORE1_SEC_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CORE1_ECC_CORRECTED_LEVEL_0
73 #define SDL_ESM_MCU_R5_CORE1_DED_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CORE1_ECC_UNCORRECTED_LEVEL_0
74 #define SDL_ESM_MAIN_ESM_ERROR_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_GLUELOGIC_ESM_MAIN_ERR_GLUE_ERR_I_N_0
75 
76 
77 #if defined (SOC_J721E)
78 #define SDL_ESM_MCU_RTI0_WWD_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_RTI0_INTR_WWD_0
79 #define SDL_ESM_MCU_RTI1_WWD_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_RTI1_INTR_WWD_0
80 #define SDL_ESM_MCU_R5_SELFTEST_ERR_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_SELFTEST_ERR_PULSE_0
81 #define SDL_ESM_MCU_R5_CPU_BUS_CMP_ERR SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_COMPARE_ERR_PULSE_0
82 #define SDL_ESM_MCU_R5_INACTIVITY_ERR_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_BUS_MONITOR_ERR_PULSE_0
83 #define SDL_ESM_MCU_R5_VIM_BUS_CMP_ERR_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_VIM_COMPARE_ERR_PULSE_0
84 #define SDL_ESM_MCU_R5_CCM_STAT_ERR_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_CCM_COMPARE_STAT_PULSE_INTR_0
85 #define SDL_ESM_MAIN_MSMC_ECC_AGGR0_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_0
86 #define SDL_ESM_MAIN_MSMC_ECC_AGGR0_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_1
87 #define SDL_ESM_MAIN_MSMC_ECC_AGGR1_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_2
88 #define SDL_ESM_MAIN_MSMC_ECC_AGGR1_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_3
89 #define SDL_ESM_MAIN_MSMC_ECC_AGGR2_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_4
90 #define SDL_ESM_MAIN_MSMC_ECC_AGGR2_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_5
91 #define SDL_ESM_MAIN_A72_ECC_AGGR0_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_7
92 #define SDL_ESM_MAIN_A72_ECC_AGGR0_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_8
93 #define SDL_ESM_MAIN_A72_ECC_AGGR1_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_9
94 #define SDL_ESM_MAIN_A72_ECC_AGGR1_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_10
95 #define SDL_ESM_MAIN_A72_ECC_AGGR2_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_11
96 #define SDL_ESM_MAIN_A72_ECC_AGGR2_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_12
97 
98 #define SDL_ESM_MCU_CBASS_ECC_AGGR_SEC_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR0_CORR_LEVEL_0
99 #define SDL_ESM_MCU_CBASS_ECC_AGGR_DED_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR0_UNCORR_LEVEL_0
100 #endif /* SOC_J721E */
101 
102 #if defined (SOC_J7200)
103 #define SDL_ESM_MCU_RTI0_WWD_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_RTI0_INTR_WWD_0
104 #define SDL_ESM_MCU_RTI1_WWD_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_RTI1_INTR_WWD_0
105 #define SDL_ESM_MCU_R5_SELFTEST_ERR_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_COMMON0_SELFTEST_ERR_PULSE_0
106 #define SDL_ESM_MCU_R5_CPU_BUS_CMP_ERR SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_COMMON0_COMPARE_ERR_PULSE_0
107 #define SDL_ESM_MCU_R5_INACTIVITY_ERR_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_COMMON0_BUS_MONITOR_ERR_PULSE_0
108 #define SDL_ESM_MCU_R5_VIM_BUS_CMP_ERR_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_COMMON0_VIM_COMPARE_ERR_PULSE_0
109 #define SDL_ESM_MCU_R5_CCM_STAT_ERR_INT SDLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_CCM_COMPARE_STAT_PULSE_INTR_0
110 #define SDL_ESM_MAIN_MSMC_ECC_AGGR0_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_0
111 #define SDL_ESM_MAIN_MSMC_ECC_AGGR0_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_1
112 #define SDL_ESM_MAIN_MSMC_ECC_AGGR1_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_2
113 #define SDL_ESM_MAIN_MSMC_ECC_AGGR1_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_3
114 #define SDL_ESM_MAIN_MSMC_ECC_AGGR2_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_4
115 #define SDL_ESM_MAIN_MSMC_ECC_AGGR2_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_5
116 #define SDL_ESM_MAIN_A72_ECC_AGGR0_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_7
117 #define SDL_ESM_MAIN_A72_ECC_AGGR0_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_8
118 #define SDL_ESM_MAIN_A72_ECC_AGGR1_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_9
119 #define SDL_ESM_MAIN_A72_ECC_AGGR1_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_10
120 #define SDL_ESM_MAIN_A72_ECC_AGGR2_DED_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_11
121 #define SDL_ESM_MAIN_A72_ECC_AGGR2_SEC_INT SDLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_MSMC_EN_ESM_EVENTS_OUT_LEVEL_12
122 
123 #define SDL_ESM_MCU_CBASS_ECC_AGGR_SEC_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR0_CORR_LEVEL_0
124 #define SDL_ESM_MCU_CBASS_ECC_AGGR_DED_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR0_UNCORR_LEVEL_0
125 #endif /* SOC_J7200 */
126 
127 #ifdef __cplusplus
128 }
129 #endif /* extern "C" */
130 #endif /* INCLUDE_SDL_ESM_CORE_H_ */
131 
132 
sdl_esm.h
Header file contains enumerations, structure definitions and function declarations for SDL Error Sign...