Macros
#define	SDL_MCU_ESM_HI_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_MCU_ESM0_ESM_INT_HI_LVL_0

#define	SDL_MCU_ESM_LO_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_MCU_ESM0_ESM_INT_LOW_LVL_0

#define	SDL_MCU_ESM_CFG_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_MCU_ESM0_ESM_INT_CFG_LVL_0

#define	SDL_WKUP_ESM_HI_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_WKUP_ESM0_ESM_INT_HI_LVL_0

#define	SDL_WKUP_ESM_LO_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_WKUP_ESM0_ESM_INT_LOW_LVL_0

#define	SDL_WKUP_ESM_CFG_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_WKUP_ESM0_ESM_INT_CFG_LVL_0

#define	SDL_MAIN_ESM_HI_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_ESM0_ESM_INT_HI_LVL_0

#define	SDL_MAIN_ESM_LO_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_ESM0_ESM_INT_LOW_LVL_0

#define	SDL_MAIN_ESM_CFG_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_ESM0_ESM_INT_CFG_LVL_0

#define	SDL_ESM_MCU_R5_CORE0_SEC_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CORE0_ECC_CORRECTED_LEVEL_0

#define	SDL_ESM_MCU_R5_CORE0_DED_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CORE0_ECC_UNCORRECTED_LEVEL_0

#define	SDL_ESM_MCU_R5_CORE1_SEC_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CORE1_ECC_CORRECTED_LEVEL_0

#define	SDL_ESM_MCU_R5_CORE1_DED_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CORE1_ECC_UNCORRECTED_LEVEL_0

#define	SDL_ESM_MAIN_ESM_ERROR_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_GLUELOGIC_ESM_MAIN_ERR_GLUE_ERR_I_N_0

Macro Definition Documentation

◆ SDL_MCU_ESM_HI_INTNO

#define SDL_MCU_ESM_HI_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_MCU_ESM0_ESM_INT_HI_LVL_0

#define SDL_MCU_ESM_LO_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_MCU_ESM0_ESM_INT_LOW_LVL_0

#define SDL_MCU_ESM_CFG_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_MCU_ESM0_ESM_INT_CFG_LVL_0

#define SDL_WKUP_ESM_HI_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_WKUP_ESM0_ESM_INT_HI_LVL_0

#define SDL_WKUP_ESM_LO_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_WKUP_ESM0_ESM_INT_LOW_LVL_0

#define SDL_WKUP_ESM_CFG_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_WKUP_ESM0_ESM_INT_CFG_LVL_0

#define SDL_MAIN_ESM_HI_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_ESM0_ESM_INT_HI_LVL_0

#define SDL_MAIN_ESM_LO_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_ESM0_ESM_INT_LOW_LVL_0

#define SDL_MAIN_ESM_CFG_INTNO SDLR_MCU_R5FSS0_CORE0_INTR_ESM0_ESM_INT_CFG_LVL_0

#define SDL_ESM_MCU_R5_CORE0_SEC_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CORE0_ECC_CORRECTED_LEVEL_0

#define SDL_ESM_MCU_R5_CORE0_DED_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CORE0_ECC_UNCORRECTED_LEVEL_0

#define SDL_ESM_MCU_R5_CORE1_SEC_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CORE1_ECC_CORRECTED_LEVEL_0

#define SDL_ESM_MCU_R5_CORE1_DED_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_MCU_R5FSS0_CORE1_ECC_UNCORRECTED_LEVEL_0

#define SDL_ESM_MAIN_ESM_ERROR_INT SDLR_MCU_ESM0_ESM_LVL_EVENT_GLUELOGIC_ESM_MAIN_ERR_GLUE_ERR_I_N_0