sdl_ecc.h

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/*
 * SDL ECC
 *
 * Software Diagnostics Library module for ECC
 *
 *  Copyright (c) Texas Instruments Incorporated 2018-2021
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

#ifndef INCLUDE_SDL_ECC_H_
#define INCLUDE_SDL_ECC_H_

#include <stdint.h>
#include <stdbool.h>

#include "sdl_common.h"
#include <src/ip/sdl_ip_ecc.h>
#include <src/ip/sdl_esm.h>

#if defined (SOC_J721E)
#define SDL_MCU_R5F0_SUB_MEMORY     SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_RAM_ID
#endif /* SOC_J721E */

#if defined (SOC_J7200)
#define SDL_MCU_R5F0_SUB_MEMORY     SDL_MCU_R5FSS0_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_RAM_ID
#endif /* SOC_J7200 */

#ifdef __cplusplus
extern "C" {
#endif

typedef enum {
    SDL_ECC_AGGR_TYPE_INJECT_ONLY = 1,
    SDL_ECC_AGGR_TYPE_FULL_FUNCTION = 2,
} SDL_ECC_AggregatorType;


typedef enum {
    SDL_INJECT_ECC_NO_ERROR = 0,
    SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE = 1,
    SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE = 2,
    SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_ONCE = 3,
    SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_ONCE = 4,
    SDL_INJECT_ECC_ERROR_FORCING_1BIT_REPEAT = 5,
    SDL_INJECT_ECC_ERROR_FORCING_2BIT_REPEAT = 6,
    SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_REPEAT = 7,
    SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_REPEAT = 8,
} SDL_ECC_InjectErrorType;


typedef enum {
    SDL_ECC_RAM_ID_TYPE_WRAPPER = 0,
    SDL_ECC_RAM_ID_TYPE_INTERCONNECT = 1,
} SDL_ECC_RamIdType;

/* @} */

typedef uint32_t SDL_ECC_MemType;

#if defined (SOC_J721E)

    #define SDL_ECC_MEMTYPE_MCU_R5F0_CORE                               (0u)
    #define SDL_ECC_MEMTYPE_MCU_R5F1_CORE                               (1u)
    #define SDL_ECC_MEMTYPE_MCU_ADC0                                    (2u)
    #define SDL_ECC_MEMTYPE_MCU_ADC1                                    (3u)
    #define SDL_ECC_MEMTYPE_MCU_CPSW0                                   (4u)  
    #define SDL_ECC_MEMTYPE_MCU_FSS0_HPB0                               (5u) 
    #define SDL_ECC_MEMTYPE_MCU_FSS0_OSPI0                              (6u) 
    #define SDL_ECC_MEMTYPE_MCU_FSS0_OSPI1                              (7u) 
    #define SDL_ECC_MEMTYPE_MCU_MCAN0                                   (8u)
    #define SDL_ECC_MEMTYPE_MCU_MCAN1                                   (9u)
    #define SDL_ECC_MEMTYPE_MCU_MSRAM0                                  (10u)
    #define SDL_ECC_MEMTYPE_MCU_NAVSS0                                  (11u)
    #define SDL_ECC_MEMTYPE_MCU_PSRAM0                                  (12u)
    #define SDL_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0                         (13u)
    #define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR                       (14u)
    #define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR                       (15u)
    #define SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR                       (16u)
    #define SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR                       (17u)
    #define SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR                       (18u)
    #define SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR                       (19u)
    #define SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR                       (20u)
    #define SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR                       (21u)
    #define SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR                       (22u)
    #define SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR                       (23u)
    #define SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR                      (24u)
    #define SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR                      (25u)
    #define SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR                      (26u)
    #define SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR                      (27u)
    #define SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR                      (28u)
    #define SDL_PCIE0_PCIE_G4X2_CORE_AXI_ECC_AGGR                       (29u)
    #define SDL_PCIE0_PCIE_G4X2_CORE_ECC_AGGR                           (30u)
    #define SDL_PCIE1_PCIE_G4X2_CORE_AXI_ECC_AGGR                       (31u)
    #define SDL_PCIE1_PCIE_G4X2_CORE_ECC_AGGR                           (32u)
    #define SDL_PCIE2_PCIE_G4X2_CORE_AXI_ECC_AGGR                       (33u)
    #define SDL_PCIE2_PCIE_G4X2_CORE_ECC_AGGR                           (34u)
    #define SDL_PCIE3_PCIE_G4X2_CORE_AXI_ECC_AGGR                       (35u)
    #define SDL_PCIE3_PCIE_G4X2_CORE_ECC_AGGR                           (36u)
    #define SDL_I3C0_I3C_S_ECC_AGGR                                     (37u)
    #define SDL_I3C0_I3C_P_ECC_AGGR                                     (38u)
    #define SDL_MCU_I3C0_I3C_P_ECC_AGGR                                 (39u)
    #define SDL_MCU_I3C0_I3C_S_ECC_AGGR                                 (40u)
    #define SDL_MCU_I3C1_I3C_P_ECC_AGGR                                 (41u)
    #define SDL_MCU_I3C1_I3C_S_ECC_AGGR                                 (42u)
    #define SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR                    (43u)
    #define SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR                    (44u)
    #define SDL_CBASS_ECC_AGGR0_MAIN_INFRA_ECC_AGGR                     (45u)
    #define SDL_MAIN_RC_ECC_AGGR0                                       (46u)
    #define SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR       (47u)
    #define SDL_DMPAC0_ECC_AGGR                                         (48u)
    #define SDL_MAIN_HC_ECC_AGGR0                                       (49u)
    #define SDL_VPAC0_ECC_AGGR                                          (50u)
    #define SDL_VPAC0_VISS_ECC_AGGR                                     (51u)
    #define SDL_VPAC0_LDC_ECC_AGGR                                      (52u)
    #define SDL_R5FSS0_CORE0_ECC_AGGR                                   (53u)
    #define SDL_R5FSS1_CORE0_ECC_AGGR                                   (54u)
    #define SDL_R5FSS0_CORE1_ECC_AGGR                                   (55u)
    #define SDL_R5FSS1_CORE1_ECC_AGGR                                   (56u)
    #define SDL_NAVSS_VIRTSS_ECC_AGGR0                                  (57u)
    #define SDL_CPSW0_CPSW_9XUSS_CORE_ECC_CPSW_ECC_AGGR                 (58u) 
    #define SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR                      (59u)
    #define SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR                          (60u)
    #define SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR                      (61u)
    #define SDL_MAIN_AC_ECC_AGGR0                                       (62u)
    #define SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR                              (63u)
    #define SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM                          (64u)
    #define SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM                          (65u)
    #define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM                         (66u)
    #define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM                         (67u)
    #define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM                         (68u)
    #define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM                         (69u)
    #define SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE        (70u)
    #define SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY         (71u)
    #define SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC         (72u)
    #define SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR                         (73u)
    #define SDL_CSI_RX_IF0_ECC_AGGR_0                                   (74u)
    #define SDL_CSI_RX_IF1_ECC_AGGR_0                                   (75u)
    #define SDL_NAVSS0_MODSS_ECC_AGGR0                                  (76u)
    #define SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR                 (77u)
    #define SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR                 (78u)
    #define SDL_NAVSS0_VIRTSS_ECC_AGGR0                                 (79u)
    #define SDL_NAVSS0_NBSS_ECC_AGGR0                                   (80u)
    #define SDL_IDOM1_ECC_AGGR0                                         (81u)
    #define SDL_IDOM1_ECC_AGGR1                                         (82u)
    #define SDL_WKUP_DMSC0_ECC_AGGR                                     (83u) 
    #define SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR                          (84u)
    #define SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR                          (85u)
    #define SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR                           (86u)
    #define SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE                      (87u)
    #define SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR                    (88u)
    #define SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS                    (89u)
    #define SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0                             (90u)
    #define SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR                            (91u)
    #define SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR                        (92u)
    #define SDL_NAVSS0_UDMASS_ECC_AGGR0                                 (93u)

    #define SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR0                             (94u)
    #define SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR1                             (95u)
    #define SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR2                             (96u)
    #define SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR                 (97u)
    #define SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR                  (98u)
    #define SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR                  (99u)
    #define SDL_COMPUTE_CLUSTER0_DDR32SSC_EW_BRCTL_SC_ECC_AGGR_VBUS     (100u)
    #define SDL_COMPUTE_CLUSTER0_DDR32SSC_EW_BRCTL_SC_ECC_AGGR_CTL      (101u)
    #define SDL_COMPUTE_CLUSTER0_DDR32SSC_EW_BRCTL_SC_ECC_AGGR_CFG      (102u)
    #define SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR                        (103u)
    #define SDL_COMPUTE_CLUSTER0_GIC_ECC_AGGR                           (104u)

#define SDL_ECC_MEMTYPE_MAX (SDL_COMPUTE_CLUSTER0_GIC_ECC_AGGR + 1U)

/* Max entries based on max mem type */
#define SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES    (SDL_NAVSS0_UDMASS_ECC_AGGR0+1U)

#define SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES (SDL_COMPUTE_CLUSTER0_GIC_ECC_AGGR - \
                                           SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR0 + 1u)

#endif

#if defined (SOC_J7200)

#define SDL_ECC_MEMTYPE_MCU_R5F0_CORE                                   (0u)
#define SDL_ECC_MEMTYPE_MCU_R5F1_CORE                                   (1u)
#define SDL_ECC_PDMA10_ECC_AGGR                                         (2u)
#define SDL_ECC_PCIE1_1_ECC_AGGR                                        (3u)
#define SDL_ECC_MCU_NAVSS0_0_ECC_AGGR                                   (4u)
#define SDL_ECC_MCU_NAVSS0_1_ECC_AGGR                                   (5u)
#define SDL_ECC_PCIE1_0_ECC_AGGR                                        (6u)
#define SDL_ECC_USB0_ECC_AGGR                                           (7u)
#define SDL_ECC_CPSW0_ECC_AGGR                                          (8u)
#define SDL_ECC_MMCSD0_1_ECC_AGGR                                       (9u)
#define SDL_ECC_MMCSD0_0_ECC_AGGR                                       (10u)
#define SDL_ECC_MMCSD1_0_ECC_AGGR                                       (11u)
#define SDL_ECC_MMCSD1_1_ECC_AGGR                                       (12u)
#define SDL_ECC_MSRAM_512K0_ECC_AGGR                                    (13u)
#define SDL_ECC_MCAN8_ECC_AGGR                                          (14u)
#define SDL_ECC_MCAN9_ECC_AGGR                                          (15u)
#define SDL_ECC_MCAN10_ECC_AGGR                                         (16u)
#define SDL_ECC_MCAN11_ECC_AGGR                                         (17u)
#define SDL_ECC_MCAN12_ECC_AGGR                                         (18u)
#define SDL_ECC_MCAN13_ECC_AGGR                                         (19u)
#define SDL_ECC_MCAN14_ECC_AGGR                                         (20u)
#define SDL_ECC_MCAN15_ECC_AGGR                                         (21u)
#define SDL_ECC_MCAN16_ECC_AGGR                                         (22u)
#define SDL_ECC_MCAN17_ECC_AGGR                                         (23u)
#define SDL_R5FSS0_CORE0_ECC_AGGR                                       (24u)  /* SDL_ECC_R5FSS0_0_ECC_AGGR */
#define SDL_ECC_I3C0_1_ECC_AGGR                                         (25u)
#define SDL_ECC_I3C0_0_ECC_AGGR                                         (26u)
#define SDL_ECC_MCAN0_ECC_AGGR                                          (27u)
#define SDL_ECC_MCAN1_ECC_AGGR                                          (28u)
#define SDL_ECC_MCAN2_ECC_AGGR                                          (29u)
#define SDL_ECC_MCAN3_ECC_AGGR                                          (30u)
#define SDL_ECC_MCAN4_ECC_AGGR                                          (31u)
#define SDL_ECC_MCAN5_ECC_AGGR                                          (32u)
#define SDL_ECC_MCAN6_ECC_AGGR                                          (33u)
#define SDL_ECC_MCAN7_ECC_AGGR                                          (34u)
#define SDL_ECC_IDOM0_ECC_AGGR16                                        (35u)
#define SDL_ECC_IDOM1_ECC_AGGR17                                        (36u)
#define SDL_ECC_VC_MAIN_RC_ECC_AGGR4_ECC_AGGR                           (37u)
#define SDL_ECC_VC_MAIN_HC_ECC_AGGR5_ECC_AGGR                           (38u)
#define SDL_ECC_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6                          (39u)
#define SDL_ECC_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_ECC_AGGR            (40u)
#define SDL_ECC_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_ECC_AGGR               (41u)
#define SDL_ECC_NAVSS0_0_ECC_AGGR                                       (42u)
#define SDL_ECC_NAVSS0_1_ECC_AGGR                                       (43u)
#define SDL_ECC_NAVSS0_3_ECC_AGGR                                       (44u)
#define SDL_ECC_NAVSS0_2_ECC_AGGR                                       (45u)
#define SDL_ECC_PDMA5_ECC_AGGR                                          (46u)
#define SDL_ECC_PDMA9_ECC_AGGR                                          (47u)
#define SDL_ECC_MCU_MCAN0_ECC_AGGR                                      (48u)
#define SDL_ECC_MCU_MCAN1_ECC_AGGR                                      (49u)
#define SDL_ECC_MCU_ADC0_ECC_AGGR                                       (50u)
#define SDL_ECC_MCU_ADC1_ECC_AGGR                                       (51u)
#define SDL_ECC_MCU_CPSW0_ECC_AGGR                                      (52u)
#define SDL_ECC_MCU_MSRAM_1MB0_ECC_AGGR                                 (53u)
#define SDL_ECC_MCU_SA2_UL0_ECC_AGGR                                    (54u)
#define SDL_ECC_MCU_I3C0_1_ECC_AGGR                                     (55u)
#define SDL_ECC_MCU_I3C0_0_ECC_AGGR                                     (56u)
#define SDL_ECC_MCU_I3C1_1_ECC_AGGR                                     (57u)
#define SDL_ECC_MCU_I3C1_0_ECC_AGGR                                     (58u)
#define SDL_ECC_WKUP_VTM0_ECC_AGGR                                      (59u)
#define SDL_ECC_MCU_FSS0_0_ECC_AGGR                                     (60u)
#define SDL_ECC_MCU_FSS0_1_ECC_AGGR                                     (61u)
#define SDL_ECC_MCU_VC_MCU_ECC_AGGR0                                    (62u)  
#define SDL_R5FSS0_CORE1_ECC_AGGR                                       (63u)  /* SDL_ECC_R5FSS0_1_ECC_AGGR */
#define SDL_ECC_PSRAMECC0_ECC_AGGR                                      (64u)
#define SDL_ECC_PSRAM2KECC0_ECC_AGGR                                    (65u)
#define SDL_ECC_VCL_MAIN_INFRA_ECC_AGGR0_0_ECC_AGGR                     (66u)

#define SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR0                                 (67u)  /* SDL_ECC_COMPUTE_CLUSTER0_3_ECC_AGGR */
#define SDL_ECC_COMPUTE_CLUSTER0_2_ECC_AGGR                             (68u)
#define SDL_ECC_COMPUTE_CLUSTER0_4_ECC_AGGR                             (69u)
#define SDL_ECC_COMPUTE_CLUSTER0_5_ECC_AGGR                             (70u)
#define SDL_ECC_COMPUTE_CLUSTER0_1_ECC_AGGR                             (71u)
#define SDL_ECC_COMPUTE_CLUSTER0_0_ECC_AGGR                             (72u)
#define SDL_DDR0_0_ECC_AGGR                                             (73u)
#define SDL_DDR0_1_ECC_AGGR                                             (74u)
#define SDL_DDR0_2_ECC_AGGR                                             (75u)
#define SDL_ECC_COMPUTE_CLUSTER0_6_ECC_AGGR                             (76u)


#define SDL_ECC_MEMTYPE_MAX (SDL_ECC_COMPUTE_CLUSTER0_6_ECC_AGGR + 1U)


/* Max entries based on max mem type */
#define SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES    (SDL_ECC_VCL_MAIN_INFRA_ECC_AGGR0_0_ECC_AGGR+1U)

#define SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES (SDL_ECC_COMPUTE_CLUSTER0_6_ECC_AGGR - \
                                           SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR0 + 1u)

#endif

typedef uint32_t SDL_ECC_MemSubType;

#if defined (SOC_J721E)

/* The following are the memory sub type for Memory type
   SDL_ECC_MEMTYPE_MCU_R5F0_CORE & SDL_ECC_MEMTYPE_MCU_R5F1_CORE */
/* Keeping for backward-compatibility. Recommend to use RAM_ID directly from sdlr_soc_ecc_aggr.h file */

#define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK0_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID)

#define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK1_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID)

#define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK0_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID)

#define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK1_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID)

#define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK0_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID)

#define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK1_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID)

#define SDL_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID)

#endif

#if defined (SOC_J7200)

/* The following are the memory sub type for Memory type
   SDL_ECC_MEMTYPE_MCU_R5F0_CORE & SDL_ECC_MEMTYPE_MCU_R5F1_CORE */
/* Keeping for backward-compatibility. Recommend to use RAM_ID directly from sdlr_soc_ecc_aggr.h file */

#define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK0_VECTOR_ID (SDL_MCU_R5FSS0_PULSAR_SL_ATCM0_BANK0_RAM_ID)

#define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK1_VECTOR_ID (SDL_MCU_R5FSS0_PULSAR_SL_ATCM0_BANK1_RAM_ID)

#define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK0_VECTOR_ID (SDL_MCU_R5FSS0_PULSAR_SL_B0TCM0_BANK0_RAM_ID)

#define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK1_VECTOR_ID (SDL_MCU_R5FSS0_PULSAR_SL_B0TCM0_BANK1_RAM_ID)

#define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK0_VECTOR_ID (SDL_MCU_R5FSS0_PULSAR_SL_B1TCM0_BANK0_RAM_ID)

#define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK1_VECTOR_ID (SDL_MCU_R5FSS0_PULSAR_SL_B1TCM0_BANK1_RAM_ID)

#define SDL_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID (SDL_MCU_R5FSS0_CPU0_KS_VIM_RAMECC_RAM_ID)

#endif

typedef void (*SDL_ECC_ErrorCallback_t) (uint32_t errorSrc, uint32_t address);

typedef void (*SDL_ECC_VIMDEDVector_t) (void);

/* @} */

typedef struct SDL_ECC_InitConfig_s
{
    uint32_t numRams;
    SDL_ECC_MemSubType *pMemSubTypeList;
} SDL_ECC_InitConfig_t;

typedef struct SDL_ECC_InjectErrorConfig_s
{
    uint32_t *pErrMem;
    uint32_t flipBitMask;
    uint32_t chkGrp;
}  SDL_ECC_InjectErrorConfig_t;

typedef struct SDL_ECC_ErrorInfo_s
{
    SDL_ECC_MemType eccMemType;
    SDL_ECC_MemSubType memSubType;
    SDL_Ecc_AggrIntrSrc intrSrc;
    uint32_t bitErrCnt;
    uint32_t injectBitErrCnt;
    uint32_t bitErrorGroup;
    uint64_t bitErrorOffset;
} SDL_ECC_ErrorInfo_t;

/* @} */

int32_t SDL_ECC_initEsm (const SDL_ESM_Inst esmInstType);

int32_t SDL_ECC_init (SDL_ECC_MemType eccMemType,
                        const SDL_ECC_InitConfig_t *pECCInitConfig);

int32_t SDL_ECC_initMemory (SDL_ECC_MemType eccMemType,
                               SDL_ECC_MemSubType memSubType);

int32_t SDL_ECC_selfTest(SDL_ECC_MemType eccMemType,
                            SDL_ECC_MemSubType memSubType,
                            SDL_ECC_InjectErrorType errorType,
                            const SDL_ECC_InjectErrorConfig_t *pECCErrorConfig,
                            uint32_t selfTestTimeOut);

int32_t SDL_ECC_injectError(SDL_ECC_MemType eccMemType,
                               SDL_ECC_MemSubType memSubType,
                               SDL_ECC_InjectErrorType errorType,
                               const SDL_ECC_InjectErrorConfig_t *pECCErrorConfig);

int32_t SDL_ECC_getStaticRegisters(SDL_ECC_MemType eccMemType,
                                   SDL_ECC_staticRegs *pStaticRegs);

int32_t SDL_ECC_getErrorInfo(SDL_ECC_MemType eccMemType,
                                SDL_Ecc_AggrIntrSrc intrSrc,
                                SDL_ECC_ErrorInfo_t *pErrorInfo);

int32_t SDL_ECC_ackIntr(SDL_ECC_MemType eccMemType,
                        SDL_Ecc_AggrIntrSrc intrSrc);

int32_t SDL_ECC_getESMErrorInfo(SDL_ESM_Inst instance, uint32_t intSrc,
                                SDL_ECC_MemType *eccMemType, SDL_Ecc_AggrIntrSrc *intrSrcType);

int32_t SDL_ECC_clearNIntrPending(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType,
                                  SDL_Ecc_AggrIntrSrc intrSrc,
                                  SDL_Ecc_AggrEDCErrorSubType subType, uint32_t numEvents);

void SDL_ECC_registerVIMDEDHandler(SDL_ECC_VIMDEDVector_t VIMDEDHandler);

void SDL_ECC_applicationCallbackFunction(SDL_ECC_MemType eccMemType,
                                         uint32_t errorSrc,
                                         uint32_t address,
                                         uint32_t ramId,
                                         uint64_t bitErrorOffset,
                                         uint32_t bitErrorGroup);

/* @} */

#ifdef __cplusplus
}
#endif  /* extern "C" */

#endif /* INCLUDE_SDL_ECC_H_ */