SDL API Guide for J7200
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POK types | |
This enumerator defines the possible POK module types | |
typedef uint8_t | SDL_pok_type |
#define | SDL_TYPE_POK ((SDL_pok_type) 1U) |
#define | SDL_TYPE_POK_SA ((SDL_pok_type) 2U) |
POK/POR Deglitch types | |
This enumerator defines the possible ping-pong control values for the Power Subsystem modules | |
typedef uint8_t | SDL_pwrss_deglitch |
#define | SDL_PWRSS_DEGLITCH_5US ((SDL_pwrss_deglitch) 0U) |
#define | SDL_PWRSS_DEGLITCH_10US ((SDL_pwrss_deglitch) 1U) |
#define | SDL_PWRSS_DEGLITCH_15US ((SDL_pwrss_deglitch) 2U) |
#define | SDL_PWRSS_DEGLITCH_20US ((SDL_pwrss_deglitch) 3U) |
#define | SDL_PWRSS_DEGLITCH_GET_VALUE ((SDL_pwrss_deglitch) 4U) |
#define | SDL_PWRSS_DEGLITCH_NO_ACTION ((SDL_pwrss_deglitch) 5U) |
POK/POR Ping/Pong types | |
This enumerator defines the possible deglitch control values for the Power Subsystem modules | |
typedef uint8_t | SDL_pwrss_pp |
#define | SDL_PWRSS_PP_MODE_DISABLE ((SDL_pwrss_pp) 0U) |
#define | SDL_PWRSS_PP_MODE_ENABLE ((SDL_pwrss_pp) 1U) |
#define | SDL_PWRSS_PP_MODE_NO_ACTION ((SDL_pwrss_pp) 2U) |
POK/POR hysteresIs types | |
This enumerator defines the possible hysteresis control values for the Power Subsystem modules | |
typedef uint8_t | SDL_pwrss_hysteresis |
#define | SDL_PWRSS_SET_HYSTERESIS_DISABLE ((SDL_pwrss_hysteresis) 0U) |
#define | SDL_PWRSS_SET_HYSTERESIS_ENABLE ((SDL_pwrss_hysteresis) 1U) |
#define | SDL_PWRSS_GET_HYSTERESIS_VALUE ((SDL_pwrss_hysteresis) 2U) |
#define | SDL_PWRSS_HYSTERESIS_NO_ACTION ((SDL_pwrss_hysteresis) 3U) |
POK/POR TRIM values | |
This enumerator defines the possible trim value for POK/POR modules Any value between 0 through 127 is valid TRIM value ------------------------------------------------------------------------— * * POK | Under Voltage | Over Voltage | * | Detection | Detection | Step Resolution * ----------- | --------------- | ---------------- | ---------------- * CORE_POK | 475mV - 1.35V | 725mV - 1.65V | 0.0125V * POK1.8 | 1.432V - 2.168V | 1.432V - 2.168V | 0.02V * POK3.3 | 2.625V - 3.975V | 2.625V - 3.975V | 0.0375V * * | |
typedef uint8_t | SDL_pwrss_trim |
#define | SDL_PWRSS_MAX_TRIM_VALUE ((SDL_pwrss_trim) 127U) |
#define | SDL_PWRSS_TRIM_NO_ACTION ((SDL_pwrss_trim) 128U) |
#define | SDL_PWRSS_GET_TRIM_VALUE ((SDL_pwrss_trim) 129U) |
#define | SDL_PWRSS_INVALID_TRIM_VALUE ((SDL_pwrss_trim) 255U) |
POK/POR Voltage detection modes | |
This enumerator defines the possible values of Voltage Detection modes | |
typedef uint8_t | SDL_pwrss_vd_mode |
#define | SDL_PWRSS_SET_UNDER_VOLTAGE_DET_ENABLE ((SDL_pwrss_vd_mode) 0U) |
#define | SDL_PWRSS_SET_OVER_VOLTAGE_DET_ENABLE ((SDL_pwrss_vd_mode) 1U) |
#define | SDL_PWRSS_SET_PP_VOLTAGE_DET_ENABLE ((SDL_pwrss_vd_mode) 2U) |
#define | SDL_PWRSS_GET_VOLTAGE_DET_MODE ((SDL_pwrss_vd_mode) 3U) |
#define | SDL_PWRSS_VOLTAGE_DET_NO_ACTION ((SDL_pwrss_vd_mode) 4U) |
POK detection status | |
This enumerator defines the POK Detection status values | |
typedef uint8_t | SDL_POK_detection_status |
#define | SDL_POK_DETECTION_DISABLED ((SDL_POK_detection_status) 0U) |
#define | SDL_POK_DETECTION_ENABLED ((SDL_POK_detection_status) 1U) |
POK detection values | |
This enumerator defines the POK Detection values | |
typedef uint8_t | SDL_POK_detection |
#define | SDL_POK_DETECTION_DISABLE ((SDL_POK_detection) 0U) |
#define | SDL_POK_DETECTION_ENABLE ((SDL_POK_detection) 1U) |
#define | SDL_POK_DETECTION_NO_ACTION ((SDL_POK_detection) 2U) |
#define | SDL_POK_GET_DETECTION_VALUE ((SDL_POK_detection) 3U) |
POK Enable Selection source Values | |
This enumerator defines the POK Enable selection source | |
typedef uint8_t | SDL_POK_enSelSrc |
#define | SDL_POK_ENSEL_HWTIEOFFS ((SDL_POK_enSelSrc) 0U) |
#define | SDL_POK_ENSEL_PRG_CTRL ((SDL_POK_enSelSrc) 1U) |
#define | SDL_POK_ENSEL_NO_ACTION ((SDL_POK_enSelSrc) 2U) |
#define | SDL_POK_GET_ENSEL_VALUE ((SDL_POK_enSelSrc) 3U) |
POK trim selection values from HHV default or CTRL registers | |
This enumerator defines the trim selection values | |
typedef uint8_t | SDL_por_trim_sel |
#define | SDL_POR_TRIM_SELECTION_FROM_HHV_DEFAULT ((uint8_t) 0U) |
#define | SDL_POR_TRIM_SELECTION_FROM_CTRL_REGS ((uint8_t) 1U) |
#define | SDL_POR_TRIM_SELECTION_NO_CHANGE ((uint8_t) 2U) |
#define | SDL_POR_TRIM_SELECTION_GET_VALUE ((uint8_t) 3U) |
POR Module state values | |
This enumerator defines the POR Module State | |
typedef uint8_t | SDL_por_module_status |
#define | SDL_POR_MODULE_STATUS_FUNCTIONAL_MODE ((SDL_por_module_status) 0U) |
#define | SDL_POR_MODULE_STATUS_RESET_MODE ((SDL_por_module_status) 1U) |
POK POK ID values | |
This enumerator defines the Wake up control MMR register | |
typedef SDL_wkup_ctrl_mmr_cfg0Regs | SDL_wkupCtrlRegsBase_t |
#define SDL_TYPE_POK ((SDL_pok_type) 1U) |
POK type Power System Module
#define SDL_TYPE_POK_SA ((SDL_pok_type) 2U) |
POK_SA type Power System Module
#define SDL_PWRSS_DEGLITCH_5US ((SDL_pwrss_deglitch) 0U) |
Deglitch period 5us
#define SDL_PWRSS_DEGLITCH_10US ((SDL_pwrss_deglitch) 1U) |
Deglitch period 10us
#define SDL_PWRSS_DEGLITCH_15US ((SDL_pwrss_deglitch) 2U) |
Deglitch period 15us
#define SDL_PWRSS_DEGLITCH_20US ((SDL_pwrss_deglitch) 3U) |
Deglitch period 20us
#define SDL_PWRSS_DEGLITCH_GET_VALUE ((SDL_pwrss_deglitch) 4U) |
Get the Deglitch value
#define SDL_PWRSS_DEGLITCH_NO_ACTION ((SDL_pwrss_deglitch) 5U) |
No update on hysteresis for the module
#define SDL_PWRSS_PP_MODE_DISABLE ((SDL_pwrss_pp) 0U) |
Ping Pong Disable
#define SDL_PWRSS_PP_MODE_ENABLE ((SDL_pwrss_pp) 1U) |
Ping Pong Enable
#define SDL_PWRSS_PP_MODE_NO_ACTION ((SDL_pwrss_pp) 2U) |
No update on ping pong for the module
#define SDL_PWRSS_SET_HYSTERESIS_DISABLE ((SDL_pwrss_hysteresis) 0U) |
Disable hysteresis for the module
#define SDL_PWRSS_SET_HYSTERESIS_ENABLE ((SDL_pwrss_hysteresis) 1U) |
Enable hysteresis for the module
#define SDL_PWRSS_GET_HYSTERESIS_VALUE ((SDL_pwrss_hysteresis) 2U) |
Get hysteresis value for the module
#define SDL_PWRSS_HYSTERESIS_NO_ACTION ((SDL_pwrss_hysteresis) 3U) |
No update on hysteresis for the module
#define SDL_PWRSS_MAX_TRIM_VALUE ((SDL_pwrss_trim) 127U) |
TRIM is 7 bit value, when the trim value is <= to the MAX value, that value would be written to trim register Any other values, would be treated as the command as described belowTRIM is 7 bit value, and hence the maximum value is 127
#define SDL_PWRSS_TRIM_NO_ACTION ((SDL_pwrss_trim) 128U) |
No update on trim value read/write for the module
#define SDL_PWRSS_GET_TRIM_VALUE ((SDL_pwrss_trim) 129U) |
Command to read the TRIM value
#define SDL_PWRSS_INVALID_TRIM_VALUE ((SDL_pwrss_trim) 255U) |
Invalid TRIM value
#define SDL_PWRSS_SET_UNDER_VOLTAGE_DET_ENABLE ((SDL_pwrss_vd_mode) 0U) |
Enable under voltage detection for the module
#define SDL_PWRSS_SET_OVER_VOLTAGE_DET_ENABLE ((SDL_pwrss_vd_mode) 1U) |
Enable over voltage detection for the module
#define SDL_PWRSS_SET_PP_VOLTAGE_DET_ENABLE ((SDL_pwrss_vd_mode) 2U) |
Enable ping-pong voltage detection for the module
#define SDL_PWRSS_GET_VOLTAGE_DET_MODE ((SDL_pwrss_vd_mode) 3U) |
Get voltage detection for the module
#define SDL_PWRSS_VOLTAGE_DET_NO_ACTION ((SDL_pwrss_vd_mode) 4U) |
No update on voltage detection mode update for the module
#define SDL_POK_DETECTION_DISABLED ((SDL_POK_detection_status) 0U) |
POK Detection disabled
#define SDL_POK_DETECTION_ENABLED ((SDL_POK_detection_status) 1U) |
POK Detection Enabled
#define SDL_POK_DETECTION_DISABLE ((SDL_POK_detection) 0U) |
POK Detection disabled
#define SDL_POK_DETECTION_ENABLE ((SDL_POK_detection) 1U) |
POK Detection Enabled
#define SDL_POK_DETECTION_NO_ACTION ((SDL_POK_detection) 2U) |
POK Detection No action
#define SDL_POK_GET_DETECTION_VALUE ((SDL_POK_detection) 3U) |
POK Detection get value
#define SDL_POK_ENSEL_HWTIEOFFS ((SDL_POK_enSelSrc) 0U) |
POK enables come from hardware tie offs
#define SDL_POK_ENSEL_PRG_CTRL ((SDL_POK_enSelSrc) 1U) |
POK enables come from CTRLMMR_WKUP_PRG0_CTRL register
#define SDL_POK_ENSEL_NO_ACTION ((SDL_POK_enSelSrc) 2U) |
POK enable selection no action
#define SDL_POK_GET_ENSEL_VALUE ((SDL_POK_enSelSrc) 3U) |
POK enable selection Get value
#define SDL_POR_TRIM_SELECTION_FROM_HHV_DEFAULT ((uint8_t) 0U) |
Trim selections for Bandgap and PORs come from HHV defaults
#define SDL_POR_TRIM_SELECTION_FROM_CTRL_REGS ((uint8_t) 1U) |
Trim selections for Bandgap and POKs come from CTRLMMR_WKUP_POR_BANDGAP_CTRL and POR_POKxxx_CTRL registers
#define SDL_POR_TRIM_SELECTION_NO_CHANGE ((uint8_t) 2U) |
Trim selections for Bandgap and POKs No Change
#define SDL_POR_TRIM_SELECTION_GET_VALUE ((uint8_t) 3U) |
Trim Read selections Bandgap and POKs
#define SDL_POR_MODULE_STATUS_FUNCTIONAL_MODE ((SDL_por_module_status) 0U) |
POR in functional mode
#define SDL_POR_MODULE_STATUS_RESET_MODE ((SDL_por_module_status) 1U) |
POR in Reset mode
typedef uint8_t SDL_pok_type |
typedef uint8_t SDL_pwrss_deglitch |
typedef uint8_t SDL_pwrss_pp |
typedef uint8_t SDL_pwrss_hysteresis |
typedef uint8_t SDL_pwrss_trim |
typedef uint8_t SDL_pwrss_vd_mode |
typedef uint8_t SDL_POK_detection_status |
typedef uint8_t SDL_POK_detection |
typedef uint8_t SDL_POK_enSelSrc |
typedef uint8_t SDL_por_trim_sel |
typedef uint8_t SDL_por_module_status |
typedef SDL_wkup_ctrl_mmr_cfg0Regs SDL_wkupCtrlRegsBase_t |