3.2.2.17. SERDES¶
3.2.2.17.1. Introduction¶
SERDES converts device (SoC) parallel data into serialized data that can be output over a high-speed electrical interface. In the opposite direction, SerDes converts high-speed serial data into parallel data that can be processed by the device.
SERDES is used for transmitting/receiving data for PCIe, USB3, CPSW (QSGMII, SGMII, USXGMII, XFI), eDP in K3 SoC.
Note
The following documentation describes the different PHY types (data rates) supported by the SERDES. While the SERDES might support a given protocol, it does not imply that the peripheral is capable of utilizing it. Please refer to the Technical Reference Manual for verifying hardware support for the peripheral. Refer to the peripheral driver documentation for verifying software support for the peripheral.
3.2.2.17.2. Types of SERDES¶
- There are two types of SERDES present in J721E:
2 Lane SERDES
4 Lane SERDES
2 Lane Serdes
┌───────────────────┐
│ │
│ │
<-> Peripheral IP1│ │ <-> RX0/TX0
──────────────────┤ ├────────────────
│ │
│ │
│ │
│ 2L SERDES │
│ │
│ │
│ │
<-> Peripheral IP2│ │ <-> RX1/TX1
──────────────────┤ ├────────────────
│ │
│ │
│ │
└───────────────────┘
4 Lane Serdes
┌───────────────────┐
<-> Peripheral IP1│ │ <-> RX0/TX0
──────────────────┤ ├────────────────
│ │
│ │
<-> Peripheral IP2│ │ <-> RX1/TX1
──────────────────┤ ├────────────────
│ │
│ 4L SERDES │
<-> Peripheral IP3│ │ <-> RX2/TX2
──────────────────┤ ├────────────────
│ │
│ │
<-> Peripheral IP4│ │ <-> RX3/TX3
──────────────────┤ ├────────────────
│ │
│ │
└───────────────────┘
3.2.2.17.3. SERDES Configurations¶
This section lists the set of PHY types (data rates) that the SERDES can be configured in, from the perspective of the SERDES driver and SERDES hardware support. To enable the desired configuration, the SoC device-tree has to be modified based on the instructions mentioned in the SERDES Muxing section.
A single SERDES can support either one protocol (connects to one Peripheral IP) or two protocols (connects to multiple Peripheral IP) at the same time.
If a SERDES supports one protocol, it’s called a single link PHY and if a SERDES supports two protocols, it’s called multi-link PHY. Note that a single link PHY can comprise multiple lanes. For a multi-link PHY, the lanes can be split up in different ways but the only constraint is that the SERDES can support up to two protocols simultaneously.
It’s also not always necessary to use all the lanes of a SERDES and some lanes can be left unused.
Supported 2 Lane Serdes Configurations
The 2 Lane SERDES instances in J721E SoC are configured by the Sierra Serdes kernel driver:
drivers/phy/cadence/phy-cadence-sierra.c
The possible Peripheral IP configurations that can be configured on the 2 Lane SERDES are:
Single Protocol Configurations:
PCIe
USB
Multi Protocol Configurations:
PCIe + QSGMII
PCIe + SGMII
Supported 4 Lane Serdes Configurations
The 4 Lane SERDES instances in J721E SoC are configured by the Torrent Serdes kernel driver:
drivers/phy/cadence/phy-cadence-torrent.c
The possible Peripheral IP configurations that can be configured on the 4 Lane SERDES are:
Single Protocol Configurations:
EDP
PCIe
QSGMII
SGMII
USB
USXGMII
Multi Protocol Configurations:
EDP + PCIe
EDP + USB
PCIe + QSGMII
PCIe + SGMII
PCIe + USB
PCIe + USXGMII
QSGMII + USB
QSGMII + USXGMII
SGMII + USB
SGMII + USXGMII
3.2.2.17.4. SERDES Instances¶
J721E SoC has four instances of the 2 Lane SERDES and one instance of the 4 Lane Serdes.
3.2.2.17.5. SERDES Muxing¶
SERDES Muxing refers to the process of selecting the mapping between the Peripheral Lanes and the SERDES Lanes. A valid mapping refers to the process of selecting a valid combination of Peripheral Lane and SERDES Lane based on the physical connections available to choose from. Listed below is the valid set of combinations for the SERDES instances.
SERDES 0
┌───────────────────┐
CPSW0_Q/SGMII_LANE1/│ │
PCIE0_LANE0/│ │
USB3_0_SWAP │ │ <-> RX0/TX0
──────────────────┤ ├────────────────
│ │
│ 2L SERDES │
CPSW0_Q/SGMII_LANE2/│ │
PCIE0_LANE1/│ │
USB3_0 │ │ <-> RX1/TX1
──────────────────┤ ├────────────────
│ │
│ │
└───────────────────┘
SERDES 1
┌───────────────────┐
CPSW0_Q/SGMII_LANE3/│ │
PCIE1_LANE0/│ │
USB3_1_SWAP/│ │
ICSSG1_SGMII_LANE0 │ │ <-> RX0/TX0
──────────────────┤ ├────────────────
│ │
│ 2L SERDES │
CPSW0_Q/SGMII_LANE4/│ │
PCIE1_LANE1/│ │
USB3_1/│ │
ICSSG1_SGMII_LANE1 │ │ <-> RX1/TX1
──────────────────┤ ├────────────────
│ │
│ │
└───────────────────┘
SERDES 2
┌───────────────────┐
PCIE2_LANE0/│ │
USB3_1_SWAP/│ │
ICSSG1_SGMII_LANE0 │ │ <-> RX0/TX0
──────────────────┤ ├────────────────
│ │
│ 2L SERDES │
PCIE2_LANE1/│ │
USB3_1/│ │
ICSSG1_SGMII_LANE1 │ │ <-> RX1/TX1
──────────────────┤ ├────────────────
│ │
│ │
└───────────────────┘
SERDES 3
┌───────────────────┐
PCIE3_LANE0/│ │
USB3_0_SWAP │ │ <-> RX0/TX0
──────────────────┤ ├────────────────
│ │
│ 2L SERDES │
PCIE3_LANE1/│ │
USB3_0 │ │ <-> RX1/TX1
──────────────────┤ ├────────────────
│ │
│ │
└───────────────────┘
SERDES 4
┌───────────────────┐
EDP_LANE0/│ │
CPSW0_Q/SGMII_LANE5 │ │ <-> RX0/TX0
──────────────────┤ ├────────────────
│ │
│ │
EDP_LANE1/│ │
CPSW0_Q/SGMII_LANE6 │ │ <-> RX1/TX1
──────────────────┤ ├────────────────
│ │
│ 4L SERDES │
EDP_LANE2/│ │
CPSW0_Q/SGMII_LANE7 │ │ <-> RX2/TX2
──────────────────┤ ├────────────────
│ │
│ │
EDP_LANE3/│ │
CPSW0_Q/SGMII_LANE8 │ │ <-> RX3/TX3
──────────────────┤ ├────────────────
│ │
└───────────────────┘
The Muxing configuration for each of the SERDES lanes can be described using device tree. The device tree node labelled serdes_ln_ctrl corresponds to the mux used to configure each of the SERDES lanes. The property “idle-states” inside the serdes_ln_ctrl mux is used to specify the mapping between the SERDES lane and the IP lane.
A valid mapping can be determined by referring to the SERDES muxing section above. To select a mapping, the following format has to be used:
<SoC_SERDESw_LANEx_IPa_LANEb>
where:
SoC is the name of the SoC,
‘w’ specifies the SERDES instance: SERDES0 for example,
‘x’ specifies the SERDES Lane: LANE0 for example,
IP specifies the peripheral IP: PCIE for example,
‘a’ specifies the instance of that peripheral IP: PCIE0 for example,
‘b’ specifies the peripheral IP’s Lane: LANE0 for example.
The mapping is interpret as follows:
For the SoC named: SoC, SERDESw LANEx should be mapped to IPa LANEb.
For unused Serdes lanes, indicate them using:
<SoC_SERDESw_LANEx_IPa_UNUSED>
Serdes Muxing Example
Consider an SoC named SoCX with one 1L SERDES, one 2L SERDES and one 4L SERDES, with the instances being SERDES0, SERDES1 and SERDES2. Additionally, let the SoC have PCIe instance PCIE1, EDP instance EDP0 and a CPSW instance using QSGMII.
Then, to configure:
SERDES0 Lane0 for PCIE1 Lane0
SERDES1 Lane0 for EDP0 Lane2
SERDES1 Lane1 for EDP0 Lane3
SERDES2 Lane0 for QSGMII Lane3
SERDES2 Lane1 for QSGMII Lane4
SERDES2 Lane2 for QSGMII Lane1
SERDES2 Lane3 for QSGMII Lane2
the device tree serdes_ln_ctrl node has to be defined as follows:
&serdes_ln_ctrl {
idle-states = <SoCX_SERDES0_LANE0_PCIE1_LANE0>, <SoCX_SERDES1_LANE0_EDP0_LANE2>,
<SoCX_SERDES1_LANE1_EDP0_LANE3>, <SoCX_SERDES2_LANE0_QSGMII_LANE3>,
<SoCX_SERDES2_LANE1_QSGMII_LANE4>, <SoCX_SERDES2_LANE2_QSGMII_LANE1>
<SoCX_SERDES2_LANE3_QSGMII_LANE2>;
};
Default Device Tree Muxing
The J721E common processor board file k3-j721e-common-proc-board.dts contains the following Serdes Muxing by default:
&serdes_ln_ctrl {
idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
<J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
<J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
<J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
<J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
<J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
};
The exact mux values to be programmed can be obtained from the dt-bindings include directory of the kernel repository:
include/dt-bindings/mux/ti-serdes.h
The serdes_ln_ctrl based configuration uses the mux framework of Linux. More information can be found in the Documentation of the kernel repository:
Documentation/devicetree/bindings/mux/mux-controller.yaml
3.2.2.17.6. SERDES Clocking Options¶
Each SERDES has PLLs inside it which have to be programmed to operate at different frequencies, based on the data rate required by the Peripheral IP connected to the SERDES.
For example, based on the specification, the data rates for some of the Peripheral IPs are:
8Gbps for PCIe GEN3
5Gbps for PCIe GEN2
2.5Gbps for PCIe GEN1
5Gbps for USB3 SS
5Gbps for QSGMII [CPSW Ethernet]
The input reference clocks connected to each SERDES are used to program the PLLs inside the SERDES. The details regarding the PLL frequencies and programming is abstracted from the user. The user only has to provide the reference clocks to be used by the SERDES for programming the PLLs, based on the data rates required by the Peripheral IPs being used.
2L SERDES Clocking Options
The following illustration shows the clocking options for the 2L SERDES.
/|HFOSC0_CLKOUT
┌───────────────────────┐ / ┌◄───────────────
│ │ │ │
│ │ core_refclk / │ │HFOSC1_CLKOUT
│ ┌─────────┐ │ core_refclk1 │ ├◄───────────────
│ │ PLL0 │ │◄────────────────┤ │
│ │ │ │ │ │MAIN_PLL3_HSDIV4_CLKOUT (100/125/156.25 MHz)
│ └─────────┘ │ │ ├◄───────────────
│ │ │ │
│ │ │ │MAIN_PLL2_HSDIV4_CLKOUT (100 MHz)
│ │ \ ├◄───────────────
│ ┌─────────┐ │ \│
│ │ PLL1 │ │
│ │ │ │ cmn_refclk
│ └─────────┘ │◄─────────────────X Not Connected
│ │
│ │
│ │
│ │ cmn_refclk1
│ │◄───────────────── External Source (CLKGEN or Remote CLK)
│ 2L SERDES │
│ │
│ │ ref_der_out_clock /
│ │ refclk1_out ┌─────────┐
│ │─────────────────► │ ACSPCIE │
└───────────────────────┘ └─────────┘
As seen in the figure above, 2L SERDES IP supports 4 clock inputs (core_refclk, core_refclk1, cmn_refclk, cmn_refclk1), of which cmn_refclk is not brought out of SoC). Thus, core_refclk and core_refclk1 should be used for internal reference clock while cmn_refclk1 can be used for external reference clock.
For the clock IDs corresponding to the 2 Lane SERDES instances, refer:
4L SERDES Clocking Options
The following illustration shows the clocking options for the 4L SERDES.
/|HFOSC0_CLKOUT
┌───────────────────────┐ / ┌◄───────────────
│ │ │ │
│ │ │ │HFOSC1_CLKOUT
│ ┌─────────┐ │ core_refclk │ ├◄───────────────
│ │ PLL0 │ │◄────────────────┤ │
│ │ │ │ │ │MAIN_PLL3_HSDIV4_CLKOUT (100/125/156.25 MHz)
│ └─────────┘ │ │ ├◄───────────────
│ │ │ │
│ │ │ │MAIN_PLL2_HSDIV4_CLKOUT (100 MHz)
│ │ \ ├◄───────────────
│ ┌─────────┐ │ \│
│ │ PLL1 │ │
│ │ │ │ cmn_refclk
│ └─────────┘ │◄─────────────────
│ │
│ │
│ 4L SERDES │ refclk_out
│ │─────────────────►X Not Used
│ │
│ │
└───────────────────────┘
As seen in the figure above, 4L SERDES IP supports 2 clock inputs (core_refclk and cmn_refclk). The clock core_refclk is the internal reference clock while the clock cmn_refclk is the external reference clock. It also has an output reference clock which is not used (refclk_out).
For the clock IDs corresponding to the 4 Lane SERDES instances, refer:
4 Lane SERDES4 Clock IDs for J721E
3.2.2.17.6.1. Internal Reference Clock¶
Internal Reference Clock (2 Lane Serdes)
In order to use internal reference clock, core_refclk and core_refclk1 inputs to 2L SERDES should be used. core_refclk and core_refclk1 can each use one of the four inputs provided to the input-muxed clock.
The WIZ wrapper allows selecting the input clock to be used for core_refclk and core_refclk1. In the device-tree, within the WIZ parent node of the 2 Lane SERDES node, the following device-tree properties are used to configure the clocks:
“assigned-clocks” property is used to indicate the input-muxed clock corresponding to the core_refclk and core_refclk1 internal reference clocks.
“assigned-clock-parents” property is used to indicate which of the 4 clock inputs to the input-muxed clock is to be selected and used for core_refclk and core_refclk1.
serdes_wiz0: wiz@5000000 {
compatible = "ti,j721e-wiz-16g";
.
.
assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
.
.
};
In the above example, the WIZ node corresponding to the 2 Lane SERDES0 instance is shown. Within the WIZ node, using the “assigned-clocks” property, we are indicating that core_refclk receives its input from the clock identified by:
<k3_clks 292 11>
which is the input-muxed clock corresponding to core_refclk. The value 292 corresponds to the J721E_DEV_SERDES_16G0 device, while the value 11 corresponds to DEV_SERDES_16G0_CORE_REF_CLK which is the input-muxed clock.
Similarly, core_refclk1 is mapped to:
<&k3_clks 292 0>
with a similar pattern as core_refclk.
The value of the “assigned-clock-parents” property corresponding to core_refclk is:
<&k3_clks 292 15>
which indicates that the clock with clock ID 15 (DEV_SERDES_16G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK) which is the MAIN_PLL2_HSDIV4_CLKOUT clock, is used as the core_refclk, via the input-muxed clock. Similar pattern is followed for core_refclk1’s “assigned-clock-parents” property value.
Internal Reference Clock (4 Lane Serdes)
In order to use internal reference clock, core_refclk input to the 4L SERDES should be used. core_refclk can use one of the four inputs provided to the input-muxed clock.
The WIZ wrapper allows selecting the input clock to be used for core_refclk. In the device-tree, within the WIZ parent node of the 4 Lane SERDES node, the following device-tree properties are used to configure the clocks:
“assigned-clocks” property is used to indicate the input-muxed clock corresponding to the core_refclk internal reference clock.
“assigned-clock-parents” property is used to indicate which of the 4 clock inputs to the input-muxed clock is to be selected and used for core_refclk.
serdes_wiz4: wiz@5050000 {
compatible = "ti,j721e-wiz-10g";
.
.
assigned-clocks = <&k3_clks 297 9>;
assigned-clock-parents = <&k3_clks 297 10>;
.
.
};
In the above example, the WIZ node corresponding to the 4 Lane SERDES4 instance is shown. Within the WIZ node, using the “assigned-clocks” property, we are indicating that core_refclk receives its input from the clock identified by:
<k3_clks 297 9>
which is the input-muxed clock corresponding to core_refclk. The value 297 corresponds to the J721E_DEV_SERDES_10G0 device, while the value 9 corresponds to DEV_SERDES_10G0_CORE_REF_CLK which is the input-muxed clock.
The value of the “assigned-clock-parents” property corresponding to core_refclk is:
<&k3_clks 297 10>
which indicates that the clock with clock ID 10 (DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT) which is the HFOSC0_CLKOUT clock has to be used as the core_refclk, via the input-muxed clock.
3.2.2.17.6.2. External Reference Clock¶
External Reference Clock (2 Lane Serdes)
The 2L SERDES IP supports two external reference clock inputs. However the J721E SoC has only one external reference clock input connected (cmn_refclk1).
The two external reference clock inputs are represented in the SoC device-tree file (k3-j721e-main.dtsi) as shown below:
/ {
cmn_refclk: clock-cmnrefclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
cmn_refclk1: clock-cmnrefclk1 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
};
Note the “clock-frequency = <0>;” is set to “0” since the external clocks need not always be connected and is based on the board design. In the case of J721E CPB, CLKGEN provides 100MHz clocks to these inputs. So the frequency is actually set in the board device-tree file (k3-j721e-common-proc-board.dts) as shown below:
&cmn_refclk1 {
clock-frequency = <100000000>;
};
External Reference Clock (4 Lane Serdes)
The 4L SERDES IP supports one external reference clock input (cmn_refclk).
The external reference clock input is represented in the SoC device-tree file (k3-j721e-main.dtsi) as shown below:
/ {
cmn_refclk: clock-cmnrefclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
.
.
.
};
Note that “clock-frequency = <0>;” is set to “0” since the external clocks need not always be connected, based on the board design.
3.2.2.17.6.3. Selecting Between Internal and External Reference Clock¶
The WIZ wrapper allows selecting between the internal and external clock to be used as the input to PLL0 and PLL1 of the SERDES. Additionally, the reference clock to be used as input for the digital logic of the SERDES PHY and PMA can also be selected.
Selecting Between Internal and External Reference Clock (2 Lane Serdes)
Configuring the wizX_pll0_refclk, wizX_pll1_refclk and wizX_refclk_dig device-tree nodes for the SERDES instance SERDESX, it is possible to choose between the internal and external reference clocks for PLL0, PLL1 and the digital reference clock respecitvely. By default they are configured to use the internal reference clock in the k3-j721e-main.dtsi SoC device-tree file:
wiz0_pll0_refclk: pll0-refclk {
clocks = <&k3_clks 292 11>, <&cmn_refclk>;
#clock-cells = <0>;
assigned-clocks = <&wiz0_pll0_refclk>;
assigned-clock-parents = <&k3_clks 292 11>;
};
wiz0_pll1_refclk: pll1-refclk {
clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz0_pll1_refclk>;
assigned-clock-parents = <&k3_clks 292 0>;
};
wiz0_refclk_dig: refclk-dig {
clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz0_refclk_dig>;
assigned-clock-parents = <&k3_clks 292 11>;
};
For the example above corresponding to SERDES0 instance, each of wiz0_pll0_refclk, wiz0_pll1_refclk and wiz0_refclk_dig have two reference clock inputs to choose from: internal clock (k3_clks) and external clock (cmn_refclk).
The “assigned-clock-parents” by default sets the clock to internal clocks.
However since in J721E Common Processor Board, there is an external clock generator which feeds both to the SERDES input and to the PCIe connector, in order to use common reference clock in PCIe RC mode, the inputs are configured to use external reference clock.
For using the external reference clock, the below device-tree modifications are done in k3-j721e-common-proc-board.dts Board device-tree file:
&wiz0_pll1_refclk {
assigned-clocks = <&wiz0_pll1_refclk>;
assigned-clock-parents = <&cmn_refclk1>;
};
&wiz0_refclk_dig {
assigned-clocks = <&wiz0_refclk_dig>;
assigned-clock-parents = <&cmn_refclk1>;
};
&serdes0 {
assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
};
Here “wiz0_pll1_refclk” is configured to use external reference clock “cmn_refclk1” and “wiz0_refclk_dig” is configured to use external reference clock “&cmn_refclk1”
CDNS_SIERRA_PLL_CMNLC represents the PLL0 within SERDES and CDNS_SIERRA_PLL_CMNLC1 represents the PLL1 within SERDES. Since external clock is NOT connected to cmn_refclk (cmn_refclk is input to wiz0_pll0_refclk), PLL0 within SERDES cannot use wiz0_pll0_refclk. Hence both CDNS_SIERRA_PLL_CMNLC and CDNS_SIERRA_PLL_CMNLC1 are configured to use &wiz0_pll1_refclk.
Selecting Between Internal and External Reference Clock (4 Lane Serdes)
Configuring the wiz4_pll0_refclk, wiz4_pll1_refclk and wiz4_refclk_dig device-tree nodes for the SERDES instance SERDES4, it is possible to choose between the internal and external reference clocks for PLL0, PLL1 and digital reference clock respectively. By default they are configured to use the internal reference clock in the k3-j721e-main.dtsi SoC device-tree file:
wiz4_pll0_refclk: pll0-refclk {
clocks = <&k3_clks 297 9>, <&cmn_refclk>;
clock-output-names = "wiz4_pll0_refclk";
#clock-cells = <0>;
assigned-clocks = <&wiz4_pll0_refclk>;
assigned-clock-parents = <&k3_clks 297 9>;
};
wiz4_pll1_refclk: pll1-refclk {
clocks = <&k3_clks 297 9>, <&cmn_refclk>;
clock-output-names = "wiz4_pll1_refclk";
#clock-cells = <0>;
assigned-clocks = <&wiz4_pll1_refclk>;
assigned-clock-parents = <&k3_clks 297 9>;
};
wiz4_refclk_dig: refclk-dig {
clocks = <&k3_clks 297 9>, <&cmn_refclk>;
clock-output-names = "wiz4_refclk_dig";
#clock-cells = <0>;
assigned-clocks = <&wiz4_refclk_dig>;
assigned-clock-parents = <&k3_clks 297 9>;
};
For the example above corresponding to SERDES4 instance, each of wiz4_pll0_refclk, wiz4_pll1_refclk and wiz4_refclk_dig have two reference clock inputs to choose from: internal clock (k3_clks) and external clock (cmn_refclk).
The “assigned-clock-parents” by default sets the clock to internal clocks.
For using the external reference clock, the “assigned-clock-parents” property has to be set to <&cmn_refclk>.
Special Case CPSW9G (PCIe + QSGMII)
In the J721E Common Processor Board (for J721E SoC), the 1st SERDES instance is shared between PCIe and CPSW9G (1L for PCIe and 1L for CPSW). Since CPSW is configured and used by Ethernet Firmware and PCIe is configured and used by Linux, SERDES configuration for this instance has to be done before loading ethernet firmware and Linux. Hence the shared SERDES configuration is done in u-boot. Since by default firmwares are not loaded in u-boot and there is no way to configure only the external PHY in Linux, the QSGMII PHY (VSC8514) in Quad Port Add-On Ethernet Card has to be brought out of reset in u-boot.
The following command should be used to bring the external PHY out of reset
setenv dorprocboot 1
Driving Clock Out
Support for driving clock out via ACSPCIE using ref_der_out_clock/refclk1_out is not present in SDK.