Nested Vectored Interrupt Controller.
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#include </home/developer/.conan/data/tirtos/7.03.00.10/library-sb/ga/build/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/kernel/tirtos7/packages/ti/sysbios/family/arm/v6m/Hwi.h>
Nested Vectored Interrupt Controller.
§ RES_00
uint32_t Hwi_NVIC::RES_00 |
§ ICTR
§ RES_08
uint32_t Hwi_NVIC::RES_08 |
0xE000E004 Interrupt Control Type
§ RES_0C
uint32_t Hwi_NVIC::RES_0C |
§ STCSR
§ STRVR
0xE000E010 SysTick Control & Status Register
§ STCVR
0xE000E014 SysTick Reload Value Register
§ STCALIB
uint32_t Hwi_NVIC::STCALIB |
0xE000E018 SysTick Current Value Register
§ RES_20
uint32_t Hwi_NVIC::RES_20[56] |
0xE000E01C SysTick Calibration Value Register
§ ISER
uint32_t Hwi_NVIC::ISER[8] |
0xE000E020-0xE000E0FC reserved
§ RES_120
uint32_t Hwi_NVIC::RES_120[24] |
0xE000E100-0xE000E11C Interrupt Set Enable Registers
§ ICER
uint32_t Hwi_NVIC::ICER[8] |
0xE000E120-0xE000E17C reserved
§ RES_1A0
uint32_t Hwi_NVIC::RES_1A0[24] |
0xE000E180-0xE000E19C Interrupt Clear Enable Registers
§ ISPR
uint32_t Hwi_NVIC::ISPR[8] |
0xE000E1A0-0xE000E1FC reserved
§ RES_220
uint32_t Hwi_NVIC::RES_220[24] |
0xE000E200-0xE000E21C Interrupt Set Pending Registers
§ ICPR
uint32_t Hwi_NVIC::ICPR[8] |
0xE000E220-0xE000E7C reserved
§ RES_2A0
uint32_t Hwi_NVIC::RES_2A0[24] |
0xE000E280-0xE000E29C Interrupt Clear Pending Registers
§ IABR
uint32_t Hwi_NVIC::IABR[8] |
0xE000E2A0-0xE000E2FC reserved
§ RES_320
uint32_t Hwi_NVIC::RES_320[56] |
0xE000E300-0xE000E31C Interrupt Active Bit Registers
§ IPR
uint8_t Hwi_NVIC::IPR[240] |
0xE000E320-0xE000E3FC reserved
§ RES_4F0
uint32_t Hwi_NVIC::RES_4F0[516] |
0xE000E400-0xE000E4EF Interrupt Priority Registers
§ CPUIDBR
uint32_t Hwi_NVIC::CPUIDBR |
0xE000E4F0-0xE000ECFC reserved
§ ICSR
0xE000ED00 CPUID Base Register
§ VTOR
0xE000ED04 Interrupt Control State Register
§ AIRCR
0xE000ED08 Vector Table Offset Register
§ SCR
0xE000ED0C Application Interrupt/Reset Control Register
§ CCR
0xE000ED10 System Control Register
§ SHPR
uint8_t Hwi_NVIC::SHPR[12] |
0xE000ED14 Configuration Control Register
§ SHCSR
0xE000ED18 System Handlers 4-15 Priority Registers
§ MMFSR
0xE000ED24 System Handler Control & State Register
§ BFSR
0xE000ED28 Memory Manage Fault Status Register
§ UFSR
0xE000ED29 Bus Fault Status Register
§ HFSR
0xE000ED2A Usage Fault Status Register
§ DFSR
0xE000ED2C Hard Fault Status Register
§ MMAR
0xE000ED30 Debug Fault Status Register
§ BFAR
0xE000ED34 Memory Manager Address Register
§ AFSR
0xE000ED38 Bus Fault Address Register
§ PFR0
0xE000ED3C Auxiliary Fault Status Register
§ PFR1
0xE000ED40 Processor Feature Register
§ DFR0
0xE000ED44 Processor Feature Register
§ AFR0
0xE000ED48 Debug Feature Register
§ MMFR0
0xE000ED4C Auxiliary Feature Register
§ MMFR1
0xE000ED50 Memory Model Fault Register0
§ MMFR2
0xE000ED54 Memory Model Fault Register1
§ MMFR3
0xE000ED58 Memory Model Fault Register2
§ ISAR0
0xE000ED5C Memory Model Fault Register3
§ ISAR1
0xE000ED60 ISA Feature Register0
§ ISAR2
0xE000ED64 ISA Feature Register1
§ ISAR3
0xE000ED68 ISA Feature Register2
§ ISAR4
0xE000ED6C ISA Feature Register3
§ RES_D74
uint32_t Hwi_NVIC::RES_D74[5] |
0xE000ED70 ISA Feature Register4
§ CPACR
0xE000ED74-0xE000ED84 reserved
§ RES_D8C
uint32_t Hwi_NVIC::RES_D8C[93] |
0xE000ED88 Coprocessor Access Control Register
§ STI
0xE000ED8C-0xE000EEFC reserved
§ RES_F04
uint32_t Hwi_NVIC::RES_F04[12] |
0xE000EF00 Software Trigger Interrupt Register
§ FPCCR
0xE000EF04-0xE000EF30 reserved
§ FPCAR
0xE000EF34 FP Context Control Register
§ FPDSCR
uint32_t Hwi_NVIC::FPDSCR |
0xE000EF38 FP Context Address Register
§ MVFR0
0xE000EF3C FP Default Status Control Register
§ MVFR1
0xE000EF40 Media & FP Feature Register0
§ RES_F48
uint32_t Hwi_NVIC::RES_F48[34] |
0xE000EF44 Media & FP Feature Register1
§ PID4
0xE000EF48-0xE000EFCC reserved
§ PID5
0xE000EFD0 Peripheral ID Register4
§ PID6
0xE000EFD4 Peripheral ID Register5
§ PID7
0xE000EFD8 Peripheral ID Register6
§ PID0
0xE000EFDC Peripheral ID Register7
§ PID1
0xE000EFE0 Peripheral ID Register0
§ PID2
0xE000EFE4 Peripheral ID Register1
§ PID3
0xE000EFE8 Peripheral ID Register2
§ CID0
0xE000EFEC Peripheral ID Register3
§ CID1
0xE000EFF0 Component ID Register0
§ CID2
0xE000EFF4 Component ID Register1
§ CID3
0xE000EFF8 Component ID Register2
The documentation for this struct was generated from the following file:
- /home/developer/.conan/data/tirtos/7.03.00.10/library-sb/ga/build/5ab84d6acfe1f23c4fae0ab88f26e3a396351ac9/kernel/tirtos7/packages/ti/sysbios/family/arm/v6m/Hwi.h