I2SCC32XX.h

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/*
 * Copyright (c) 2019, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
#ifndef ti_drivers_i2s_I2SCC32XX__include
#define ti_drivers_i2s_I2SCC32XX__include

#include <ti/drivers/I2S.h>
#include <ti/drivers/dma/UDMACC32XX.h>
#include <ti/drivers/dpl/SemaphoreP.h>
#include <ti/drivers/dpl/HwiP.h>
#include <ti/drivers/utils/List.h>
#include <ti/drivers/Power.h>

#ifdef __cplusplus
extern "C" {
#endif


/*
 *  Macros defining possible I2S signal pin mux options
 *
 *  The bits in the pin mode macros are as follows:
 *  The lower 8 bits of the macro refer to the pin, offset by 1, to match
 *  driverlib pin defines.  For example, I2SCC32XX_PIN_02_WS & 0xff = 1,
 *  which equals PIN_02 in driverlib pin.h.  By matching the PIN_xx defines in
 *  driverlib pin.h, we can pass the pin directly to the driverlib functions.
 *  The upper 8 bits of the macro correspond to the pin mux confg mode
 *  value for the pin to operate in the I2S mode.  For example, pin 2 is
 *  configured with mode 13 to operate as WS.
 *
 *  The macro I2SCC32XX_PIN_UNUSED allows the user to not activate one
 *  of the signal.
 */
#define I2SCC32XX_PIN_02_McAFSX  0x0d01 
#define I2SCC32XX_PIN_03_McACLK  0x0302 
#define I2SCC32XX_PIN_15_McAFSX  0x070e 
#define I2SCC32XX_PIN_17_McAFSX  0x0610 
#define I2SCC32XX_PIN_21_McAFSX  0x0214 
#define I2SCC32XX_PIN_45_McAXR0  0x062c 
#define I2SCC32XX_PIN_45_McAFSX  0x0c2c 
#define I2SCC32XX_PIN_50_McAXR0  0x0431 
#define I2SCC32XX_PIN_50_McAXR1  0x0631 
#define I2SCC32XX_PIN_52_McACLK  0x0233 
#define I2SCC32XX_PIN_52_McAXR0  0x0433 
#define I2SCC32XX_PIN_53_McACLK  0x0234 
#define I2SCC32XX_PIN_53_McAFSX  0x0334 
#define I2SCC32XX_PIN_60_McAXR1  0x063b 
#define I2SCC32XX_PIN_62_McACLKX 0x0d3d 
#define I2SCC32XX_PIN_63_McAFSX  0x073e 
#define I2SCC32XX_PIN_64_McAXR0  0x073f 
#define I2SCC32XX_PIN_UNUSED     0xffff 
#define I2SCC32XX_PIN_50_SD1     I2SCC32XX_PIN_50_McAXR1   
#define I2SCC32XX_PIN_60_SD1     I2SCC32XX_PIN_60_McAXR1   
#define I2SCC32XX_PIN_52_SD0     I2SCC32XX_PIN_52_McAXR0   
#define I2SCC32XX_PIN_64_SD0     I2SCC32XX_PIN_64_McAXR0   
#define I2SCC32XX_PIN_45_SD0     I2SCC32XX_PIN_45_McAXR0   
#define I2SCC32XX_PIN_50_SD0     I2SCC32XX_PIN_50_McAXR0   
#define I2SCC32XX_PIN_03_SCK     I2SCC32XX_PIN_03_McACLK   
#define I2SCC32XX_PIN_52_SCK     I2SCC32XX_PIN_52_McACLK   
#define I2SCC32XX_PIN_53_SCK     I2SCC32XX_PIN_53_McACLK   
#define I2SCC32XX_PIN_62_SCKX    I2SCC32XX_PIN_62_McACLKX  
#define I2SCC32XX_PIN_02_WS      I2SCC32XX_PIN_02_McAFSX   
#define I2SCC32XX_PIN_15_WS      I2SCC32XX_PIN_15_McAFSX   
#define I2SCC32XX_PIN_17_WS      I2SCC32XX_PIN_17_McAFSX   
#define I2SCC32XX_PIN_21_WS      I2SCC32XX_PIN_21_McAFSX   
#define I2SCC32XX_PIN_45_WS      I2SCC32XX_PIN_45_McAFSX   
#define I2SCC32XX_PIN_63_WS      I2SCC32XX_PIN_63_McAFSX   
#define I2SCC32XX_PIN_53_WS      I2SCC32XX_PIN_53_McAFSX   
typedef struct {
    uint32_t                        pinSD1;                  
    uint32_t                        pinSD0;                  
    uint32_t                        pinSCK;                  
    uint32_t                        pinSCKX;                 
    uint32_t                        pinWS;                   
    uint32_t                        rxChannelIndex;          
    uint32_t                        txChannelIndex;          
    uint32_t                        intPriority;             
}I2SCC32XX_HWAttrs;

typedef struct {
    I2S_DataInterfaceUse            interfaceConfig;          
    I2S_ChannelConfig               channelsUsed;             
    uint8_t                         numberOfChannelsUsed;     
    uint8_t                         dataLine;                 
}I2SCC32XX_DataInterface;
typedef struct {
    uint16_t                        delay;                    
    I2S_Transaction                *activeTransfer;           
    I2S_Callback                    callback;                 
    uint32_t                        udmaConfig;               
    I2S_StopInterface               stopInterface;            
}I2SCC32XX_Interface;
typedef void (*I2SCC32XX_FifoUpdate)(uintptr_t arg);

typedef struct {

    bool                            isOpen;                  
    bool                            invertWS;                
    bool                            isMSBFirst;              
    bool                            isDMAUnused;             
    volatile bool                   isLastReadTransfer;      
    volatile bool                   isLastWriteTransfer;     
    uint8_t                         dataShift;               
    uint8_t                         memorySlotLength;        
    uint8_t                         sampleRotation;          
    uint8_t                         noOfInputs;              
    uint8_t                         noOfOutputs;             
    uint8_t                         udmaArbLength;           
    uint8_t                         dataLength;              
    I2S_Role                        moduleRole;              
    I2S_SamplingEdge                samplingEdge;            
    uint32_t                        samplingFrequency;       
    uint32_t                        sampleMask;              
    uint32_t                        activatedFlag;           
    I2SCC32XX_DataInterface         dataInterfaceSD0;        
    I2SCC32XX_DataInterface         dataInterfaceSD1;        
    I2SCC32XX_Interface             read;                    
    I2SCC32XX_Interface             write;                   
    I2S_Callback                    errorCallback;           
    I2SCC32XX_FifoUpdate            updateDataReadFxn;       
    I2SCC32XX_FifoUpdate            updateDataWriteFxn;      
    HwiP_Handle                     hwi;                     
    UDMACC32XX_Handle               dmaHandle;               
    Power_NotifyObj                 notifyObj;               
} I2SCC32XX_Object;
#ifdef __cplusplus
}
#endif

#endif /* ti_drivers_i2s_I2SCC32XX__include */