I2SCC32XX.h
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1 /*
2  * Copyright (c) 2019, Texas Instruments Incorporated
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32 #ifndef ti_drivers_i2s_I2SCC32XX__include
33 #define ti_drivers_i2s_I2SCC32XX__include
34 
35 #include <ti/drivers/I2S.h>
37 #include <ti/drivers/dpl/SemaphoreP.h>
38 #include <ti/drivers/dpl/HwiP.h>
39 #include <ti/drivers/utils/List.h>
40 #include <ti/drivers/Power.h>
41 
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45 
46 
47 /*
48  * Macros defining possible I2S signal pin mux options
49  *
50  * The bits in the pin mode macros are as follows:
51  * The lower 8 bits of the macro refer to the pin, offset by 1, to match
52  * driverlib pin defines. For example, I2SCC32XX_PIN_02_McAFSX & 0xff = 1,
53  * which equals PIN_02 in driverlib pin.h. By matching the PIN_xx defines in
54  * driverlib pin.h, we can pass the pin directly to the driverlib functions.
55  * The upper 8 bits of the macro correspond to the pin mux confg mode
56  * value for the pin to operate in the I2S mode. For example, pin 2 is
57  * configured with mode 13 to operate as McAFSX.
58  */
59 #define I2SCC32XX_PIN_02_McAFSX 0x0d01
60 #define I2SCC32XX_PIN_03_McACLK 0x0302
61 #define I2SCC32XX_PIN_15_McAFSX 0x070e
62 #define I2SCC32XX_PIN_17_McAFSX 0x0610
63 #define I2SCC32XX_PIN_21_McAFSX 0x0214
64 #define I2SCC32XX_PIN_45_McAXR0 0x062c
65 #define I2SCC32XX_PIN_45_McAFSX 0x0c2c
66 #define I2SCC32XX_PIN_50_McAXR0 0x0431
67 #define I2SCC32XX_PIN_50_McAXR1 0x0631
68 #define I2SCC32XX_PIN_52_McACLK 0x0233
69 #define I2SCC32XX_PIN_52_McAXR0 0x0433
70 #define I2SCC32XX_PIN_53_McACLK 0x0234
71 #define I2SCC32XX_PIN_53_McAFSX 0x0334
72 #define I2SCC32XX_PIN_60_McAXR1 0x063b
73 #define I2SCC32XX_PIN_62_McACLKX 0x0d3d
74 #define I2SCC32XX_PIN_63_McAFSX 0x073e
75 #define I2SCC32XX_PIN_64_McAXR0 0x073f
76 #define I2SCC32XX_PIN_UNUSED 0xffff
78 #define I2SCC32XX_PIN_50_SD1 I2SCC32XX_PIN_50_McAXR1
79 #define I2SCC32XX_PIN_60_SD1 I2SCC32XX_PIN_60_McAXR1
80 #define I2SCC32XX_PIN_52_SD0 I2SCC32XX_PIN_52_McAXR0
81 #define I2SCC32XX_PIN_64_SD0 I2SCC32XX_PIN_64_McAXR0
82 #define I2SCC32XX_PIN_45_SD0 I2SCC32XX_PIN_45_McAXR0
83 #define I2SCC32XX_PIN_50_SD0 I2SCC32XX_PIN_50_McAXR0
84 #define I2SCC32XX_PIN_03_SCK I2SCC32XX_PIN_03_McACLK
85 #define I2SCC32XX_PIN_52_SCK I2SCC32XX_PIN_52_McACLK
86 #define I2SCC32XX_PIN_53_SCK I2SCC32XX_PIN_53_McACLK
87 #define I2SCC32XX_PIN_62_SCKX I2SCC32XX_PIN_62_McACLKX
88 #define I2SCC32XX_PIN_02_WS I2SCC32XX_PIN_02_McAFSX
89 #define I2SCC32XX_PIN_15_WS I2SCC32XX_PIN_15_McAFSX
90 #define I2SCC32XX_PIN_17_WS I2SCC32XX_PIN_17_McAFSX
91 #define I2SCC32XX_PIN_21_WS I2SCC32XX_PIN_21_McAFSX
92 #define I2SCC32XX_PIN_45_WS I2SCC32XX_PIN_45_McAFSX
93 #define I2SCC32XX_PIN_63_WS I2SCC32XX_PIN_63_McAFSX
94 #define I2SCC32XX_PIN_53_WS I2SCC32XX_PIN_53_McAFSX
95 
96 typedef struct I2SCC32XX_HWAttrs_ {
97  uint32_t pinSD1;
100  uint32_t pinSD0;
103  uint32_t pinSCK;
106  uint32_t pinSCKX;
108  uint32_t pinWS;
111  uint32_t rxChannelIndex;
113  uint32_t txChannelIndex;
115  uint32_t intPriority;
117 
118 typedef struct I2SCC32XX_DataInterface_ {
122  uint8_t dataLine;
124 
125 typedef struct I2SCC32XX_Interface_ {
126  uint16_t delay;
129  uint32_t udmaConfig;
131 
139 typedef void (*I2SCC32XX_FifoUpdate)(uintptr_t arg);
140 
141 typedef struct I2SCC32XX_Object_ {
142 
143  bool isOpen;
144  bool invertWS;
147  bool isMSBFirst;
150  bool isDMAUnused;
158  uint8_t sampleRotation;
159  uint8_t noOfInputs;
160  uint8_t noOfOutputs;
161  uint8_t udmaArbLength;
162  uint8_t dataLength;
169  uint32_t samplingFrequency;
170  uint32_t sampleMask;
171  uint32_t activatedFlag;
179  HwiP_Handle hwi;
185 #ifdef __cplusplus
186 }
187 #endif
188 
189 #endif /* ti_drivers_i2s_I2SCC32XX__include */
I2S_SamplingEdge samplingEdge
Definition: I2SCC32XX.h:166
uint8_t dataLength
Definition: I2SCC32XX.h:162
Definition: I2SCC32XX.h:96
uint32_t pinSD0
Definition: I2SCC32XX.h:100
struct I2SCC32XX_Object_ I2SCC32XX_Object
enum I2S_ChannelConfig_ I2S_ChannelConfig
Channels used selection.
enum I2S_Role_ I2S_Role
I2S master / slave selection.
enum I2S_SamplingEdge_ I2S_SamplingEdge
I2S sampling setting.
I2SCC32XX_FifoUpdate updateDataWriteFxn
Definition: I2SCC32XX.h:178
I2SCC32XX_FifoUpdate updateDataReadFxn
Definition: I2SCC32XX.h:177
I2S_Role moduleRole
Definition: I2SCC32XX.h:163
void(* I2S_Callback)(I2S_Handle handle, int_fast16_t status, I2S_Transaction *transactionPtr)
The definition of a user-callback function used by the I2S driver.
Definition: I2S.h:686
uint8_t memorySlotLength
Definition: I2SCC32XX.h:153
Power Manager.
uint32_t samplingFrequency
Definition: I2SCC32XX.h:169
I2SCC32XX_Interface write
Definition: I2SCC32XX.h:175
I2SCC32XX_Interface read
Definition: I2SCC32XX.h:174
HwiP_Handle hwi
Definition: I2SCC32XX.h:179
enum I2S_DataInterfaceUse_ I2S_DataInterfaceUse
I2S data interface configuration.
Definition: I2SCC32XX.h:118
uint8_t sampleRotation
Definition: I2SCC32XX.h:158
uint8_t numberOfChannelsUsed
Definition: I2SCC32XX.h:121
I2SCC32XX_DataInterface dataInterfaceSD1
Definition: I2SCC32XX.h:173
uDMA driver implementation for CC32XX.
uint32_t txChannelIndex
Definition: I2SCC32XX.h:113
UDMACC32XX Global configuration.
Definition: UDMACC32XX.h:125
void(* I2SCC32XX_FifoUpdate)(uintptr_t arg)
The definition of a function used by the I2S driver to refresh the FIFO.
Definition: I2SCC32XX.h:139
uint32_t pinSCK
Definition: I2SCC32XX.h:103
bool isDMAUnused
Definition: I2SCC32XX.h:150
Inter-Integrated Circuit Sound (I2S) Bus Driver.
uint32_t pinSD1
Definition: I2SCC32XX.h:97
Power notify object structure.
Definition: Power.h:443
struct I2SCC32XX_Interface_ I2SCC32XX_Interface
Definition: I2SCC32XX.h:125
Definition: I2SCC32XX.h:141
uint32_t pinWS
Definition: I2SCC32XX.h:108
I2S transaction descriptor.
Definition: I2S.h:656
uint32_t activatedFlag
Definition: I2SCC32XX.h:171
I2S_Callback callback
Definition: I2SCC32XX.h:128
uint8_t dataLine
Definition: I2SCC32XX.h:122
uint32_t pinSCKX
Definition: I2SCC32XX.h:106
I2SCC32XX_DataInterface dataInterfaceSD0
Definition: I2SCC32XX.h:172
uint8_t udmaArbLength
Definition: I2SCC32XX.h:161
UDMACC32XX_Handle dmaHandle
Definition: I2SCC32XX.h:180
bool invertWS
Definition: I2SCC32XX.h:144
I2S_Callback errorCallback
Definition: I2SCC32XX.h:176
uint32_t udmaConfig
Definition: I2SCC32XX.h:129
struct I2SCC32XX_DataInterface_ I2SCC32XX_DataInterface
uint32_t rxChannelIndex
Definition: I2SCC32XX.h:111
bool isOpen
Definition: I2SCC32XX.h:143
I2S_ChannelConfig channelsUsed
Definition: I2SCC32XX.h:120
uint32_t intPriority
Definition: I2SCC32XX.h:115
uint8_t noOfInputs
Definition: I2SCC32XX.h:159
struct I2SCC32XX_HWAttrs_ I2SCC32XX_HWAttrs
I2S_DataInterfaceUse interfaceConfig
Definition: I2SCC32XX.h:119
uint8_t noOfOutputs
Definition: I2SCC32XX.h:160
I2S_Transaction * activeTransfer
Definition: I2SCC32XX.h:127
uint32_t sampleMask
Definition: I2SCC32XX.h:170
Power_NotifyObj notifyObj
Definition: I2SCC32XX.h:181
uint16_t delay
Definition: I2SCC32XX.h:126
Linked List interface for use in drivers.
bool isMSBFirst
Definition: I2SCC32XX.h:147
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