enum UCS.ACLKREQEN_t |
![](../../../../../Arrow_up.png) |
ACLK clock request enable
XDCscript usage |
meta-domain |
values of type UCS.ACLKREQEN_t
const UCS.ACLKREQEN_OFF;
// ACLK conditional requests are disabled
const UCS.ACLKREQEN;
// ACLK conditional requests are enabled
enum UCS.DCO0_t |
![](../../../../../Arrow_up.png) |
DCO0 Bit
XDCscript usage |
meta-domain |
values of type UCS.DCO0_t
const UCS.DCO0_OFF;
// Disable DCO0 bit
const UCS.DCO0;
// Enable DCO0 bit
enum UCS.DCO1_t |
![](../../../../../Arrow_up.png) |
DCO1 Bit
XDCscript usage |
meta-domain |
values of type UCS.DCO1_t
const UCS.DCO1_OFF;
// Disable DCO1 bit
const UCS.DCO1;
// Enable DCO1 bit
enum UCS.DCO2_t |
![](../../../../../Arrow_up.png) |
DCO2 Bit
XDCscript usage |
meta-domain |
values of type UCS.DCO2_t
const UCS.DCO2_OFF;
// Disable DCO2 bit
const UCS.DCO2;
// Enable DCO2 bit
enum UCS.DCO3_t |
![](../../../../../Arrow_up.png) |
DCO3 Bit
XDCscript usage |
meta-domain |
values of type UCS.DCO3_t
const UCS.DCO3_OFF;
// Disable DCO3 bit
const UCS.DCO3;
// Enable DCO3 bit
enum UCS.DCO4_t |
![](../../../../../Arrow_up.png) |
DCO4 Bit
XDCscript usage |
meta-domain |
values of type UCS.DCO4_t
const UCS.DCO4_OFF;
// Disable DCO4 bit
const UCS.DCO4;
// Enable DCO4 bit
enum UCS.DCOFFG_t |
![](../../../../../Arrow_up.png) |
DCO fault flag
XDCscript usage |
meta-domain |
values of type UCS.DCOFFG_t
const UCS.DCOFFG_OFF;
// No fault condition present
const UCS.DCOFFG;
// DCO fault condition present
enum UCS.DCORSEL_t |
![](../../../../../Arrow_up.png) |
DCO frequency range select
XDCscript usage |
meta-domain |
values of type UCS.DCORSEL_t
const UCS.DCORSEL_0;
// DCORSEL_0
const UCS.DCORSEL_1;
// DCORSEL_1
const UCS.DCORSEL_2;
// DCORSEL_2
const UCS.DCORSEL_3;
// DCORSEL_3
const UCS.DCORSEL_4;
// DCORSEL_4
const UCS.DCORSEL_5;
// DCORSEL_5
const UCS.DCORSEL_6;
// DCORSEL_6
const UCS.DCORSEL_7;
// DCORSEL_7
enum UCS.DISMOD_t |
![](../../../../../Arrow_up.png) |
DISMOD Bit
XDCscript usage |
meta-domain |
values of type UCS.DISMOD_t
const UCS.DISMOD_OFF;
// Modulation enabled
const UCS.DISMOD;
// Modulation disabled
enum UCS.DIVA_t |
![](../../../../../Arrow_up.png) |
ACLK source divider
XDCscript usage |
meta-domain |
values of type UCS.DIVA_t
const UCS.DIVA_0;
// Divide by 1
const UCS.DIVA_1;
// Divide by 2
const UCS.DIVA_2;
// Divide by 4
const UCS.DIVA_3;
// Divide by 8
const UCS.DIVA_4;
// Divide by 16
const UCS.DIVA_5;
// Divide by 32
const UCS.DIVA_6;
// Reserved
const UCS.DIVA_7;
// Reserved
enum UCS.DIVM_t |
![](../../../../../Arrow_up.png) |
MCLK source divider
XDCscript usage |
meta-domain |
values of type UCS.DIVM_t
const UCS.DIVM_0;
// Divide by 1
const UCS.DIVM_1;
// Divide by 2
const UCS.DIVM_2;
// Divide by 4
const UCS.DIVM_3;
// Divide by 8
const UCS.DIVM_4;
// Divide by 16
const UCS.DIVM_5;
// Divide by 32
const UCS.DIVM_6;
// Reserved
const UCS.DIVM_7;
// Reserved
enum UCS.DIVPA_t |
![](../../../../../Arrow_up.png) |
ACLK source divider available at external pin
XDCscript usage |
meta-domain |
values of type UCS.DIVPA_t
const UCS.DIVPA_0;
// Divide by 1
const UCS.DIVPA_1;
// Divide by 2
const UCS.DIVPA_2;
// Divide by 4
const UCS.DIVPA_3;
// Divide by 8
const UCS.DIVPA_4;
// Divide by 16
const UCS.DIVPA_5;
// Divide by 32
const UCS.DIVPA_6;
// Reserved
const UCS.DIVPA_7;
// Reserved
enum UCS.DIVS_t |
![](../../../../../Arrow_up.png) |
SMCLK source divider
XDCscript usage |
meta-domain |
values of type UCS.DIVS_t
const UCS.DIVS_0;
// Divide by 1
const UCS.DIVS_1;
// Divide by 2
const UCS.DIVS_2;
// Divide by 4
const UCS.DIVS_3;
// Divide by 8
const UCS.DIVS_4;
// Divide by 16
const UCS.DIVS_5;
// Divide by 32
const UCS.DIVS_6;
// Reserved
const UCS.DIVS_7;
// Reserved
enum UCS.FLLD_t |
![](../../../../../Arrow_up.png) |
FLL Loop Divider
XDCscript usage |
meta-domain |
values of type UCS.FLLD_t
const UCS.FLLD_0;
// Multiply Selected Loop Freq. 1
const UCS.FLLD_1;
// Multiply Selected Loop Freq. 2
const UCS.FLLD_2;
// Multiply Selected Loop Freq. 4
const UCS.FLLD_3;
// Multiply Selected Loop Freq. 8
const UCS.FLLD_4;
// Multiply Selected Loop Freq. 16
const UCS.FLLD_5;
// Multiply Selected Loop Freq. 32
const UCS.FLLD_6;
// Multiply Selected Loop Freq. 32
const UCS.FLLD_7;
// Multiply Selected Loop Freq. 32
enum UCS.FLLN0_t |
![](../../../../../Arrow_up.png) |
FLL Multiplier Bit 0
XDCscript usage |
meta-domain |
values of type UCS.FLLN0_t
const UCS.FLLN0_OFF;
// Disable FLLN bit 0
const UCS.FLLN0;
// Enable FLLN bit 0
enum UCS.FLLN1_t |
![](../../../../../Arrow_up.png) |
FLL Multiplier Bit 1
XDCscript usage |
meta-domain |
values of type UCS.FLLN1_t
const UCS.FLLN1_OFF;
// Disable FLLN bit 1
const UCS.FLLN1;
// Enable FLLN bit 1
enum UCS.FLLN2_t |
![](../../../../../Arrow_up.png) |
FLL Multiplier Bit 2
XDCscript usage |
meta-domain |
values of type UCS.FLLN2_t
const UCS.FLLN2_OFF;
// Disable FLLN bit 2
const UCS.FLLN2;
// Enable FLLN bit 2
enum UCS.FLLN3_t |
![](../../../../../Arrow_up.png) |
FLL Multiplier Bit 3
XDCscript usage |
meta-domain |
values of type UCS.FLLN3_t
const UCS.FLLN3_OFF;
// Disable FLLN bit 3
const UCS.FLLN3;
// Enable FLLN bit 3
enum UCS.FLLN4_t |
![](../../../../../Arrow_up.png) |
FLL Multiplier Bit 4
XDCscript usage |
meta-domain |
values of type UCS.FLLN4_t
const UCS.FLLN4_OFF;
// Disable FLLN bit 4
const UCS.FLLN4;
// Enable FLLN bit 4
enum UCS.FLLN5_t |
![](../../../../../Arrow_up.png) |
FLL Multiplier Bit 5
XDCscript usage |
meta-domain |
values of type UCS.FLLN5_t
const UCS.FLLN5_OFF;
// Disable FLLN bit 5
const UCS.FLLN5;
// Enable FLLN bit 5
enum UCS.FLLN6_t |
![](../../../../../Arrow_up.png) |
FLL Multiplier Bit 6
XDCscript usage |
meta-domain |
values of type UCS.FLLN6_t
const UCS.FLLN6_OFF;
// Disable FLLN bit 6
const UCS.FLLN6;
// Enable FLLN bit 6
enum UCS.FLLN7_t |
![](../../../../../Arrow_up.png) |
FLL Multiplier Bit 7
XDCscript usage |
meta-domain |
values of type UCS.FLLN7_t
const UCS.FLLN7_OFF;
// Disable FLLN bit 7
const UCS.FLLN7;
// Enable FLLN bit 7
enum UCS.FLLN8_t |
![](../../../../../Arrow_up.png) |
FLL Multiplier Bit 8
XDCscript usage |
meta-domain |
values of type UCS.FLLN8_t
const UCS.FLLN8_OFF;
// Disable FLLN bit 8
const UCS.FLLN8;
// Enable FLLN bit 8
enum UCS.FLLN9_t |
![](../../../../../Arrow_up.png) |
FLL Multiplier Bit 9
XDCscript usage |
meta-domain |
values of type UCS.FLLN9_t
const UCS.FLLN9_OFF;
// Disable FLLN bit 9
const UCS.FLLN9;
// Enable FLLN bit 9
enum UCS.FLLREFDIV_t |
![](../../../../../Arrow_up.png) |
FLL Reference Divider
XDCscript usage |
meta-domain |
values of type UCS.FLLREFDIV_t
const UCS.FLLREFDIV_0;
// f(FLLREFCLK) / 1
const UCS.FLLREFDIV_1;
// f(FLLREFCLK) / 2
const UCS.FLLREFDIV_2;
// f(FLLREFCLK) / 4
const UCS.FLLREFDIV_3;
// f(FLLREFCLK) / 8
const UCS.FLLREFDIV_4;
// f(FLLREFCLK) / 12
const UCS.FLLREFDIV_5;
// f(FLLREFCLK) / 16
const UCS.FLLREFDIV_6;
// Reserved
const UCS.FLLREFDIV_7;
// Reserved
enum UCS.MCLKREQEN_t |
![](../../../../../Arrow_up.png) |
MCLK clock request enable
XDCscript usage |
meta-domain |
values of type UCS.MCLKREQEN_t
const UCS.MCLKREQEN_OFF;
// MCLK conditional requests are disabled
const UCS.MCLKREQEN;
// MCLK conditional requests are enabled
enum UCS.MOD0_t |
![](../../../../../Arrow_up.png) |
MOD0 Bit
XDCscript usage |
meta-domain |
values of type UCS.MOD0_t
const UCS.MOD0_OFF;
// Disable MOD0 bit
const UCS.MOD0;
// Enable MOD0 bit
enum UCS.MOD1_t |
![](../../../../../Arrow_up.png) |
MOD1 Bit
XDCscript usage |
meta-domain |
values of type UCS.MOD1_t
const UCS.MOD1_OFF;
// Disable MOD1 bit
const UCS.MOD1;
// Enable MOD1 bit
enum UCS.MOD2_t |
![](../../../../../Arrow_up.png) |
MOD2 Bit
XDCscript usage |
meta-domain |
values of type UCS.MOD2_t
const UCS.MOD2_OFF;
// Disable MOD2 bit
const UCS.MOD2;
// Enable MOD2 bit
enum UCS.MOD3_t |
![](../../../../../Arrow_up.png) |
MOD3 Bit
XDCscript usage |
meta-domain |
values of type UCS.MOD3_t
const UCS.MOD3_OFF;
// Disable MOD3 bit
const UCS.MOD3;
// Enable MOD3 bit
enum UCS.MOD4_t |
![](../../../../../Arrow_up.png) |
MOD4 Bit
XDCscript usage |
meta-domain |
values of type UCS.MOD4_t
const UCS.MOD4_OFF;
// Disable MOD4 bit
const UCS.MOD4;
// Enable MOD4 bit
enum UCS.MODOSCREQEN_t |
![](../../../../../Arrow_up.png) |
MODOSC clock request enable
XDCscript usage |
meta-domain |
values of type UCS.MODOSCREQEN_t
const UCS.MODOSCREQEN_OFF;
// MODOSC conditional requests are disabled
const UCS.MODOSCREQEN;
// MODOSC conditional requests are enabled
enum UCS.SELA_t |
![](../../../../../Arrow_up.png) |
Select the ACLK source
XDCscript usage |
meta-domain |
values of type UCS.SELA_t
const UCS.SELA_0;
// XT1CLK
const UCS.SELA_1;
// VLOCLK
const UCS.SELA_2;
// REFOCLK
const UCS.SELA_3;
// DCOCLK
const UCS.SELA_4;
// DCOCLKDIV
const UCS.SELA_5;
// XT2CLK
const UCS.SELA_6;
// Reserved
const UCS.SELA_7;
// Reserved
enum UCS.SELM_t |
![](../../../../../Arrow_up.png) |
Select the MCLK source
XDCscript usage |
meta-domain |
values of type UCS.SELM_t
const UCS.SELM_0;
// XT1CLK
const UCS.SELM_1;
// VLOCLK
const UCS.SELM_2;
// REFOCLK
const UCS.SELM_3;
// DCOCLK
const UCS.SELM_4;
// DCOCLKDIV
const UCS.SELM_5;
// XT2CLK
const UCS.SELM_6;
// Reserved
const UCS.SELM_7;
// Reserved
enum UCS.SELREF_t |
![](../../../../../Arrow_up.png) |
FLL Reference Select
XDCscript usage |
meta-domain |
values of type UCS.SELREF_t
const UCS.SELREF_0;
// FLL Reference by XT1CLK
const UCS.SELREF_1;
// Reserved
const UCS.SELREF_2;
// FLL Reference by REFOCLK
const UCS.SELREF_3;
// Reserved
const UCS.SELREF_4;
// Reserved
const UCS.SELREF_5;
// FLL Reference by XT2CLK
const UCS.SELREF_6;
// Reserved
const UCS.SELREF_7;
// Reserved
enum UCS.SELS_t |
![](../../../../../Arrow_up.png) |
Select the SMCLK source
XDCscript usage |
meta-domain |
values of type UCS.SELS_t
const UCS.SELS_0;
// XT1CLK
const UCS.SELS_1;
// VLOCLK
const UCS.SELS_2;
// REFOCLK
const UCS.SELS_3;
// DCOCLK
const UCS.SELS_4;
// DCOCLKDIV
const UCS.SELS_5;
// XT2CLK
const UCS.SELS_6;
// Reserved
const UCS.SELS_7;
// Reserved
enum UCS.SMCLKOFF_t |
![](../../../../../Arrow_up.png) |
SMCLK off
XDCscript usage |
meta-domain |
values of type UCS.SMCLKOFF_t
const UCS.SMCLKOFF_OFF;
// SMCLK on
const UCS.SMCLKOFF;
// SMCLK off
enum UCS.SMCLKREQEN_t |
![](../../../../../Arrow_up.png) |
SMCLK clock request enable
XDCscript usage |
meta-domain |
values of type UCS.SMCLKREQEN_t
const UCS.SMCLKREQEN_OFF;
// SMCLK conditional requests are disabled
const UCS.SMCLKREQEN;
// SMCLK conditional requests are enabled
enum UCS.UCS_CLK_SOURCE_t |
![](../../../../../Arrow_up.png) |
Select the clock source
XDCscript usage |
meta-domain |
values of type UCS.UCS_CLK_SOURCE_t
const UCS.UCS_XT1CLK_SELECT;
// XT1CLK
const UCS.UCS_VLOCLK_SELECT;
// VLOCLK
const UCS.UCS_REFOCLK_SELECT;
// REFOCLK
const UCS.UCS_DCOCLK_SELECT;
// DCOCLK
const UCS.UCS_DCOCLKDIV_SELECT;
// DCOCLKDIV
const UCS.UCS_XT2CLK_SELECT;
// XT2CLK
enum UCS.UCS_CLK_SRC_DIVIDER_t |
![](../../../../../Arrow_up.png) |
Select clock source divider
XDCscript usage |
meta-domain |
values of type UCS.UCS_CLK_SRC_DIVIDER_t
const UCS.UCS_CLOCK_DIVIDER_1;
// Divide by 1
const UCS.UCS_CLOCK_DIVIDER_2;
// Divide by 2
const UCS.UCS_CLOCK_DIVIDER_4;
// Divide by 4
const UCS.UCS_CLOCK_DIVIDER_8;
// Divide by 8
const UCS.UCS_CLOCK_DIVIDER_12;
// Divide by 12
const UCS.UCS_CLOCK_DIVIDER_16;
// Divide by 16
const UCS.UCS_CLOCK_DIVIDER_32;
// Divide by 32
enum UCS.UCS_XCAP_t |
![](../../../../../Arrow_up.png) |
XT1 oscillator capacitor select
XDCscript usage |
meta-domain |
values of type UCS.UCS_XCAP_t
const UCS.UCS_XCAP_0;
// ~ 2 pF
const UCS.UCS_XCAP_1;
// ~ 5.5 pF
const UCS.UCS_XCAP_2;
// ~ 8.5 pF
const UCS.UCS_XCAP_3;
// ~ 12 pF
enum UCS.XCAP_t |
![](../../../../../Arrow_up.png) |
XT1 oscillator capacitor select
XDCscript usage |
meta-domain |
values of type UCS.XCAP_t
const UCS.XCAP_0;
// XT1 Cap 0
const UCS.XCAP_1;
// XT1 Cap 1
const UCS.XCAP_2;
// XT1 Cap 2
const UCS.XCAP_3;
// XT1 Cap 3
enum UCS.XT1BYPASSLV_t |
![](../../../../../Arrow_up.png) |
Selects XT1 bypass input swing level
XDCscript usage |
meta-domain |
values of type UCS.XT1BYPASSLV_t
const UCS.XT1BYPASSLV_OFF;
// Input range from 0 to DVCC
const UCS.XT1BYPASSLV;
// Input range from 0 to DVIO
enum UCS.XT1BYPASS_t |
![](../../../../../Arrow_up.png) |
XT1 bypass select
XDCscript usage |
meta-domain |
values of type UCS.XT1BYPASS_t
const UCS.XT1BYPASS_OFF;
// XT1 sourced internally
const UCS.XT1BYPASS;
// XT1 sourced externally from pin
enum UCS.XT1DRIVE_t |
![](../../../../../Arrow_up.png) |
XT1 oscillator current
XDCscript usage |
meta-domain |
values of type UCS.XT1DRIVE_t
const UCS.XT1DRIVE_0;
// XT1 drive 0
const UCS.XT1DRIVE_1;
// XT1 drive 1
const UCS.XT1DRIVE_2;
// XT1 drive 2
const UCS.XT1DRIVE_3;
// XT1 drive 3
enum UCS.XT1HFOFFG_t |
![](../../../../../Arrow_up.png) |
XT1 high frequency oscillator fault flag
XDCscript usage |
meta-domain |
values of type UCS.XT1HFOFFG_t
const UCS.XT1HFOFFG_OFF;
// No fault condition present
const UCS.XT1HFOFFG;
// XT1 HF fault condition present
enum UCS.XT1LFOFFG_t |
![](../../../../../Arrow_up.png) |
XT1 low frequency oscillator fault flag
XDCscript usage |
meta-domain |
values of type UCS.XT1LFOFFG_t
const UCS.XT1LFOFFG_OFF;
// No fault condition present
const UCS.XT1LFOFFG;
// XT1 LF fault condition present
enum UCS.XT1OFF_t |
![](../../../../../Arrow_up.png) |
Turns off the XT1 oscillator
XDCscript usage |
meta-domain |
values of type UCS.XT1OFF_t
const UCS.XT1OFF_OFF;
// Enable XT1
const UCS.XT1OFF;
// Disable XT1
enum UCS.XT2BYPASSLV_t |
![](../../../../../Arrow_up.png) |
Selects XT2 bypass input swing level
XDCscript usage |
meta-domain |
values of type UCS.XT2BYPASSLV_t
const UCS.XT2BYPASSLV_OFF;
// Input range from 0 to DVCC
const UCS.XT2BYPASSLV;
// Input range from 0 to DVIO
enum UCS.XT2BYPASS_t |
![](../../../../../Arrow_up.png) |
XT2 bypass select
XDCscript usage |
meta-domain |
values of type UCS.XT2BYPASS_t
const UCS.XT2BYPASS_OFF;
// XT2 sourced internally
const UCS.XT2BYPASS;
// XT2 sourced externally from pin
enum UCS.XT2DRIVE_t |
![](../../../../../Arrow_up.png) |
XT2 oscillator current
XDCscript usage |
meta-domain |
values of type UCS.XT2DRIVE_t
const UCS.XT2DRIVE_0;
// 4 MHz to 8 MHz
const UCS.XT2DRIVE_1;
// 8 MHz to 16 MHz
const UCS.XT2DRIVE_2;
// 16 MHz to 24 MHz
const UCS.XT2DRIVE_3;
// 24 MHz to 32 MHz
enum UCS.XT2OFFG_t |
![](../../../../../Arrow_up.png) |
XT2 oscillator fault flag
XDCscript usage |
meta-domain |
values of type UCS.XT2OFFG_t
const UCS.XT2OFFG_OFF;
// No fault condition present
const UCS.XT2OFFG;
// XT2 fault condition present
enum UCS.XT2OFF_t |
![](../../../../../Arrow_up.png) |
Turns off the XT2 oscillator
XDCscript usage |
meta-domain |
values of type UCS.XT2OFF_t
const UCS.XT2OFF_OFF;
// Enable XT2
const UCS.XT2OFF;
// Disable XT2
enum UCS.XTS_t |
![](../../../../../Arrow_up.png) |
XTS mode select
XDCscript usage |
meta-domain |
values of type UCS.XTS_t
const UCS.XTS_OFF;
// Low Frequency
const UCS.XTS;
// High Frequency
struct UCS.AvailableClockVariations_t |
![](../../../../../Arrow_up.png) |
Available variations of clock in a device
XDCscript usage |
meta-domain |
var obj = new UCS.AvailableClockVariations_t;
obj.clockType = String ...
obj.hasClock = Bool ...
DETAILS
Stores true/false if any of the clock variations are
available.
SEE
struct UCS.ForceSetDefaultRegister_t |
![](../../../../../Arrow_up.png) |
Force Set Default Register
XDCscript usage |
meta-domain |
var obj = new UCS.ForceSetDefaultRegister_t;
obj.register = String ...
obj.regForceSet = Bool ...
DETAILS
Type to store if each register needs to be forced initialized
even if the register is in default state.
SEE
struct UCS.UCSCTL0_t |
![](../../../../../Arrow_up.png) |
Unified Clock System Control 0 Register
XDCscript usage |
meta-domain |
var obj = new UCS.UCSCTL0_t;
// DCO tap selection bit 0
// DCO tap selection bit 1
// DCO tap selection bit 2
// DCO tap selection bit 3
// DCO tap selection bit 4
// Modulation bit counter bit 0
// Modulation bit counter bit 1
// Modulation bit counter bit 2
// Modulation bit counter bit 3
// Modulation bit counter bit 4
FIELDS
DCO
DCO tap selection.
MOD
Modulation bit counter.
struct UCS.UCSCTL1_t |
![](../../../../../Arrow_up.png) |
Unified Clock System Control 1 Register
XDCscript usage |
meta-domain |
var obj = new UCS.UCSCTL1_t;
// DCO frequency range select. These bits select the DCO frequency range of operation defined in the
device-specific datasheet
// Modulation. This bit enables/disables the modulation.
0 Modulation enabled
1 Modulation disabled
FIELDS
DCORSEL
DCO frequency range select. These bits select the DCO frequency range of operation defined in the
device-specific datasheet.
DISMOD
0 Modulation enabled, 1 Modulation disabled.
struct UCS.UCSCTL2_t |
![](../../../../../Arrow_up.png) |
Unified Clock System Control 2 Register
XDCscript usage |
meta-domain |
var obj = new UCS.UCSCTL2_t;
// FLL loop divider. These bits divide fDCOCLK in the FLL feedback loop. This results in an additional multiplier
for the multiplier bits. See also multiplier bits.
000 fDCOCLK/1
001 fDCOCLK/2
010 fDCOCLK/4
011 fDCOCLK/8
100 fDCOCLK/16
101 fDCOCLK/32
110 Reserved for future use. Defaults to fDCOCLK/32
111 Reserved for future use. Defaults to fDCOCLK/32
// Multiplier bit 0
// Multiplier bit 1
// Multiplier bit 2
// Multiplier bit 3
// Multiplier bit 4
// Multiplier bit 5
// Multiplier bit 6
// Multiplier bit 7
// Multiplier bit 8
// Multiplier bit 9
FIELDS
FLLD
FLL loop divider. These bits divide fDCOCLK in the FLL feedback loop. This results in an additional multiplier
for the multiplier bits.
FLLN
Multiplier bits. These bits set the multiplier value N of the DCO. N must be greater than 0. Writing zero to
FLLN causes N to be set to 1.
struct UCS.UCSCTL3_t |
![](../../../../../Arrow_up.png) |
Unified Clock System Control 3 Register
XDCscript usage |
meta-domain |
var obj = new UCS.UCSCTL3_t;
// FLL reference select. These bits select the FLL reference clock source.
000 XT1CLK
001 Reserved for future use. Defaults to XT1CLK.
010 REFOCLK
011 Reserved for future use. Defaults to REFOCLK.
100 Reserved for future use. Defaults to REFOCLK.
101 XT2CLK when available, otherwise REFOCLK.
110 Reserved for future use. XT2CLK when available, otherwise REFOCLK.
111 No selection. For the 'F543x and 'F541x non-A versions only, this defaults to XT2CLK. Reserved for
future use. XT2CLK when available, otherwise REFOCLK
// FLL reference divider. These bits define the divide factor for fFLLREFCLK. The divided frequency is used as the
FLL reference frequency.
000 fFLLREFCLK/1
001 fFLLREFCLK/2
010 fFLLREFCLK/4
011 fFLLREFCLK/8
100 fFLLREFCLK/12
101 fFLLREFCLK/16
110 Reserved for future use. Defaults to fFLLREFCLK/16.
111 Reserved for future use. Defaults to fFLLREFCLK/16
FIELDS
SELREF
FLL reference select. These bits select the FLL reference clock source.
FLLREFDIV
FLL reference divider. These bits define the divide factor for fFLLREFCLK. The divided frequency is used as the
FLL reference frequency.
struct UCS.UCSCTL4_t |
![](../../../../../Arrow_up.png) |
Unified Clock System Control 4 Register
XDCscript usage |
meta-domain |
var obj = new UCS.UCSCTL4_t;
// Selects the ACLK source
000 XT1CLK
001 VLOCLK
010 REFOCLK
011 DCOCLK
100 DCOCLKDIV
101 XT2CLK when available, otherwise DCOCLKDIV
110 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV.
111 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV
// Selects the SMCLK source
000 XT1CLK
001 VLOCLK
010 REFOCLK
011 DCOCLK
100 DCOCLKDIV
101 XT2CLK when available, otherwise DCOCLKDIV
110 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV.
111 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV
// Selects the MCLK source
000 XT1CLK
001 VLOCLK
010 REFOCLK
011 DCOCLK
100 DCOCLKDIV
101 XT2CLK when available, otherwise DCOCLKDIV
110 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV.
111 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV
FIELDS
SELA
Selects the ACLK source
SELS
Selects the SMCLK source
SELM
Selects the MCLK source
struct UCS.UCSCTL5_t |
![](../../../../../Arrow_up.png) |
Unified Clock System Control 5 Register
XDCscript usage |
meta-domain |
var obj = new UCS.UCSCTL5_t;
// ACLK source divider available at external pin. Divides the frequency of ACLK and presents it to an external pin.
000 fACLK/1
001 fACLK/2
010 fACLK/4
011 fACLK/8
100 fACLK/16
101 fACLK/32
110 Reserved for future use. Defaults to fACLK/32.
111 Reserved for future use. Defaults to fACLK/32
// ACLK source divider. Divides the frequency of the ACLK clock source.
000 fACLK/1
001 fACLK/2
010 fACLK/4
011 fACLK/8
100 fACLK/16
101 fACLK/32
110 Reserved for future use. Defaults to fACLK/32.
111 Reserved for future use. Defaults to fACLK/32
// SMCLK source divider
000 fSMCLK/1
001 fSMCLK/2
010 fSMCLK/4
011 fSMCLK/8
100 fSMCLK/16
101 fSMCLK/32
110 Reserved for future use. Defaults to fSMCLK/32.
111 Reserved for future use. Defaults to fSMCLK/32
// MCLK source divider
000 fMCLK/1
001 fMCLK/2
010 fMCLK/4
011 fMCLK/8
100 fMCLK/16
101 fMCLK/32
110 Reserved for future use. Defaults to fMCLK/32.
111 Reserved for future use. Defaults to fMCLK/32
FIELDS
SELA
Selects the ACLK source
SELS
Selects the SMCLK source
SELM
Selects the MCLK source
struct UCS.UCSCTL6_t |
![](../../../../../Arrow_up.png) |
Unified Clock System Control 6 Register
XDCscript usage |
meta-domain |
var obj = new UCS.UCSCTL6_t;
// The XT2 oscillator current can be adjusted to its drive needs. Initially, it starts with the highest supply current
for reliable and quick startup. If needed, user software can reduce the drive strength.
00 Lowest current consumption. XT2 oscillator operating range is 4 MHz to 8 MHz.
01 Increased drive strength XT2 oscillator. XT2 oscillator operating range is 8 MHz to 16 MHz.
10 Increased drive capability XT2 oscillator. XT2 oscillator operating range is 16 MHz to 24 MHz.
11 Maximum drive capability and maximum current consumption for both XT2 oscillator. XT2 oscillator
operating range is 24 MHz to 32 MHz
// XT2 bypass select
0 XT2 sourced internally
1 XT2 sourced externally from pin
// Turns off the XT2 oscillator
0 XT2 is on if XT2 is selected via the port selection and XT2 is not in bypass mode of operation.
1 XT2 is off if it is not used as a source for ACLK, MCLK, or SMCLK or is not used as a reference source
required for FLL operation
// The XT1 oscillator current can be adjusted to its drive needs. Initially, it starts with the highest supply current
for reliable and quick startup. If needed, user software can reduce the drive strength.
00 Lowest current consumption for XT1 LF mode. XT1 oscillator operating range in HF mode is 4 MHz to
8 MHz.
01 Increased drive strength for XT1 LF mode. XT1 oscillator operating range in HF mode is 8 MHz to
16 MHz.
10 Increased drive capability for XT1 LF mode. XT1 oscillator operating range in HF mode is 16 MHz to
24 MHz.
11 Maximum drive capability and maximum current consumption for XT1 LF mode. XT1 oscillator operating
range in HF mode is 24 MHz to 32 MHz
// XT1 mode select
0 Low-frequency mode. XCAP bits define the capacitance at the XIN and XOUT pins.
1 High-frequency mode. XCAP bits are not used
// XT1 bypass select
0 XT1 sourced internally
1 XT1 sourced externally from pin
// Oscillator capacitor selection. These bits select the capacitors applied to the LF crystal or resonator in the LF
mode (XTS = 0). The effective capacitance (seen by the crystal) is Ceff (CXIN + 2 pF)/2. It is assumed that
CXIN = CXOUT and that a parasitic capacitance of 2 pF is added by the package and the printed circuit board. For
details about the typical internal and the effective capacitors, refer to the device-specific data sheet
// SMCLK off. This bit turns off the SMCLK.
0 SMCLK on
1 SMCLK off
// XT1 off. This bit turns off the XT1.
0 XT1 is on if XT1 is selected via the port selection and XT1 is not in bypass mode of operation.
1 XT1 is off if it is not used as a source for ACLK, MCLK, or SMCLK or is not used as a reference source
required for FLL operation
FIELDS
SELA
Selects the ACLK source
SELS
Selects the SMCLK source
SELM
Selects the MCLK source
struct UCS.UCSCTL7_t |
![](../../../../../Arrow_up.png) |
Unified Clock System Control 7 Register
XDCscript usage |
meta-domain |
var obj = new UCS.UCSCTL7_t;
// XT2 oscillator fault flag. If this bit is set, the OFIFG flag is also set. XT2OFFG is set if a XT2 fault
condition exists. XT2OFFG can be cleared via software. If the XT2 fault condition still remains,
XT2OFFG is set.
0 No fault condition occurred after the last reset.
1 XT2 fault. An XT2 fault occurred after the last reset
// XT1 oscillator fault flag (HF mode). If this bit is set, the OFIFG flag is also set. XT1HFOFFG is set if a
XT1 fault condition exists. XT1HFOFFG can be cleared via software. If the XT1 fault condition still
remains, XT1HFOFFG is set.
0 No fault condition occurred after the last reset.
1 XT1 fault. An XT1 fault occurred after the last reset
// XT1 oscillator fault flag (LF mode). If this bit is set, the OFIFG flag is also set. XT1LFOFFG is set if a
XT1 fault condition exists. XT1LFOFFG can be cleared via software. If the XT1 fault condition still
remains, XT1LFOFFG is set.
0 No fault condition occurred after the last reset.
1 XT1 fault (LF mode). A XT1 fault occurred after the last reset
// DCO fault flag. If this bit is set, the OFIFG flag is also set. The DCOFFG bit is set if DCO = {0} or
DCO = {31}. DCOFFG can be cleared via software. If the DCO fault condition still remains, DCOFFG is
set.
0 No fault condition occurred after the last reset.
1 DCO fault. A DCO fault occurred after the last reset
FIELDS
XT2OFFG
0 No fault condition, 1 XT2 fault
XT1HFOFFG
0 No fault condition, 1 XT1 HF fault
XT1LFOFFG
0 No fault condition, 1 XT1 LF fault
DCOFFG
0 No fault condition, 1 DCO fault
struct UCS.UCSCTL8_t |
![](../../../../../Arrow_up.png) |
Unified Clock System Control 8 Register
XDCscript usage |
meta-domain |
var obj = new UCS.UCSCTL8_t;
// MODOSC clock request enable. Setting this enables conditional module requests for MODOSC.
0 MODOSC conditional requests are disabled.
1 MODOSC conditional requests are enabled
// SMCLK clock request enable. Setting this enables conditional module requests for SMCLK.
0 SMCLK conditional requests are disabled.
1 SMCLK conditional requests are enabled
// MCLK clock request enable. Setting this enables conditional module requests for MCLK
0 MCLK conditional requests are disabled.
1 MCLK conditional requests are enabled
// ACLK clock request enable. Setting this enables conditional module requests for ACLK
0 ACLK conditional requests are disabled.
1 ACLK conditional requests are enabled
FIELDS
MODOSCREQEN
0 MODOSC conditional requests are disabled
1 MODOSC conditional requests are enabled
SMCLKREQEN
0 SMCLK conditional requests are disabled
1 SMCLK conditional requests are enabled
MCLKREQEN
0 MCLK conditional requests are disabled
1 MCLK conditional requests are enabled
ACLKREQEN
0 ACLK conditional requests are disabled
1 ACLK conditional requests are enabled
struct UCS.UCSCTL9_t |
![](../../../../../Arrow_up.png) |
Unified Clock System Control 9 Register
XDCscript usage |
meta-domain |
var obj = new UCS.UCSCTL9_t;
// Selects XT2 bypass input swing level. Must be set for reduced swing operation.
0 Input range from 0 to DVCC
1 Input range from 0 to DVIO
// Selects XT1 bypass input swing level. Must be set for reduced swing operation.
0 Input range from 0 to DVCC
1 Input range from 0 to DVIO
FIELDS
XT2BYPASSLV
0 Input range from 0 to DVCC
1 Input range from 0 to DVIO
XT1BYPASSLV
0 Input range from 0 to DVCC
1 Input range from 0 to DVIO
UCS.getAll() // module-wide |
![](../../../../../Arrow_up.png) |
Find all peripherals of a certain type
XDCscript usage |
meta-domain |
DETAILS
The type of the peripherals returned is defined by the type of the
caller.
RETURNS
Returns an array of IPeripheral instances
UCS.getRegisters() // module-wide |
![](../../../../../Arrow_up.png) |
Find all registers defined by the peripheral
XDCscript usage |
meta-domain |
UCS.getRegisters() returns String[]
RETURNS
Returns an array of register names
Instance Config Parameters |
![](../../../../../Arrow_up.png) |
XDCscript usage |
meta-domain |
var params = new UCS.Params;
// Instance config-params object
params.ACLKHz = Float undefined;
// ACLK frequency in Hertz
params.DCOCLKDIVHz = Float undefined;
// Divided DCO clock frequency in Hertz
params.DCOCLKHz = Float 1000000;
// DCO clock frequency in Hertz
params.MCLKHz = Float undefined;
// MCLK frequency in Hertz
params.REFOCLKHz = Float 32768;
//
params.SMCLKHz = Float undefined;
// SMCLK frequency in Hertz
// Unified Clock System Control 0 Register
};
// Unified Clock System Control 1 Register
};
// Unified Clock System Control 2 Register
};
// Unified Clock System Control 3 Register
};
// Unified Clock System Control 4 Register
};
// Unified Clock System Control 5 Register
};
// Unified Clock System Control 6 Register
};
// Unified Clock System Control 7 Register
};
// Unified Clock System Control 8 Register
};
// Unified Clock System Control 9 Register
};
// ACLK clock request enable. Setting this enables conditional module requests for ACLK
0 ACLK conditional requests are disabled.
1 ACLK conditional requests are enabled
// ACLK clock source select
// ACLK clock source divider select
params.UCS_FLL_FREQ = Float 0;
// Set FLL target frequency
params.UCS_FLL_RATIO = UInt 31;
// FLLN value
// FLL reference clock source select
// FLL reference clock source divider select
// MCLK clock request enable. Setting this enables conditional module requests for MCLK
0 MCLK conditional requests are disabled.
1 MCLK conditional requests are enabled
// MCLK clock source select
// MCLK clock source divider select
// MODOSC clock request enable. Setting this enables conditional module requests for MODOSC.
0 MODOSC conditional requests are disabled.
1 MODOSC conditional requests are enabled
// External pin ACLK clock source divider select
params.UCS_SMCLKOFF = Bool false;
// Turns OFF SMCLK using the SMCLKOFF bit
0 SMCLK On
1 SMCLK Off
// SMCLK clock request enable. Setting this enables conditional module requests for SMCLK.
0 SMCLK conditional requests are disabled.
1 SMCLK conditional requests are enabled
// SMCLK clock source select
// SMCLK clock source divider select
// Set oscillator capacitor. Available only in LF mode. See device-specific datasheet for actual values
params.UCS_XT1BYPASS = Bool false;
// Set XT1 in bypass mode. The frequency input at XIN1 pin requires 0 to VCC
// Set XT1 drive strength
params.UCS_XT2BYPASS = Bool false;
// Set XT2 in bypass mode. The frequency input at XIN2 pin requires 0 to VCC
// Set XT2 drive strength
params.VLOCLKHz = Float 12000;
//
params.WATCHCRYSTALCLKHz = Float 32768;
//
params.XT1CLKHz = Float 0;
//
params.XT2CLKHz = Float 0;
//
params.baseAddr = UInt undefined;
// Address of the peripheral's control register
params.baseAddress = String "__MSP430_BASEADDRESS_UCS__";
// UCS base address
// Determine if each Register needs to be forced set or not
{
register: "UCS_SMCLKREQEN",
regForceSet: false
},
{
register: "UCS_MCLKREQEN",
regForceSet: false
},
{
register: "UCS_ACLKREQEN",
regForceSet: false
},
{
register: "UCS_MODOSCREQEN",
regForceSet: false
}
];
params.hasAllCal = Bool false;
// Specify if device has all calibration constants
params.hasHFXT1 = Bool false;
// Specify if HFXT1 is available on the device
params.hasRosc = Bool false;
// Specify if Rosc is available on the device
params.hasVLO = Bool false;
// Specify if VLO is available on the device
params.hasXT2 = Bool false;
// Specify if XT2 is available on the device
params.maxCpuFrequency = Float 0;
// Maximum CPU frequency in Hertz
params.name = String undefined;
// Specific peripheral name given by the device
params.owner = String undefined;
// String specifying the entity that manages the peripheral
config UCS.ACLKHz // instance |
![](../../../../../Arrow_up.png) |
ACLK frequency in Hertz
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
const params.ACLKHz = Float computed value;
config UCS.DCOCLKDIVHz // instance |
![](../../../../../Arrow_up.png) |
Divided DCO clock frequency in Hertz
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
const params.DCOCLKDIVHz = Float computed value;
config UCS.DCOCLKHz // instance |
![](../../../../../Arrow_up.png) |
DCO clock frequency in Hertz
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
const params.DCOCLKHz = Float 1000000;
config UCS.MCLKHz // instance |
![](../../../../../Arrow_up.png) |
MCLK frequency in Hertz
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
const params.MCLKHz = Float computed value;
config UCS.REFOCLKHz // instance |
![](../../../../../Arrow_up.png) |
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
params.REFOCLKHz = Float 32768;
config UCS.SMCLKHz // instance |
![](../../../../../Arrow_up.png) |
SMCLK frequency in Hertz
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
const params.SMCLKHz = Float computed value;
config UCS.UCSCTL0 // instance |
![](../../../../../Arrow_up.png) |
Unified Clock System Control 0 Register
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
};
config UCS.UCSCTL1 // instance |
![](../../../../../Arrow_up.png) |
Unified Clock System Control 1 Register
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
};
config UCS.UCSCTL2 // instance |
![](../../../../../Arrow_up.png) |
Unified Clock System Control 2 Register
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
};
config UCS.UCSCTL3 // instance |
![](../../../../../Arrow_up.png) |
Unified Clock System Control 3 Register
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
};
config UCS.UCSCTL4 // instance |
![](../../../../../Arrow_up.png) |
Unified Clock System Control 4 Register
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
};
config UCS.UCSCTL5 // instance |
![](../../../../../Arrow_up.png) |
Unified Clock System Control 5 Register
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
};
config UCS.UCSCTL6 // instance |
![](../../../../../Arrow_up.png) |
Unified Clock System Control 6 Register
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
};
config UCS.UCSCTL7 // instance |
![](../../../../../Arrow_up.png) |
Unified Clock System Control 7 Register
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
};
config UCS.UCSCTL8 // instance |
![](../../../../../Arrow_up.png) |
Unified Clock System Control 8 Register
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
};
config UCS.UCSCTL9 // instance |
![](../../../../../Arrow_up.png) |
Unified Clock System Control 9 Register
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
};
config UCS.UCS_ACLKREQEN // instance |
![](../../../../../Arrow_up.png) |
ACLK clock request enable. Setting this enables conditional module requests for ACLK
0 ACLK conditional requests are disabled.
1 ACLK conditional requests are enabled
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
config UCS.UCS_ACLK_SOURCE // instance |
![](../../../../../Arrow_up.png) |
ACLK clock source select
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
config UCS.UCS_ACLK_SRC_DIVIDER // instance |
![](../../../../../Arrow_up.png) |
ACLK clock source divider select
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
config UCS.UCS_FLL_FREQ // instance |
![](../../../../../Arrow_up.png) |
Set FLL target frequency
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
params.UCS_FLL_FREQ = Float 0;
config UCS.UCS_FLL_RATIO // instance |
![](../../../../../Arrow_up.png) |
FLLN value
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
params.UCS_FLL_RATIO = UInt 31;
config UCS.UCS_FLL_REF_CLK_SOURCE // instance |
![](../../../../../Arrow_up.png) |
FLL reference clock source select
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
config UCS.UCS_FLL_REF_SRC_DIVIDER // instance |
![](../../../../../Arrow_up.png) |
FLL reference clock source divider select
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
config UCS.UCS_MCLKREQEN // instance |
![](../../../../../Arrow_up.png) |
MCLK clock request enable. Setting this enables conditional module requests for MCLK
0 MCLK conditional requests are disabled.
1 MCLK conditional requests are enabled
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
config UCS.UCS_MCLK_SOURCE // instance |
![](../../../../../Arrow_up.png) |
MCLK clock source select
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
config UCS.UCS_MCLK_SRC_DIVIDER // instance |
![](../../../../../Arrow_up.png) |
MCLK clock source divider select
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
config UCS.UCS_MODOSCREQEN // instance |
![](../../../../../Arrow_up.png) |
MODOSC clock request enable. Setting this enables conditional module requests for MODOSC.
0 MODOSC conditional requests are disabled.
1 MODOSC conditional requests are enabled
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
config UCS.UCS_PACLK_SRC_DIVIDER // instance |
![](../../../../../Arrow_up.png) |
External pin ACLK clock source divider select
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
config UCS.UCS_SMCLKOFF // instance |
![](../../../../../Arrow_up.png) |
Turns OFF SMCLK using the SMCLKOFF bit
0 SMCLK On
1 SMCLK Off
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
params.UCS_SMCLKOFF = Bool false;
config UCS.UCS_SMCLKREQEN // instance |
![](../../../../../Arrow_up.png) |
SMCLK clock request enable. Setting this enables conditional module requests for SMCLK.
0 SMCLK conditional requests are disabled.
1 SMCLK conditional requests are enabled
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
config UCS.UCS_SMCLK_SOURCE // instance |
![](../../../../../Arrow_up.png) |
SMCLK clock source select
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
config UCS.UCS_SMCLK_SRC_DIVIDER // instance |
![](../../../../../Arrow_up.png) |
SMCLK clock source divider select
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
config UCS.UCS_XCAP // instance |
![](../../../../../Arrow_up.png) |
Set oscillator capacitor. Available only in LF mode. See device-specific datasheet for actual values
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
config UCS.UCS_XT1BYPASS // instance |
![](../../../../../Arrow_up.png) |
Set XT1 in bypass mode. The frequency input at XIN1 pin requires 0 to VCC
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
params.UCS_XT1BYPASS = Bool false;
config UCS.UCS_XT1_DRIVE // instance |
![](../../../../../Arrow_up.png) |
Set XT1 drive strength
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
config UCS.UCS_XT2BYPASS // instance |
![](../../../../../Arrow_up.png) |
Set XT2 in bypass mode. The frequency input at XIN2 pin requires 0 to VCC
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
params.UCS_XT2BYPASS = Bool false;
config UCS.UCS_XT2_DRIVE // instance |
![](../../../../../Arrow_up.png) |
Set XT2 drive strength
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
config UCS.VLOCLKHz // instance |
![](../../../../../Arrow_up.png) |
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
params.VLOCLKHz = Float 12000;
config UCS.WATCHCRYSTALCLKHz // instance |
![](../../../../../Arrow_up.png) |
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
params.WATCHCRYSTALCLKHz = Float 32768;
config UCS.XT1CLKHz // instance |
![](../../../../../Arrow_up.png) |
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
params.XT1CLKHz = Float 0;
config UCS.XT2CLKHz // instance |
![](../../../../../Arrow_up.png) |
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
params.XT2CLKHz = Float 0;
config UCS.baseAddr // instance |
![](../../../../../Arrow_up.png) |
Address of the peripheral's control register
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
params.baseAddr = UInt undefined;
DETAILS
A peripheral's registers are commonly accessed through a structure
that defines the offsets of a particular register from the lowest
address mapped to a peripheral. That lowest address is specified by
this parameter.
config UCS.baseAddress // instance |
![](../../../../../Arrow_up.png) |
UCS base address
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
params.baseAddress = String "__MSP430_BASEADDRESS_UCS__";
config UCS.forceSetDefaultRegister // instance |
![](../../../../../Arrow_up.png) |
Determine if each Register needs to be forced set or not
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
{
register: "UCS_SMCLKREQEN",
regForceSet: false
},
{
register: "UCS_MCLKREQEN",
regForceSet: false
},
{
register: "UCS_ACLKREQEN",
regForceSet: false
},
{
register: "UCS_MODOSCREQEN",
regForceSet: false
}
];
config UCS.hasAllCal // instance |
![](../../../../../Arrow_up.png) |
Specify if device has all calibration constants
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
params.hasAllCal = Bool false;
DETAILS
G1 devices do not.
config UCS.hasHFXT1 // instance |
![](../../../../../Arrow_up.png) |
Specify if HFXT1 is available on the device
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
params.hasHFXT1 = Bool false;
DETAILS
Not all devices have high frequency clock. This specifies if
it is available for a particular device.
config UCS.hasRosc // instance |
![](../../../../../Arrow_up.png) |
Specify if Rosc is available on the device
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
params.hasRosc = Bool false;
DETAILS
Not all devices have Rosc circuitry. This specifies if
it is available for a particular device.
config UCS.hasVLO // instance |
![](../../../../../Arrow_up.png) |
Specify if VLO is available on the device
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
params.hasVLO = Bool false;
DETAILS
Not all devices have very low frequency clock VLO. This specifies if
it is available for a particular device.
config UCS.hasXT2 // instance |
![](../../../../../Arrow_up.png) |
Specify if XT2 is available on the device
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
params.hasXT2 = Bool false;
DETAILS
Not all devices have XT2 clock available. This specifies if
it is available for a particular device.
config UCS.maxCpuFrequency // instance |
![](../../../../../Arrow_up.png) |
Maximum CPU frequency in Hertz
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
params.maxCpuFrequency = Float 0;
config UCS.name // instance |
![](../../../../../Arrow_up.png) |
Specific peripheral name given by the device
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
params.name = String undefined;
DETAILS
Devices can have more than one peripheral of the same type. In such
cases, device data sheets give different names to the instances of a
same peripheral. For example, the name for a timer module could be
TimerA3, and a device that has two such timers can name them TA0
and TA1.
config UCS.owner // instance |
![](../../../../../Arrow_up.png) |
String specifying the entity that manages the peripheral
XDCscript usage |
meta-domain |
var params = new UCS.Params;
...
params.owner = String undefined;
UCS.computeDCOCLKHz() // instance |
![](../../../../../Arrow_up.png) |
Initialize to the nearest available DCO clock frequency
XDCscript usage |
meta-domain |
inst.computeDCOCLKHz(Float DCOCLKHz) returns Void