1 2 3 4 5 6 7 8 9 10 11
12
13 /*!
14 * ======== UCS ========
15 * MSP430 Unified Clock System
16 */
17 metaonly module UCS inherits IClock
18 {
19 /*! DCO4 Bit */
20 enum DCO4_t {
21 DCO4_OFF = 0x0000, /*! Disable DCO4 bit */
22 DCO4 = 0x1000 /*! Enable DCO4 bit */
23 };
24
25 /*! DCO3 Bit */
26 enum DCO3_t {
27 DCO3_OFF = 0x0000, /*! Disable DCO3 bit */
28 DCO3 = 0x0800 /*! Enable DCO3 bit */
29 };
30
31 /*! DCO2 Bit */
32 enum DCO2_t {
33 DCO2_OFF = 0x0000, /*! Disable DCO2 bit */
34 DCO2 = 0x0400 /*! Enable DCO2 bit */
35 };
36
37 /*! DCO1 Bit */
38 enum DCO1_t {
39 DCO1_OFF = 0x0000, /*! Disable DCO1 bit */
40 DCO1 = 0x0200 /*! Enable DCO1 bit */
41 };
42
43 /*! DCO0 Bit */
44 enum DCO0_t {
45 DCO0_OFF = 0x0000, /*! Disable DCO0 bit */
46 DCO0 = 0x0100 /*! Enable DCO0 bit */
47 };
48
49 /*! MOD4 Bit */
50 enum MOD4_t {
51 MOD4_OFF = 0x0000, /*! Disable MOD4 bit */
52 MOD4 = 0x0080 /*! Enable MOD4 bit */
53 };
54
55 /*! MOD3 Bit */
56 enum MOD3_t {
57 MOD3_OFF = 0x0000, /*! Disable MOD3 bit */
58 MOD3 = 0x0040 /*! Enable MOD3 bit */
59 };
60
61 /*! MOD2 Bit */
62 enum MOD2_t {
63 MOD2_OFF = 0x0000, /*! Disable MOD2 bit */
64 MOD2 = 0x0020 /*! Enable MOD2 bit */
65 };
66
67 /*! MOD1 Bit */
68 enum MOD1_t {
69 MOD1_OFF = 0x0000, /*! Disable MOD1 bit */
70 MOD1 = 0x0010 /*! Enable MOD1 bit */
71 };
72
73 /*! MOD0 Bit */
74 enum MOD0_t {
75 MOD0_OFF = 0x0000, /*! Disable MOD0 bit */
76 MOD0 = 0x0080 /*! Enable MOD0 bit */
77 };
78
79 /*! DCO frequency range select */
80 enum DCORSEL_t {
81 DCORSEL_0 = 0x0000, /*! DCORSEL_0 */
82 DCORSEL_1 = 0x0010, /*! DCORSEL_1 */
83 DCORSEL_2 = 0x0020, /*! DCORSEL_2 */
84 DCORSEL_3 = 0x0030, /*! DCORSEL_3 */
85 DCORSEL_4 = 0x0040, /*! DCORSEL_4 */
86 DCORSEL_5 = 0x0050, /*! DCORSEL_5 */
87 DCORSEL_6 = 0x0060, /*! DCORSEL_6 */
88 DCORSEL_7 = 0x0070 /*! DCORSEL_7 */
89 };
90
91 /*! DISMOD Bit */
92 enum DISMOD_t {
93 DISMOD_OFF = 0x0000, /*! Modulation enabled */
94 DISMOD = 0x0001 /*! Modulation disabled */
95 };
96
97 /*! FLL Loop Divider */
98 enum FLLD_t {
99 FLLD_0 = 0x0000, /*! Multiply Selected Loop Freq. 1 */
100 FLLD_1 = 0x1000, /*! Multiply Selected Loop Freq. 2 */
101 FLLD_2 = 0x2000, /*! Multiply Selected Loop Freq. 4 */
102 FLLD_3 = 0x3000, /*! Multiply Selected Loop Freq. 8 */
103 FLLD_4 = 0x4000, /*! Multiply Selected Loop Freq. 16 */
104 FLLD_5 = 0x5000, /*! Multiply Selected Loop Freq. 32 */
105 FLLD_6 = 0x6000, /*! Multiply Selected Loop Freq. 32 */
106 FLLD_7 = 0x7000 /*! Multiply Selected Loop Freq. 32 */
107 };
108
109 /*! FLL Multiplier Bit 0 */
110 enum FLLN0_t {
111 FLLN0_OFF = 0x0000, /*! Disable FLLN bit 0 */
112 FLLN0 = 0x0001 /*! Enable FLLN bit 0 */
113 };
114
115 /*! FLL Multiplier Bit 1 */
116 enum FLLN1_t {
117 FLLN1_OFF = 0x0000, /*! Disable FLLN bit 1 */
118 FLLN1 = 0x0002 /*! Enable FLLN bit 1 */
119 };
120
121 /*! FLL Multiplier Bit 2 */
122 enum FLLN2_t {
123 FLLN2_OFF = 0x0000, /*! Disable FLLN bit 2 */
124 FLLN2 = 0x0004 /*! Enable FLLN bit 2 */
125 };
126
127 /*! FLL Multiplier Bit 3 */
128 enum FLLN3_t {
129 FLLN3_OFF = 0x0000, /*! Disable FLLN bit 3 */
130 FLLN3 = 0x0008 /*! Enable FLLN bit 3 */
131 };
132
133 /*! FLL Multiplier Bit 4 */
134 enum FLLN4_t {
135 FLLN4_OFF = 0x0000, /*! Disable FLLN bit 4 */
136 FLLN4 = 0x0010 /*! Enable FLLN bit 4 */
137 };
138
139 /*! FLL Multiplier Bit 5 */
140 enum FLLN5_t {
141 FLLN5_OFF = 0x0000, /*! Disable FLLN bit 5 */
142 FLLN5 = 0x0020 /*! Enable FLLN bit 5 */
143 };
144
145 /*! FLL Multiplier Bit 6 */
146 enum FLLN6_t {
147 FLLN6_OFF = 0x0000, /*! Disable FLLN bit 6 */
148 FLLN6 = 0x0040 /*! Enable FLLN bit 6 */
149 };
150
151 /*! FLL Multiplier Bit 7 */
152 enum FLLN7_t {
153 FLLN7_OFF = 0x0000, /*! Disable FLLN bit 7 */
154 FLLN7 = 0x0080 /*! Enable FLLN bit 7 */
155 };
156
157 /*! FLL Multiplier Bit 8 */
158 enum FLLN8_t {
159 FLLN8_OFF = 0x0000, /*! Disable FLLN bit 8 */
160 FLLN8 = 0x0100 /*! Enable FLLN bit 8 */
161 };
162
163 /*! FLL Multiplier Bit 9 */
164 enum FLLN9_t {
165 FLLN9_OFF = 0x0000, /*! Disable FLLN bit 9 */
166 FLLN9 = 0x0200 /*! Enable FLLN bit 9 */
167 };
168
169 /*! FLL Reference Select */
170 enum SELREF_t {
171 SELREF_0 = 0x0000, /*! FLL Reference by XT1CLK */
172 SELREF_1 = 0x0010, /*! Reserved */
173 SELREF_2 = 0x0020, /*! FLL Reference by REFOCLK */
174 SELREF_3 = 0x0030, /*! Reserved */
175 SELREF_4 = 0x0040, /*! Reserved */
176 SELREF_5 = 0x0050, /*! FLL Reference by XT2CLK */
177 SELREF_6 = 0x0060, /*! Reserved */
178 SELREF_7 = 0x0070 /*! Reserved */
179 };
180
181 /*! FLL Reference Divider */
182 enum FLLREFDIV_t {
183 FLLREFDIV_0 = 0x0000, /*! f(FLLREFCLK) / 1 */
184 FLLREFDIV_1 = 0x0001, /*! f(FLLREFCLK) / 2 */
185 FLLREFDIV_2 = 0x0002, /*! f(FLLREFCLK) / 4 */
186 FLLREFDIV_3 = 0x0003, /*! f(FLLREFCLK) / 8 */
187 FLLREFDIV_4 = 0x0004, /*! f(FLLREFCLK) / 12 */
188 FLLREFDIV_5 = 0x0005, /*! f(FLLREFCLK) / 16 */
189 FLLREFDIV_6 = 0x0006, /*! Reserved */
190 FLLREFDIV_7 = 0x0007 /*! Reserved */
191 };
192
193 /*! Select the ACLK source */
194 enum SELA_t {
195 SELA_0 = 0x0000, /*! XT1CLK */
196 SELA_1 = 0x0100, /*! VLOCLK */
197 SELA_2 = 0x0200, /*! REFOCLK */
198 SELA_3 = 0x0300, /*! DCOCLK */
199 SELA_4 = 0x0400, /*! DCOCLKDIV */
200 SELA_5 = 0x0500, /*! XT2CLK */
201 SELA_6 = 0x0600, /*! Reserved */
202 SELA_7 = 0x0700 /*! Reserved */
203 };
204
205 /*! Select the SMCLK source */
206 enum SELS_t {
207 SELS_0 = 0x0000, /*! XT1CLK */
208 SELS_1 = 0x0010, /*! VLOCLK */
209 SELS_2 = 0x0020, /*! REFOCLK */
210 SELS_3 = 0x0030, /*! DCOCLK */
211 SELS_4 = 0x0040, /*! DCOCLKDIV */
212 SELS_5 = 0x0050, /*! XT2CLK */
213 SELS_6 = 0x0060, /*! Reserved */
214 SELS_7 = 0x0070 /*! Reserved */
215 };
216
217 /*! Select the MCLK source */
218 enum SELM_t {
219 SELM_0 = 0x0000, /*! XT1CLK */
220 SELM_1 = 0x0001, /*! VLOCLK */
221 SELM_2 = 0x0002, /*! REFOCLK */
222 SELM_3 = 0x0003, /*! DCOCLK */
223 SELM_4 = 0x0004, /*! DCOCLKDIV */
224 SELM_5 = 0x0005, /*! XT2CLK */
225 SELM_6 = 0x0006, /*! Reserved */
226 SELM_7 = 0x0007 /*! Reserved */
227 };
228
229 /*! ACLK source divider available at external pin */
230 enum DIVPA_t {
231 DIVPA_0 = 0x0000, /*! Divide by 1 */
232 DIVPA_1 = 0x1000, /*! Divide by 2 */
233 DIVPA_2 = 0x2000, /*! Divide by 4 */
234 DIVPA_3 = 0x3000, /*! Divide by 8 */
235 DIVPA_4 = 0x4000, /*! Divide by 16 */
236 DIVPA_5 = 0x5000, /*! Divide by 32 */
237 DIVPA_6 = 0x6000, /*! Reserved */
238 DIVPA_7 = 0x7000 /*! Reserved */
239 };
240
241 /*! ACLK source divider */
242 enum DIVA_t {
243 DIVA_0 = 0x0000, /*! Divide by 1 */
244 DIVA_1 = 0x0100, /*! Divide by 2 */
245 DIVA_2 = 0x0200, /*! Divide by 4 */
246 DIVA_3 = 0x0300, /*! Divide by 8 */
247 DIVA_4 = 0x0400, /*! Divide by 16 */
248 DIVA_5 = 0x0500, /*! Divide by 32 */
249 DIVA_6 = 0x0600, /*! Reserved */
250 DIVA_7 = 0x0700 /*! Reserved */
251 };
252
253 /*! SMCLK source divider */
254 enum DIVS_t {
255 DIVS_0 = 0x0000, /*! Divide by 1 */
256 DIVS_1 = 0x0010, /*! Divide by 2 */
257 DIVS_2 = 0x0020, /*! Divide by 4 */
258 DIVS_3 = 0x0030, /*! Divide by 8 */
259 DIVS_4 = 0x0040, /*! Divide by 16 */
260 DIVS_5 = 0x0050, /*! Divide by 32 */
261 DIVS_6 = 0x0060, /*! Reserved */
262 DIVS_7 = 0x0070 /*! Reserved */
263 };
264
265 /*! MCLK source divider */
266 enum DIVM_t {
267 DIVM_0 = 0x0000, /*! Divide by 1 */
268 DIVM_1 = 0x0010, /*! Divide by 2 */
269 DIVM_2 = 0x0020, /*! Divide by 4 */
270 DIVM_3 = 0x0030, /*! Divide by 8 */
271 DIVM_4 = 0x0040, /*! Divide by 16 */
272 DIVM_5 = 0x0050, /*! Divide by 32 */
273 DIVM_6 = 0x0060, /*! Reserved */
274 DIVM_7 = 0x0070 /*! Reserved */
275 };
276
277 /*! XT2 oscillator current */
278 enum XT2DRIVE_t {
279 XT2DRIVE_0 = 0x0000, /*! 4 MHz to 8 MHz */
280 XT2DRIVE_1 = 0x4000, /*! 8 MHz to 16 MHz */
281 XT2DRIVE_2 = 0x8000, /*! 16 MHz to 24 MHz */
282 XT2DRIVE_3 = 0xC000 /*! 24 MHz to 32 MHz */
283 };
284
285 /*! XT2 bypass select */
286 enum XT2BYPASS_t {
287 XT2BYPASS_OFF = 0x0000, /*! XT2 sourced internally */
288 XT2BYPASS = 0x1000 /*! XT2 sourced externally from pin */
289 };
290
291 /*! Turns off the XT2 oscillator */
292 enum XT2OFF_t {
293 XT2OFF_OFF = 0x0000, /*! Enable XT2 */
294 XT2OFF = 0x0100 /*! Disable XT2*/
295 };
296
297 /*! XT1 oscillator current */
298 enum XT1DRIVE_t {
299 XT1DRIVE_0 = 0x0000, /*! XT1 drive 0 */
300 XT1DRIVE_1 = 0x0040, /*! XT1 drive 1 */
301 XT1DRIVE_2 = 0x0080, /*! XT1 drive 2 */
302 XT1DRIVE_3 = 0x00C0 /*! XT1 drive 3 */
303 };
304
305 /*! XTS mode select */
306 enum XTS_t {
307 XTS_OFF = 0x0000, /*! Low Frequency */
308 XTS = 0x0020 /*! High Frequency */
309 };
310
311 /*! XT1 bypass select */
312 enum XT1BYPASS_t {
313 XT1BYPASS_OFF = 0x0000, /*! XT1 sourced internally */
314 XT1BYPASS = 0x0010 /*! XT1 sourced externally from pin */
315 };
316
317 /*! XT1 oscillator capacitor select */
318 enum XCAP_t {
319 XCAP_0 = 0x0000, /*! XT1 Cap 0 */
320 XCAP_1 = 0x0004, /*! XT1 Cap 1 */
321 XCAP_2 = 0x0008, /*! XT1 Cap 2 */
322 XCAP_3 = 0x000C /*! XT1 Cap 3 */
323 };
324
325 /*! SMCLK off */
326 enum SMCLKOFF_t {
327 SMCLKOFF_OFF = 0x0000, /*! SMCLK on */
328 SMCLKOFF = 0x0002 /*! SMCLK off */
329 };
330
331 /*! Turns off the XT1 oscillator */
332 enum XT1OFF_t {
333 XT1OFF_OFF = 0x0000, /*! Enable XT1 */
334 XT1OFF = 0x0001 /*! Disable XT1 */
335 };
336
337 /*! XT2 oscillator fault flag */
338 enum XT2OFFG_t {
339 XT2OFFG_OFF = 0x0000, /*! No fault condition present */
340 XT2OFFG = 0x0008 /*! XT2 fault condition present */
341 };
342
343 /*! XT1 high frequency oscillator fault flag */
344 enum XT1HFOFFG_t {
345 XT1HFOFFG_OFF = 0x0000, /*! No fault condition present */
346 XT1HFOFFG = 0x0004 /*! XT1 HF fault condition present */
347 };
348
349 /*! XT1 low frequency oscillator fault flag */
350 enum XT1LFOFFG_t {
351 XT1LFOFFG_OFF = 0x0000, /*! No fault condition present */
352 XT1LFOFFG = 0x0002 /*! XT1 LF fault condition present */
353 };
354
355 /*! DCO fault flag */
356 enum DCOFFG_t {
357 DCOFFG_OFF = 0x0000, /*! No fault condition present */
358 DCOFFG = 0x0001 /*! DCO fault condition present */
359 };
360
361 /*! MODOSC clock request enable */
362 enum MODOSCREQEN_t {
363 MODOSCREQEN_OFF = 0x0000, /*! MODOSC conditional requests are disabled */
364 MODOSCREQEN = 0x0008 /*! MODOSC conditional requests are enabled */
365 };
366
367 /*! SMCLK clock request enable */
368 enum SMCLKREQEN_t {
369 SMCLKREQEN_OFF = 0x0000, /*! SMCLK conditional requests are disabled */
370 SMCLKREQEN = 0x0004 /*! SMCLK conditional requests are enabled */
371 };
372
373 /*! MCLK clock request enable */
374 enum MCLKREQEN_t {
375 MCLKREQEN_OFF = 0x0000, /*! MCLK conditional requests are disabled */
376 MCLKREQEN = 0x0002 /*! MCLK conditional requests are enabled */
377 };
378
379 /*! ACLK clock request enable */
380 enum ACLKREQEN_t {
381 ACLKREQEN_OFF = 0x0000, /*! ACLK conditional requests are disabled */
382 ACLKREQEN = 0x0001 /*! ACLK conditional requests are enabled */
383 };
384
385 /*! Selects XT2 bypass input swing level */
386 enum XT2BYPASSLV_t {
387 XT2BYPASSLV_OFF = 0x0000, /*! Input range from 0 to DVCC */
388 XT2BYPASSLV = 0x0002 /*! Input range from 0 to DVIO */
389 };
390
391 /*! Selects XT1 bypass input swing level */
392 enum XT1BYPASSLV_t {
393 XT1BYPASSLV_OFF = 0x0000, /*! Input range from 0 to DVCC */
394 XT1BYPASSLV = 0x0001 /*! Input range from 0 to DVIO */
395 };
396
397 /*!
398 * ======== UCSCTL0_t ========
399 * Unified Clock System Control 0 Register
400 *
401 * @field(DCO) DCO tap selection.
402 * @field(MOD) Modulation bit counter.
403 */
404 struct UCSCTL0_t {
405 DCO0_t DCO0; /*! DCO tap selection bit 0 */
406 DCO1_t DCO1; /*! DCO tap selection bit 1 */
407 DCO2_t DCO2; /*! DCO tap selection bit 2 */
408 DCO3_t DCO3; /*! DCO tap selection bit 3 */
409 DCO4_t DCO4; /*! DCO tap selection bit 4 */
410 MOD0_t MOD0; /*! Modulation bit counter bit 0 */
411 MOD1_t MOD1; /*! Modulation bit counter bit 1 */
412 MOD2_t MOD2; /*! Modulation bit counter bit 2 */
413 MOD3_t MOD3; /*! Modulation bit counter bit 3 */
414 MOD4_t MOD4; /*! Modulation bit counter bit 4 */
415 }
416
417 /*!
418 * ======== UCSCTL1_t ========
419 * Unified Clock System Control 1 Register
420 *
421 * @field(DCORSEL) DCO frequency range select. These bits select the DCO frequency range of operation defined in the
422 * device-specific datasheet.
423 * @field(DISMOD) 0 Modulation enabled, 1 Modulation disabled.
424 */
425 struct UCSCTL1_t {
426 DCORSEL_t DCORSEL; /*! DCO frequency range select. These bits select the DCO frequency range of operation defined in the
427 * device-specific datasheet. */
428 DISMOD_t DISMOD; /*! Modulation. This bit enables/disables the modulation.
429 * 0 Modulation enabled
430 * 1 Modulation disabled */
431 }
432
433 /*!
434 * ======== UCSCTL2_t ========
435 * Unified Clock System Control 2 Register
436 *
437 * @field(FLLD) FLL loop divider. These bits divide fDCOCLK in the FLL feedback loop. This results in an additional multiplier
438 * for the multiplier bits.
439 * @field(FLLN) Multiplier bits. These bits set the multiplier value N of the DCO. N must be greater than 0. Writing zero to
440 * FLLN causes N to be set to 1.
441 */
442 struct UCSCTL2_t {
443 FLLD_t FLLD; /*! FLL loop divider. These bits divide fDCOCLK in the FLL feedback loop. This results in an additional multiplier
444 * for the multiplier bits. See also multiplier bits.
445 * 000 fDCOCLK/1
446 * 001 fDCOCLK/2
447 * 010 fDCOCLK/4
448 * 011 fDCOCLK/8
449 * 100 fDCOCLK/16
450 * 101 fDCOCLK/32
451 * 110 Reserved for future use. Defaults to fDCOCLK/32
452 * 111 Reserved for future use. Defaults to fDCOCLK/32 */
453 FLLN0_t FLLN0; /*! Multiplier bit 0 */
454 FLLN1_t FLLN1; /*! Multiplier bit 1 */
455 FLLN2_t FLLN2; /*! Multiplier bit 2 */
456 FLLN3_t FLLN3; /*! Multiplier bit 3 */
457 FLLN4_t FLLN4; /*! Multiplier bit 4 */
458 FLLN5_t FLLN5; /*! Multiplier bit 5 */
459 FLLN6_t FLLN6; /*! Multiplier bit 6 */
460 FLLN7_t FLLN7; /*! Multiplier bit 7 */
461 FLLN8_t FLLN8; /*! Multiplier bit 8 */
462 FLLN9_t FLLN9; /*! Multiplier bit 9 */
463 }
464
465 /*!
466 * ======== UCSCTL3_t ========
467 * Unified Clock System Control 3 Register
468 *
469 * @field(SELREF) FLL reference select. These bits select the FLL reference clock source.
470 * @field(FLLREFDIV) FLL reference divider. These bits define the divide factor for fFLLREFCLK. The divided frequency is used as the
471 * FLL reference frequency.
472 */
473 struct UCSCTL3_t {
474 SELREF_t SELREF; /*! FLL reference select. These bits select the FLL reference clock source.
475 * 000 XT1CLK
476 * 001 Reserved for future use. Defaults to XT1CLK.
477 * 010 REFOCLK
478 * 011 Reserved for future use. Defaults to REFOCLK.
479 * 100 Reserved for future use. Defaults to REFOCLK.
480 * 101 XT2CLK when available, otherwise REFOCLK.
481 * 110 Reserved for future use. XT2CLK when available, otherwise REFOCLK.
482 * 111 No selection. For the 'F543x and 'F541x non-A versions only, this defaults to XT2CLK. Reserved for
483 * future use. XT2CLK when available, otherwise REFOCLK. */
484 FLLREFDIV_t FLLREFDIV; /*! FLL reference divider. These bits define the divide factor for fFLLREFCLK. The divided frequency is used as the
485 * FLL reference frequency.
486 * 000 fFLLREFCLK/1
487 * 001 fFLLREFCLK/2
488 * 010 fFLLREFCLK/4
489 * 011 fFLLREFCLK/8
490 * 100 fFLLREFCLK/12
491 * 101 fFLLREFCLK/16
492 * 110 Reserved for future use. Defaults to fFLLREFCLK/16.
493 * 111 Reserved for future use. Defaults to fFLLREFCLK/16. */
494 }
495
496 /*!
497 * ======== UCSCTL4_t ========
498 * Unified Clock System Control 4 Register
499 *
500 * @field(SELA) Selects the ACLK source
501 * @field(SELS) Selects the SMCLK source
502 * @field(SELM) Selects the MCLK source
503 */
504 struct UCSCTL4_t {
505 SELA_t SELA; /*! Selects the ACLK source
506 * 000 XT1CLK
507 * 001 VLOCLK
508 * 010 REFOCLK
509 * 011 DCOCLK
510 * 100 DCOCLKDIV
511 * 101 XT2CLK when available, otherwise DCOCLKDIV
512 * 110 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV.
513 * 111 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV. */
514 SELS_t SELS; /*! Selects the SMCLK source
515 * 000 XT1CLK
516 * 001 VLOCLK
517 * 010 REFOCLK
518 * 011 DCOCLK
519 * 100 DCOCLKDIV
520 * 101 XT2CLK when available, otherwise DCOCLKDIV
521 * 110 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV.
522 * 111 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV. */
523 SELM_t SELM; /*! Selects the MCLK source
524 * 000 XT1CLK
525 * 001 VLOCLK
526 * 010 REFOCLK
527 * 011 DCOCLK
528 * 100 DCOCLKDIV
529 * 101 XT2CLK when available, otherwise DCOCLKDIV
530 * 110 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV.
531 * 111 Reserved for future use. Defaults to XT2CLK when available, otherwise DCOCLKDIV. */
532 }
533
534 /*!
535 * ======== UCSCTL5_t ========
536 * Unified Clock System Control 5 Register
537 *
538 * @field(SELA) Selects the ACLK source
539 * @field(SELS) Selects the SMCLK source
540 * @field(SELM) Selects the MCLK source
541 */
542 struct UCSCTL5_t {
543 DIVPA_t DIVPA; /*! ACLK source divider available at external pin. Divides the frequency of ACLK and presents it to an external pin.
544 * 000 fACLK/1
545 * 001 fACLK/2
546 * 010 fACLK/4
547 * 011 fACLK/8
548 * 100 fACLK/16
549 * 101 fACLK/32
550 * 110 Reserved for future use. Defaults to fACLK/32.
551 * 111 Reserved for future use. Defaults to fACLK/32. */
552 DIVA_t DIVA; /*! ACLK source divider. Divides the frequency of the ACLK clock source.
553 * 000 fACLK/1
554 * 001 fACLK/2
555 * 010 fACLK/4
556 * 011 fACLK/8
557 * 100 fACLK/16
558 * 101 fACLK/32
559 * 110 Reserved for future use. Defaults to fACLK/32.
560 * 111 Reserved for future use. Defaults to fACLK/32. */
561 DIVS_t DIVS; /*! SMCLK source divider
562 * 000 fSMCLK/1
563 * 001 fSMCLK/2
564 * 010 fSMCLK/4
565 * 011 fSMCLK/8
566 * 100 fSMCLK/16
567 * 101 fSMCLK/32
568 * 110 Reserved for future use. Defaults to fSMCLK/32.
569 * 111 Reserved for future use. Defaults to fSMCLK/32. */
570 DIVM_t DIVM; /*! MCLK source divider
571 * 000 fMCLK/1
572 * 001 fMCLK/2
573 * 010 fMCLK/4
574 * 011 fMCLK/8
575 * 100 fMCLK/16
576 * 101 fMCLK/32
577 * 110 Reserved for future use. Defaults to fMCLK/32.
578 * 111 Reserved for future use. Defaults to fMCLK/32.*/
579 }
580
581 /*!
582 * ======== UCSCTL6_t ========
583 * Unified Clock System Control 6 Register
584 *
585 * @field(SELA) Selects the ACLK source
586 * @field(SELS) Selects the SMCLK source
587 * @field(SELM) Selects the MCLK source
588 */
589 struct UCSCTL6_t {
590 XT2DRIVE_t XT2DRIVE; /*! The XT2 oscillator current can be adjusted to its drive needs. Initially, it starts with the highest supply current
591 * for reliable and quick startup. If needed, user software can reduce the drive strength.
592 * 00 Lowest current consumption. XT2 oscillator operating range is 4 MHz to 8 MHz.
593 * 01 Increased drive strength XT2 oscillator. XT2 oscillator operating range is 8 MHz to 16 MHz.
594 * 10 Increased drive capability XT2 oscillator. XT2 oscillator operating range is 16 MHz to 24 MHz.
595 * 11 Maximum drive capability and maximum current consumption for both XT2 oscillator. XT2 oscillator
596 * operating range is 24 MHz to 32 MHz. */
597 XT2BYPASS_t XT2BYPASS; /*! XT2 bypass select
598 * 0 XT2 sourced internally
599 * 1 XT2 sourced externally from pin */
600 XT2OFF_t XT2OFF; /*! Turns off the XT2 oscillator
601 * 0 XT2 is on if XT2 is selected via the port selection and XT2 is not in bypass mode of operation.
602 * 1 XT2 is off if it is not used as a source for ACLK, MCLK, or SMCLK or is not used as a reference source
603 * required for FLL operation. */
604 XT1DRIVE_t XT1DRIVE; /*! The XT1 oscillator current can be adjusted to its drive needs. Initially, it starts with the highest supply current
605 * for reliable and quick startup. If needed, user software can reduce the drive strength.
606 * 00 Lowest current consumption for XT1 LF mode. XT1 oscillator operating range in HF mode is 4 MHz to
607 * 8 MHz.
608 * 01 Increased drive strength for XT1 LF mode. XT1 oscillator operating range in HF mode is 8 MHz to
609 * 16 MHz.
610 * 10 Increased drive capability for XT1 LF mode. XT1 oscillator operating range in HF mode is 16 MHz to
611 * 24 MHz.
612 * 11 Maximum drive capability and maximum current consumption for XT1 LF mode. XT1 oscillator operating
613 * range in HF mode is 24 MHz to 32 MHz. */
614 XTS_t XTS; /*! XT1 mode select
615 * 0 Low-frequency mode. XCAP bits define the capacitance at the XIN and XOUT pins.
616 * 1 High-frequency mode. XCAP bits are not used. */
617 XT1BYPASS_t XT1BYPASS; /*! XT1 bypass select
618 * 0 XT1 sourced internally
619 * 1 XT1 sourced externally from pin */
620 XCAP_t XCAP; /*! Oscillator capacitor selection. These bits select the capacitors applied to the LF crystal or resonator in the LF
621 * mode (XTS = 0). The effective capacitance (seen by the crystal) is Ceff (CXIN + 2 pF)/2. It is assumed that
622 * CXIN = CXOUT and that a parasitic capacitance of 2 pF is added by the package and the printed circuit board. For
623 * details about the typical internal and the effective capacitors, refer to the device-specific data sheet. */
624 SMCLKOFF_t SMCLKOFF; /*! SMCLK off. This bit turns off the SMCLK.
625 * 0 SMCLK on
626 * 1 SMCLK off */
627 XT1OFF_t XT1OFF; /*! XT1 off. This bit turns off the XT1.
628 * 0 XT1 is on if XT1 is selected via the port selection and XT1 is not in bypass mode of operation.
629 * 1 XT1 is off if it is not used as a source for ACLK, MCLK, or SMCLK or is not used as a reference source
630 * required for FLL operation. */
631 }
632
633 /*!
634 * ======== UCSCTL7_t ========
635 * Unified Clock System Control 7 Register
636 *
637 * @field(XT2OFFG) 0 No fault condition, 1 XT2 fault
638 * @field(XT1HFOFFG) 0 No fault condition, 1 XT1 HF fault
639 * @field(XT1LFOFFG) 0 No fault condition, 1 XT1 LF fault
640 * @field(DCOFFG) 0 No fault condition, 1 DCO fault
641 */
642 struct UCSCTL7_t {
643 XT2OFFG_t XT2OFFG; /*! XT2 oscillator fault flag. If this bit is set, the OFIFG flag is also set. XT2OFFG is set if a XT2 fault
644 * condition exists. XT2OFFG can be cleared via software. If the XT2 fault condition still remains,
645 * XT2OFFG is set.
646 * 0 No fault condition occurred after the last reset.
647 * 1 XT2 fault. An XT2 fault occurred after the last reset. */
648 XT1HFOFFG_t XT1HFOFFG; /*! XT1 oscillator fault flag (HF mode). If this bit is set, the OFIFG flag is also set. XT1HFOFFG is set if a
649 * XT1 fault condition exists. XT1HFOFFG can be cleared via software. If the XT1 fault condition still
650 * remains, XT1HFOFFG is set.
651 * 0 No fault condition occurred after the last reset.
652 * 1 XT1 fault. An XT1 fault occurred after the last reset. */
653 XT1LFOFFG_t XT1LFOFFG; /*! XT1 oscillator fault flag (LF mode). If this bit is set, the OFIFG flag is also set. XT1LFOFFG is set if a
654 * XT1 fault condition exists. XT1LFOFFG can be cleared via software. If the XT1 fault condition still
655 * remains, XT1LFOFFG is set.
656 * 0 No fault condition occurred after the last reset.
657 * 1 XT1 fault (LF mode). A XT1 fault occurred after the last reset. */
658 DCOFFG_t DCOFFG; /*! DCO fault flag. If this bit is set, the OFIFG flag is also set. The DCOFFG bit is set if DCO = {0} or
659 * DCO = {31}. DCOFFG can be cleared via software. If the DCO fault condition still remains, DCOFFG is
660 * set.
661 * 0 No fault condition occurred after the last reset.
662 * 1 DCO fault. A DCO fault occurred after the last reset. */
663 }
664
665 /*!
666 * ======== UCSCTL8_t ========
667 * Unified Clock System Control 8 Register
668 *
669 * @field(MODOSCREQEN) 0 MODOSC conditional requests are disabled
670 * 1 MODOSC conditional requests are enabled
671 * @field(SMCLKREQEN) 0 SMCLK conditional requests are disabled
672 * 1 SMCLK conditional requests are enabled
673 * @field(MCLKREQEN) 0 MCLK conditional requests are disabled
674 * 1 MCLK conditional requests are enabled
675 * @field(ACLKREQEN) 0 ACLK conditional requests are disabled
676 * 1 ACLK conditional requests are enabled
677 */
678 struct UCSCTL8_t {
679 MODOSCREQEN_t MODOSCREQEN; /*! MODOSC clock request enable. Setting this enables conditional module requests for MODOSC.
680 * 0 MODOSC conditional requests are disabled.
681 * 1 MODOSC conditional requests are enabled. */
682 SMCLKREQEN_t SMCLKREQEN; /*! SMCLK clock request enable. Setting this enables conditional module requests for SMCLK.
683 * 0 SMCLK conditional requests are disabled.
684 * 1 SMCLK conditional requests are enabled. */
685 MCLKREQEN_t MCLKREQEN; /*! MCLK clock request enable. Setting this enables conditional module requests for MCLK
686 * 0 MCLK conditional requests are disabled.
687 * 1 MCLK conditional requests are enabled. */
688 ACLKREQEN_t ACLKREQEN; /*! ACLK clock request enable. Setting this enables conditional module requests for ACLK
689 * 0 ACLK conditional requests are disabled.
690 * 1 ACLK conditional requests are enabled. */
691 }
692
693 /*!
694 * ======== UCSCTL9_t ========
695 * Unified Clock System Control 9 Register
696 *
697 * @field(XT2BYPASSLV) 0 Input range from 0 to DVCC
698 * 1 Input range from 0 to DVIO
699 * @field(XT1BYPASSLV) 0 Input range from 0 to DVCC
700 * 1 Input range from 0 to DVIO
701 */
702 struct UCSCTL9_t {
703 XT2BYPASSLV_t XT2BYPASSLV; /*! Selects XT2 bypass input swing level. Must be set for reduced swing operation.
704 * 0 Input range from 0 to DVCC
705 * 1 Input range from 0 to DVIO */
706 XT1BYPASSLV_t XT1BYPASSLV; /*! Selects XT1 bypass input swing level. Must be set for reduced swing operation.
707 * 0 Input range from 0 to DVCC
708 * 1 Input range from 0 to DVIO */
709 }
710
711 712 713
714 /*! Select the clock source */
715 enum UCS_CLK_SOURCE_t {
716 UCS_XT1CLK_SELECT = 0x0000, /*! XT1CLK */
717 UCS_VLOCLK_SELECT = 0x0010, /*! VLOCLK */
718 UCS_REFOCLK_SELECT = 0x0020, /*! REFOCLK */
719 UCS_DCOCLK_SELECT = 0x0030, /*! DCOCLK */
720 UCS_DCOCLKDIV_SELECT = 0x0040, /*! DCOCLKDIV */
721 UCS_XT2CLK_SELECT = 0x0050 /*! XT2CLK */
722 };
723
724 /*! Select clock source divider */
725 enum UCS_CLK_SRC_DIVIDER_t {
726 UCS_CLOCK_DIVIDER_1 = 0x0000, /*! Divide by 1 */
727 UCS_CLOCK_DIVIDER_2 = 0x0010, /*! Divide by 2 */
728 UCS_CLOCK_DIVIDER_4 = 0x0020, /*! Divide by 4 */
729 UCS_CLOCK_DIVIDER_8 = 0x0030, /*! Divide by 8 */
730 UCS_CLOCK_DIVIDER_12 = 0x0040, /*! Divide by 12 */
731 UCS_CLOCK_DIVIDER_16 = 0x0050, /*! Divide by 16 */
732 UCS_CLOCK_DIVIDER_32 = 0x0060 /*! Divide by 32 */
733 };
734
735 /*! XT1 oscillator capacitor select */
736 enum UCS_XCAP_t {
737 UCS_XCAP_0 = 0x0000, /*! ~ 2 pF */
738 UCS_XCAP_1 = 0x0004, /*! ~ 5.5 pF */
739 UCS_XCAP_2 = 0x0008, /*! ~ 8.5 pF */
740 UCS_XCAP_3 = 0x000C /*! ~ 12 pF */
741 };
742
743 instance:
744
745 /*! Unified Clock System Control 0 Register */
746 config UCSCTL0_t UCSCTL0 = {
747 DCO0 : DCO0_OFF,
748 DCO1 : DCO1_OFF,
749 DCO2 : DCO2_OFF,
750 DCO3 : DCO3_OFF,
751 DCO4 : DCO4_OFF,
752 MOD0 : MOD0_OFF,
753 MOD1 : MOD1_OFF,
754 MOD2 : MOD2_OFF,
755 MOD3 : MOD3_OFF,
756 MOD4 : MOD4_OFF,
757 };
758
759 /*! Unified Clock System Control 1 Register */
760 config UCSCTL1_t UCSCTL1 = {
761 DCORSEL : DCORSEL_2,
762 DISMOD : DISMOD_OFF,
763 };
764
765 /*! Unified Clock System Control 2 Register */
766 config UCSCTL2_t UCSCTL2 = {
767 FLLD : FLLD_1,
768 FLLN0 : FLLN0,
769 FLLN1 : FLLN1,
770 FLLN2 : FLLN2,
771 FLLN3 : FLLN3,
772 FLLN4 : FLLN4,
773 FLLN5 : FLLN5_OFF,
774 FLLN6 : FLLN6_OFF,
775 FLLN7 : FLLN7_OFF,
776 FLLN8 : FLLN8_OFF,
777 FLLN9 : FLLN9_OFF,
778 };
779
780 /*! Unified Clock System Control 3 Register */
781 config UCSCTL3_t UCSCTL3 = {
782 SELREF : SELREF_0,
783 FLLREFDIV : FLLREFDIV_0,
784 };
785
786 /*! Unified Clock System Control 4 Register */
787 config UCSCTL4_t UCSCTL4 = {
788 SELA : SELA_0,
789 SELS : SELS_4,
790 SELM : SELM_4,
791 };
792
793 /*! Unified Clock System Control 5 Register */
794 config UCSCTL5_t UCSCTL5 = {
795 DIVPA : DIVPA_0,
796 DIVA : DIVA_0,
797 DIVS : DIVS_0,
798 DIVM : DIVM_0,
799 };
800
801 /*! Unified Clock System Control 6 Register */
802 config UCSCTL6_t UCSCTL6 = {
803 XT2DRIVE : XT2DRIVE_3,
804 XT2BYPASS : XT2BYPASS_OFF,
805 XT2OFF : XT2OFF,
806 XT1DRIVE : XT1DRIVE_3,
807 XTS : XTS,
808 XT1BYPASS : XT1BYPASS,
809 XCAP : XCAP_3,
810 SMCLKOFF : SMCLKOFF_OFF,
811 XT1OFF : XT1OFF,
812 };
813
814 /*! Unified Clock System Control 7 Register */
815 config UCSCTL7_t UCSCTL7 = {
816 XT2OFFG : XT2OFFG_OFF,
817 XT1HFOFFG : XT1HFOFFG_OFF,
818 XT1LFOFFG : XT1LFOFFG,
819 DCOFFG : DCOFFG,
820 };
821
822 /*! Unified Clock System Control 8 Register */
823 config UCSCTL8_t UCSCTL8 = {
824 MODOSCREQEN : MODOSCREQEN_OFF,
825 SMCLKREQEN : SMCLKREQEN,
826 MCLKREQEN : MCLKREQEN,
827 ACLKREQEN : ACLKREQEN,
828 };
829
830 /*! Unified Clock System Control 9 Register */
831 config UCSCTL9_t UCSCTL9 = {
832 XT2BYPASSLV : XT2BYPASSLV_OFF,
833 XT1BYPASSLV : XT1BYPASSLV_OFF,
834 };
835
836 /*! MCLK clock source select */
837 config UCS_CLK_SOURCE_t UCS_MCLK_SOURCE = UCS_DCOCLKDIV_SELECT;
838
839 /*! SMCLK clock source select */
840 config UCS_CLK_SOURCE_t UCS_SMCLK_SOURCE = UCS_DCOCLKDIV_SELECT;
841
842 /*! ACLK clock source select */
843 config UCS_CLK_SOURCE_t UCS_ACLK_SOURCE = UCS_XT1CLK_SELECT;
844
845 /*! FLL reference clock source select */
846 config UCS_CLK_SOURCE_t UCS_FLL_REF_CLK_SOURCE = UCS_XT1CLK_SELECT;
847
848 /*! MCLK clock source divider select */
849 config UCS_CLK_SRC_DIVIDER_t UCS_MCLK_SRC_DIVIDER = UCS_CLOCK_DIVIDER_1;
850
851 /*! SMCLK clock source divider select */
852 config UCS_CLK_SRC_DIVIDER_t UCS_SMCLK_SRC_DIVIDER = UCS_CLOCK_DIVIDER_1;
853
854 /*! ACLK clock source divider select */
855 config UCS_CLK_SRC_DIVIDER_t UCS_ACLK_SRC_DIVIDER = UCS_CLOCK_DIVIDER_1;
856
857 /*! External pin ACLK clock source divider select */
858 config UCS_CLK_SRC_DIVIDER_t UCS_PACLK_SRC_DIVIDER = UCS_CLOCK_DIVIDER_1;
859
860 /*! FLL reference clock source divider select */
861 config UCS_CLK_SRC_DIVIDER_t UCS_FLL_REF_SRC_DIVIDER = UCS_CLOCK_DIVIDER_1;
862
863 /*! FLLN value */
864 config UInt UCS_FLL_RATIO = 31;
865
866 /*! Set FLL target frequency */
867 config Float UCS_FLL_FREQ = 0;
868
869 /*! Set XT1 drive strength */
870 config XT1DRIVE_t UCS_XT1_DRIVE = XT1DRIVE_3;
871
872 /*! Set XT2 drive strength */
873 config XT2DRIVE_t UCS_XT2_DRIVE = XT2DRIVE_3;
874
875 /*! Set oscillator capacitor. Available only in LF mode. See device-specific datasheet for actual values. */
876 config UCS_XCAP_t UCS_XCAP = UCS_XCAP_3;
877
878 /*! Set XT1 in bypass mode. The frequency input at XIN1 pin requires 0 to VCC. */
879 config Bool UCS_XT1BYPASS = false;
880
881 /*! Set XT2 in bypass mode. The frequency input at XIN2 pin requires 0 to VCC. */
882 config Bool UCS_XT2BYPASS = false;
883
884 /*! MODOSC clock request enable. Setting this enables conditional module requests for MODOSC.
885 * 0 MODOSC conditional requests are disabled.
886 * 1 MODOSC conditional requests are enabled. */
887 config MODOSCREQEN_t UCS_MODOSCREQEN = MODOSCREQEN_OFF;
888
889 /*! SMCLK clock request enable. Setting this enables conditional module requests for SMCLK.
890 * 0 SMCLK conditional requests are disabled.
891 * 1 SMCLK conditional requests are enabled. */
892 config SMCLKREQEN_t UCS_SMCLKREQEN = SMCLKREQEN;
893
894 /*! MCLK clock request enable. Setting this enables conditional module requests for MCLK
895 * 0 MCLK conditional requests are disabled.
896 * 1 MCLK conditional requests are enabled. */
897 config MCLKREQEN_t UCS_MCLKREQEN = MCLKREQEN;
898
899 /*! ACLK clock request enable. Setting this enables conditional module requests for ACLK
900 * 0 ACLK conditional requests are disabled.
901 * 1 ACLK conditional requests are enabled. */
902 config ACLKREQEN_t UCS_ACLKREQEN = ACLKREQEN;
903
904 /*! Turns OFF SMCLK using the SMCLKOFF bit
905 * 0 SMCLK On
906 * 1 SMCLK Off */
907 config Bool UCS_SMCLKOFF = false;
908
909 /*!
910 * UCS base address
911 */
912 config String baseAddress = "__MSP430_BASEADDRESS_UCS__";
913
914 config Float VLOCLKHz = 12000;
915 config Float WATCHCRYSTALCLKHz = 32768;
916 config Float REFOCLKHz = 32768;
917 config Float XT1CLKHz = 0;
918 config Float XT2CLKHz = 0;
919
920 /*!
921 * ======== DCOCLKDIVHz ========
922 * Divided DCO clock frequency in Hertz
923 */
924 readonly config Float DCOCLKDIVHz;
925
926 /*! Determine if each Register needs to be forced set or not */
927 readonly config ForceSetDefaultRegister_t forceSetDefaultRegister[] =
928 [
929 { register : "UCS_SMCLKREQEN" , regForceSet : false },
930 { register : "UCS_MCLKREQEN" , regForceSet : false },
931 { register : "UCS_ACLKREQEN" , regForceSet : false },
932 { register : "UCS_MODOSCREQEN" , regForceSet : false }
933 ];
934 }