5.8. PORT Module

5.8.1. Acronyms and Definitions

Abbreviation/Term

Explanation

AUTOSAR

Automotive Open System Architecture

RTE

Runtime Environment

BSW

Basic Software

GPIO

General Purpose Input Output

MCAL

Micro Controller Abstraction Layer

API

Application Programming Interface

DET

Default Error Tracer

HW

Hardware

SW

Software

I/O

Input/Output

5.8.2. Introduction

The Port driver module is an I/O driver in AUTOSAR Basic Software (BSW) layer. PORT driver provide the services for initializing the whole PORT structure of the microcontroller. It is used to assign various functionalities to Port and port pins (e.g. GPIOs, ADC, SPI and other peripheral modes)

PORT MCAL AUTOSAR

Fig. 5.26 PORT MCAL AUTOSAR

This document details AUTOSAR BSW PORT module implementation

Supported AUTOSAR Release

4.3.1

Supported Configuration Variants

Pre-Compile & Post Build

Vendor ID

PORT_VENDOR_ID (44)

Module ID

PORT_MODULE_ID (124)

5.8.3. Functional Overview

The Port module shall provide the service for initializing the whole PORT structure of the microcontroller. Many ports and port pins can be assigned to various functionalities, For e.g.

  • General purpose I/O

  • CAN

  • SPI

  • ADC

  • LIN etc

Up to twelve independent peripheral signals are multiplexed on a single GPIO-enabled pin in addition to the CPU-controlled I/O capability. Each pin output can be controlled by either a peripheral or one of the CPU controllers. PORT driver module shall complete the overall configuration and initialization of the port structure which is used in other dependent driver modules. Therefore, other dependent modules driver works on pins and ports which are configured by the PORT driver. Hence PORT driver shall be initialized prior to use of other driver modules functions. Otherwise those functions might exhibit undefined behavior.

5.8.4. Hardware Features

5.8.4.1. Hardware Features supported

Features Supported at a high level are:

  • Configure each port and port pin (Input/Output, Pin driver characteristics).

  • Set pins to an initial default value.

  • Refresh the direction of the initial configuration.

  • Switch the port pin configuration during runtime.

  • Pin direction changeable during runtime.

  • Port mode changeable during runtime.

5.8.4.1.1. Port Structure

For the device there are up to 8 Possible I/O Ports. Up to twelve independent peripheral signals are multiplexed on a single GPIO-enabled pin in addition to the CPU-controlled I/O capability.

Each pin output can be controlled by either a peripheral or one of the CPU controllers.

Port

GPIO Number

Port ID

Port A

0 - 31

0

Port B

32 - 63

1

Port C

64 - 95

2

Port D

96 - 127

3

Port E

128 - 159

4

Port F

160 - 191

5

Port G

192 - 223

6

Port H

224 - 255

7

5.8.4.1.2. AIOs

Some GPIOs are multiplexed with analog pins and only have digital input functionality. These are also referred to as AIOs. Pins with only an AIO option on this port can only function in input mode. See the device data sheet for list of AIO signals. By default, these pins function as analog pins and the GPIOs are in a high-impedance state.

5.8.4.1.3. AGPIOs

Some GPIOs are multiplexed with analog pins and have digital input and output functionality. These are also referred to as AGPIOs. Unlike AIOs, AGPIOs have full input and output capability. By default, the AGPIOs are not connected and must be configured.

5.8.4.1.4. Input Qualification

The input qualification scheme has been designed to be very flexible. Input qualification can be configured by user using the configurator tool. In the case of a GPIO input pin, the qualification can be specified as only synchronized to SYSCLKOUT or qualification by a sampling window. For pins that are configured as peripheral inputs, the input can also be asynchronous in addition to synchronized to SYSCLKOUT or qualified by a sampling window. The remainder of this section describes the options available.

  • No Synchronization (Asynchronous Input) : This mode is used for peripherals where input synchronization is not required or the peripheral itself performs the synchronization. Examples include communication ports McBSP, SCI, SPI, and I2C. In addition, the ePWM trip zone (TZn) signals can function independent of the presence of SYSCLKOUT

  • Synchronization to SYSCLKOUT Only : This is the default qualification mode of all the pins at reset. In this mode, the input signal is only synchronized to the system clock (SYSCLKOUT). Because the incoming signal is asynchronous, a SYSCLKOUT period of delay is needed for the input to the device to be changed. No further qualification is performed on the signal.

  • Qualification Using a Sampling Window : In this mode, the signal is first synchronized to the system clock (SYSCLKOUT) and then qualified by a specified number of cycles before the input is allowed to change. Two parameters are specified by the user for this type of qualification: (1) the sampling period, or how often the signal is sampled, and (2) the number of samples to be taken.

Note

Using input synchronization when the peripheral itself performs the synchronization can cause unexpected results. The user must make sure that the GPIO pin is configured for asynchronous in this case.

5.8.4.1.5. GPIO and Peripheral Muxing

Up to twelve different peripheral functions are multiplexed to each pin along with a general-purpose input/output (GPIO) function. This allows user to choose the peripheral mix and pinout that works best for your particular application.

Note

Available Pin Packages: Port Driver needs to be initialized as per the available pin package. Refer Device Data Sheet for details about available pin packages.

5.8.4.2. Not supported Features

  • Out of total number of available pins for a particular pin package, there are few reserved/not configurable pins.

Note

Refer Device Data Sheet for details about reserved/non-configurable pins for the respective pin package.

  • Lock Configuration and Lock Commit configuration as not supported for the module

5.8.4.3. Non compliance

Below AUTOSAR design requirements are not supported/partially supported for Port Driver :
SWS_Port_00205 : Port_Lcfg.c shall include Port_MemMap.h and Port.h

Rejection Reason : Port Driver doesn’t have any Link Time configuration input file, it only supports Pre-Compile and Port-Build configurations.

ECUC_Port_00127 : Pin Id of the port pin. Range : 1 .. 65535

Partial Non Compliance Reason : In current implementation, Pin Id range starts from 0 instead of 1 as mapping of Pin Id to GPIOs starts from 0. Therefore Port Pin Id Range is 0 to Number of Pins in Pin package. i.e for 256 pin package , range will be 0-255.

SWS_BSW_00042 : Detection of Development Errors: The detection and reporting of Development errors shall be performed only if the configuration parameter for detection of Development errors is set

Partial Non Compliance Reason : Few Null pointer input parameter checks are needed irrespective of Development errors is set, to handle MISRA requirement.

For more details, Refer AUTOSAR_SWS_PortDriver : Section: 5.1.2 : Header File Structure

5.8.5. Source files

📦f29h85x_mcal
┣ 📂build
┣ 📂docs
┣ 📂drivers
┃ ┣ 📂BSW_Stubs
┃ ┣ 📂Can
┃ ┣ 📂Dio
┃ ┣ 📂Gpt
┃ ┣ 📂hw_include
┃ ┣ 📂Mcal_Lib
┃ ┣ 📂Mcu
┃ ┗ 📂Port
┃ ┃ ┣ 📂include
┃ ┃ ┃ ┣ 📜Port.h : Contains the API declarations of the Port driver to be used by upper layers.
┃ ┃ ┃ ┣ 📜Port_Pin_Map.h : Contains the MACROs to define GPIO MUX values.
┃ ┃ ┃ ┗ 📜Port_Priv.h : Contains data structures and Internal function declarations.
┃ ┃ ┣ 📂src
┃ ┃ ┃ ┣ 📜Port.c : Contains the implementation of the API for Port driver.
┃ ┃ ┃ ┗ 📜Port_Priv.c : Contains Functions that support the API for Port driver
┃ ┃ ┗ 📜CMakeLists.txt
┣ 📂examples
┣ 📂plugins
┣ 📜CMakeLists.txt
┗ 📜CMakePresets.json

Port Header File Structure

Fig. 5.27 Port Header File Structure

5.8.6. Module requirements

5.8.6.1. Memory Mapping

The driver follows the AUTOSAR memory mapping strategy. All memory sections should be stored in memory as per AUTOSAR specifications, considering initialization policy, alignment requirements, safety classification, and core scope where applicable.

Reference memory map files can be found at:

{MCAL_INSTALL_PATH}\drivers\BSW_Stubs\MemMap\include

The memory sections are organized according to AUTOSAR specifications to ensure proper placement of code and data in different memory regions based on their usage and access patterns.

5.8.6.2. Scheduling

None

5.8.6.3. Error handling

5.8.6.3.1. Development Error Reporting

Development errors are reported to the DET using the service Det_ReportError(), when enabled. The driver interface contains the MACRO declaration of the error codes to be returned.

5.8.6.4. Error codes

Type of Error

Related Error code

Value (Hex)

Invalid Port Pin ID requested.

PORT_E_PARAM_PIN

0x0A

Port Pin not configured as changeable.

PORT_E_DIRECTION_UNCHANGEABLE

0x0B

API Port_Init service called with wrong parameter.

PORT_E_INIT_FAILED

0x0C

API Port_SetPinMode service called when mode is unchangeable. Invalid Mode Passed

PORT_E_PARAM_INVALID_MODE

0x0D

API Port_SetPinMode service called when mode is unchangeable.

PORT_E_MODE_UNCHANGEABLE

0x0E

API service called without module initialization.

PORT_E_UNINIT

0x0F

API called with a Null Pointer.

PORT_E_PARAM_POINTER

0x10

5.8.7. Safety Mechanism

TI Diagnostic Unique Identifier

Summary

Description

GPIO1

Lock Mechanism for Control Registers

Port Pins Pad control register configuration can be locked and locked configurations can be committed. If user calls Port_Init or Port_SetPinMode APIs after committing the locked configuration, it will result in DET error PORT_E_INIT_FAILED or PORT_PIN_MODE_UNCHANGEABLE respectively

Note

Locked Configurations can be committed by user during runtime. After committing the configurations, user won’t be able to change the configurations during runtime. To change the configuration after committing, hard reset will be required. More details of Safety Mechanisms can be found in Safety Manual.

5.8.8. Used resources

5.8.8.1. Interrupt Handling

There are no Interrupts in Port

5.8.8.2. Instance support

CPU instances

supported

CPU 1

YES

CPU 2

NO

CPU 3

NO

5.8.8.3. Hardware-Software Mapping

Below image shows Port driver Hardware-Software mapping. For more information related to HW/SW mapping, refer the F29x Reference Manual.

Port HW/SW Mapping

Fig. 5.28 Port HW/SW Mapping

5.8.9. Integration description

5.8.9.1. Dependent modules

5.8.9.1.1. DET

This implementation depends on the DET in order to report development errors The detection of development errors is configurable (ON / OFF), The switch PORT_DEV_ERROR_DETECT will activate or deactivate the detection of all development errors.

5.8.9.1.2. SchM

If multiple AUTOSAR runnables have access to the same Data Store Memory block, the exported AUTOSAR specification enforces data consistency by using an AUTOSAR exclusive area. With this specification, the runnables have mutually exclusive access to the per-instance memory global data, which prevents data corruption. Beside the OS, the BSW Scheduler provides functions that PORT module calls at begin and end of critical sections. This implementation requires 1 level of exclusive access to guard critical sections.

The data consistency mechanism that has to be applied to an ExclusiveArea might be domain, ECU or even project specific. The decision which mechanism has to be applied by RTE / Basic Software Scheduler is taken during ECU integration by setting the Exclusive Area configuration parameter RteExclusiveAreaImplMechanism. This parameter is an input for RTE generator.
For Port Module, data consistency and exclusive access to critical sections are required for the following sections as shown in the table below:

Exclusive Area Functions used

Port Function calling Exclusive Area

Need for Exclusive Area

Recommended Exclusive Area Mapping

PORT_EXCLUSIVE_AREA_0

Port_SetPinDirection
Port_RefreshPortDirection
Port_SetPinMode

To protect against multiple access for shared resources, i.e. GPIO Data and Mode Registers, which can lead to race condition

OS_RESOURCE : If the Port APIs are only called from pre-emptible task context, its recommended to use this mechanism as it takes care of resource access protection and task priority management.
None: If Port APIs are only called from non pre-emptible task context or during init, its recommended to use this mechanism as multiple access protection to shared resource is not needed.

5.8.9.1.3. MCU

MCU Module is required to initialize all the clock to be used by different peripherals

5.8.9.2. Resource Allocator Integration

The Port module integrates with the Resource Allocator plugin to determine available pin configurations based on the selected device, package, and variant.

How Port Uses Resource Allocator:

  1. Device Selection: The Resource Allocator configuration specifies the target device family (F29H85x, F29P32x, or F29P58x)

  2. Package Selection: The selected pin package (e.g., 256-pin, 176-pin, 144-pin) determines which GPIO pins are physically available

  3. Variant Selection: The device variant may affect available pin functionalities

Configuration Dependency:

When configuring the Port module in EB Tresos:

  • The Resource Allocator plugin must be added and configured first

  • The Port plugin reads the device and package information from Resource Allocator

  • Available pin options in PortPinName and PortPinPeripheralSignal are filtered based on the selected package

  • Only pins that exist on the selected package variant are shown as configurable options

Multi-core Consideration:

On F29H85x, PinMux configuration can only be performed from CPU1. Therefore, the Port module running on CPU1 sets the PinMux settings for all GPIO pins used across all CPU cores in the system. The PortPinCoreSelect parameter in the Port configuration specifies which CPU core owns each pin, but the actual PinMux register writes are always performed by CPU1.

Benefits:

  • Prevents configuration of pins that don’t exist on the target package

  • Automatically filters peripheral mux options based on device capabilities

  • Ensures generated configuration matches the physical device

Note

The Resource Allocator plugin must be configured before the Port plugin to ensure correct pin availability filtering. Refer to the Resource Allocator Module User Guide for configuration details.

5.8.10. Configuration

The Port Driver implementation supports multiple configuration variants, namely Port Post-Build config and Pre-Compile config. The driver expects generated Port_cfg.h to be present as input file. The associated Port driver configuration generated source files are Port_Cfg.c or Port_PBcfg.c

The generated configuration files should not be modified manually. The config tool Elektrobit Tresos should be used to modify the configuration files.

Note

Refer section Getting Started with EB Tresos of Chapter MCAL Configuration and EB Tresos for more information on how to load plugin and generate the configuration files.

5.8.10.1. Configuration Parameters

5.8.10.1.1. PortConfigSet

This container contains the configuration parameters and sub containers of the AUTOSAR Port module.

5.8.10.1.1.1. PortContainer

Container collecting the PortPins.

5.8.10.1.1.2. PortNumberOfPortPins

Item

Name

PortNumberOfPortPins

Description

The number of specified PortPins in this PortContainer.

Origin

AUTOSAR_ECUC

Post-Build-Variant-Value

false

Value-Configuration-Class

Post-Build-Time

VARIANT-POST-BUILD

Pre-Compile-Time

VARIANT-PRE-COMPILE

Default-value

1

Max-value

256

Min-value

1

5.8.10.1.1.3. PortPin

Configuration of the individual port pins.

5.8.10.1.1.4. PortPinPeripheral

Item

Name

PortPinPeripheral

Description

Available Peripherals for the pin package

Origin

Texas Instruments

Post-Build-Variant-Value

false

Value-Configuration-Class

Post-Build-Time

VARIANT-POST-BUILD

Pre-Compile-Time

VARIANT-PRE-COMPILE

Default-value

ADC_EXTMUXSEL

Range

ADC_EXTMUXSEL
AIO
ANALOG
EPWM
FSIRX
FSITX
GPIO
I2C
JTAG
LIN
MCAN
OTHER
OUTPUTXBAR
PMBUS
SD
SENT
SPI
UART
XTAL

5.8.10.1.1.5. PortPinPeripheralInstance

Item

Name

PortPinPeripheralInstance

Description

Available instances for the Peripheral selected

Origin

Texas Instruments

Post-Build-Variant-Value

false

Value-Configuration-Class

Post-Build-Time

VARIANT-POST-BUILD

Pre-Compile-Time

VARIANT-PRE-COMPILE

Default-value

ADCA_EXTMUXSEL

Range

ADCA_EXTMUXSEL
ADCB_EXTMUXSEL
ADCC_EXTMUXSEL
ADCD_EXTMUXSEL
ADCE_EXTMUXSEL
AIO160
AIO161
AIO162
AIO163
AIO164
AIO165
AIO166
AIO167
AIO168
AIO169
AIO170
AIO171
AIO172
AIO173
AIO174
AIO175
AIO176
AIO177
AIO178
AIO179
AIO180
AIO181
AIO182
AIO183
AIO184
AIO185
AIO186
AIO187
AIO188
AIO189
AIO190
AIO191
AIO192
AIO193
AIO194
AIO195
AIO196
AIO197
AIO198
AIO199
AIO200
AIO201
AIO202
AIO203
AIO204
AIO205
AIO206
AIO207
AIO208
AIO209
AIO210
AIO211
AIO212
AIO213
ANALOG
EPWM1
EPWM10
EPWM11
EPWM12
EPWM13
EPWM14
EPWM15
EPWM16
EPWM17
EPWM18
EPWM2
EPWM3
EPWM4
EPWM5
EPWM6
EPWM7
EPWM8
EPWM9
FSIRXA
FSIRXB
FSIRXC
FSIRXD
FSITXA
FSITXB
FSITXC
FSITXD
GPIO0
GPIO1
GPIO10
GPIO100
GPIO101
GPIO103
GPIO105
GPIO11
GPIO12
GPIO127
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO2
GPIO20
GPIO21
GPIO219
GPIO22
GPIO220
GPIO221
GPIO222
GPIO223
GPIO224
GPIO225
GPIO226
GPIO227
GPIO228
GPIO229
GPIO23
GPIO230
GPIO231
GPIO232
GPIO233
GPIO234
GPIO235
GPIO236
GPIO237
GPIO238
GPIO239
GPIO24
GPIO240
GPIO241
GPIO242
GPIO243
GPIO244
GPIO245
GPIO246
GPIO247
GPIO248
GPIO249
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO3
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO39
GPIO4
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO48
GPIO49
GPIO5
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55
GPIO56
GPIO57
GPIO58
GPIO59
GPIO6
GPIO60
GPIO61
GPIO62
GPIO63
GPIO64
GPIO65
GPIO66
GPIO67
GPIO68
GPIO69
GPIO7
GPIO70
GPIO71
GPIO72
GPIO73
GPIO74
GPIO75
GPIO76
GPIO77
GPIO78
GPIO79
GPIO8
GPIO80
GPIO81
GPIO82
GPIO83
GPIO84
GPIO85
GPIO86
GPIO87
GPIO88
GPIO89
GPIO9
GPIO90
GPIO91
GPIO92
GPIO93
GPIO94
GPIO95
GPIO96
GPIO97
GPIO98
GPIO99
I2CA
I2CB
INPUTXBAR
JTAG
LINA
LINB
MCANA
MCANB
MCANC
MCAND
MCANE
MCANF
OTHER
OUTPUTXBAR1
OUTPUTXBAR10
OUTPUTXBAR11
OUTPUTXBAR12
OUTPUTXBAR13
OUTPUTXBAR14
OUTPUTXBAR15
OUTPUTXBAR16
OUTPUTXBAR2
OUTPUTXBAR3
OUTPUTXBAR4
OUTPUTXBAR5
OUTPUTXBAR6
OUTPUTXBAR7
OUTPUTXBAR8
OUTPUTXBAR9
PMBUSA
SD1
SD2
SD3
SD4
SENT1
SENT2
SENT3
SENT4
SENT5
SENT6
SPIA
SPIB
SPIC
SPID
SPIE
UARTA
UARTB
UARTC
UARTD
UARTE
UARTF
XTAL

5.8.10.1.1.6. PortPinPeripheralSignal

Item

Name

PortPinPeripheralSignal

Description

Select specific type of peripheral signal pin of interest

Origin

Texas Instruments

Post-Build-Variant-Value

false

Value-Configuration-Class

Post-Build-Time

VARIANT-POST-BUILD

Pre-Compile-Time

VARIANT-PRE-COMPILE

Default-value

A0_C24_DACA_OUT

Range

A0_C24_DACA_OUT
A10_GPIO228
A11_GPIO229
A12
A13
A14_B14_C14_D14_E14
A15_B15_C15_D15_E15
A1_C25
A2_D24
A3_D25
A4_D28
A5_D29
A6_E24_GPIO224
A7_E25_GPIO225
A8_GPIO226
A9_GPIO227
ADCA_EXTMUXSEL0
ADCA_EXTMUXSEL1
ADCA_EXTMUXSEL2
ADCA_EXTMUXSEL3
ADCB_EXTMUXSEL0
ADCB_EXTMUXSEL1
ADCB_EXTMUXSEL2
ADCB_EXTMUXSEL3
ADCC_EXTMUXSEL0
ADCC_EXTMUXSEL1
ADCC_EXTMUXSEL2
ADCC_EXTMUXSEL3
ADCD_EXTMUXSEL0
ADCD_EXTMUXSEL1
ADCD_EXTMUXSEL2
ADCD_EXTMUXSEL3
ADCE_EXTMUXSEL0
ADCE_EXTMUXSEL1
ADCE_EXTMUXSEL2
ADCE_EXTMUXSEL3
ADCSOCAO
ADCSOCBO
AIO160
AIO161
AIO162
AIO163
AIO164
AIO165
AIO166
AIO167
AIO168
AIO169
AIO170
AIO171
AIO172
AIO173
AIO174
AIO175
AIO176
AIO177
AIO178
AIO179
AIO180
AIO181
AIO182
AIO183
AIO184
AIO185
AIO186
AIO187
AIO188
AIO189
AIO190
AIO191
AIO192
AIO193
AIO194
AIO195
AIO196
AIO197
AIO198
AIO199
AIO200
AIO201
AIO202
AIO203
AIO204
AIO205
AIO206
AIO207
AIO208
AIO209
AIO210
AIO211
AIO212
AIO213
B0_C26_VDAC
B10_GPIO234
B11_GPIO235
B12
B13
B16
B17
B1_C27
B2_D26
B3_D27
B4_D30
B5_D31
B6_E26_GPIO230
B7_E27_GPIO231
B8_GPIO232
B9_GPIO233
C0_E28
C10
C11
C12
C13
C16
C17
C1_E29
C2_E30
C3_E31
C4
C5
C6_GPIO236
C7_GPIO237
C8_GPIO238
C9_GPIO239
D0_B24
D10
D11
D12
D13
D16
D17
D1_B25
D2_B26
D3_B27
D4_B28_GPIO240
D5_B29_GPIO241
D6_B30_GPIO242
D7_B31_GPIO243
D8_C28_GPIO244
D9_C29_GPIO245
E0_A24_DACB_OUT
E10
E11
E12
E13
E16
E17
E1_A25
E2_A26
E3_A27
E4_A28_GPIO246
E5_A29_GPIO247
E6_A30_GPIO248
E7_A31_GPIO249
E8_C30
E9_C31
EPWM10_A
EPWM10_B
EPWM11_A
EPWM11_B
EPWM12_A
EPWM12_B
EPWM13_A
EPWM13_B
EPWM14_A
EPWM14_B
EPWM15_A
EPWM15_B
EPWM16_A
EPWM16_B
EPWM17_A
EPWM17_B
EPWM18_A
EPWM18_B
EPWM1_A
EPWM1_B
EPWM2_A
EPWM2_B
EPWM3_A
EPWM3_B
EPWM4_A
EPWM4_B
EPWM5_A
EPWM5_B
EPWM6_A
EPWM6_B
EPWM7_A
EPWM7_B
EPWM8_A
EPWM8_B
EPWM9_A
EPWM9_B
ERRORSTS
FSIRXA_CLK
FSIRXA_D0
FSIRXA_D1
FSIRXB_CLK
FSIRXB_D0
FSIRXB_D1
FSIRXC_CLK
FSIRXC_D0
FSIRXC_D1
FSIRXD_CLK
FSIRXD_D0
FSIRXD_D1
FSITXA_CLK
FSITXA_D0
FSITXA_D1
FSITXB_CLK
FSITXB_D0
FSITXB_D1
FSITXC_CLK
FSITXC_D0
FSITXC_D1
FSITXD_CLK
FSITXD_D0
FSITXD_D1
GPIO0
GPIO1
GPIO10
GPIO100
GPIO101
GPIO103
GPIO105
GPIO11
GPIO12
GPIO127
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO2
GPIO20
GPIO21
GPIO219
GPIO22
GPIO220
GPIO221
GPIO222
GPIO223
GPIO224
GPIO225
GPIO226
GPIO227
GPIO228
GPIO229
GPIO23
GPIO230
GPIO231
GPIO232
GPIO233
GPIO234
GPIO235
GPIO236
GPIO237
GPIO238
GPIO239
GPIO24
GPIO240
GPIO241
GPIO242
GPIO243
GPIO244
GPIO245
GPIO246
GPIO247
GPIO248
GPIO249
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO3
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO39
GPIO4
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO48
GPIO49
GPIO5
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55
GPIO56
GPIO57
GPIO58
GPIO59
GPIO6
GPIO60
GPIO61
GPIO62
GPIO63
GPIO64
GPIO65
GPIO66
GPIO67
GPIO68
GPIO69
GPIO7
GPIO70
GPIO71
GPIO72
GPIO73
GPIO74
GPIO75
GPIO76
GPIO77
GPIO78
GPIO79
GPIO8
GPIO80
GPIO81
GPIO82
GPIO83
GPIO84
GPIO85
GPIO86
GPIO87
GPIO88
GPIO89
GPIO9
GPIO90
GPIO91
GPIO92
GPIO93
GPIO94
GPIO95
GPIO96
GPIO97
GPIO98
GPIO99
I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
INPUTXBAR1
INPUTXBAR10
INPUTXBAR11
INPUTXBAR12
INPUTXBAR13
INPUTXBAR14
INPUTXBAR15
INPUTXBAR16
INPUTXBAR17
INPUTXBAR18
INPUTXBAR19
INPUTXBAR2
INPUTXBAR20
INPUTXBAR21
INPUTXBAR22
INPUTXBAR23
INPUTXBAR24
INPUTXBAR25
INPUTXBAR26
INPUTXBAR27
INPUTXBAR28
INPUTXBAR29
INPUTXBAR3
INPUTXBAR30
INPUTXBAR31
INPUTXBAR32
INPUTXBAR33
INPUTXBAR34
INPUTXBAR35
INPUTXBAR36
INPUTXBAR37
INPUTXBAR38
INPUTXBAR39
INPUTXBAR4
INPUTXBAR40
INPUTXBAR41
INPUTXBAR42
INPUTXBAR43
INPUTXBAR44
INPUTXBAR45
INPUTXBAR46
INPUTXBAR47
INPUTXBAR48
INPUTXBAR49
INPUTXBAR5
INPUTXBAR50
INPUTXBAR51
INPUTXBAR52
INPUTXBAR53
INPUTXBAR54
INPUTXBAR55
INPUTXBAR56
INPUTXBAR57
INPUTXBAR58
INPUTXBAR59
INPUTXBAR6
INPUTXBAR60
INPUTXBAR61
INPUTXBAR62
INPUTXBAR63
INPUTXBAR64
INPUTXBAR7
INPUTXBAR8
INPUTXBAR9
LINA_RX
LINA_TX
LINB_RX
LINB_TX
MCANA_RX
MCANA_TX
MCANB_RX
MCANB_TX
MCANC_RX
MCANC_TX
MCAND_RX
MCAND_TX
MCANE_RX
MCANE_TX
MCANF_RX
MCANF_TX
OUTPUTXBAR1
OUTPUTXBAR10
OUTPUTXBAR11
OUTPUTXBAR12
OUTPUTXBAR13
OUTPUTXBAR14
OUTPUTXBAR15
OUTPUTXBAR16
OUTPUTXBAR2
OUTPUTXBAR3
OUTPUTXBAR4
OUTPUTXBAR5
OUTPUTXBAR6
OUTPUTXBAR7
OUTPUTXBAR8
OUTPUTXBAR9
PMBUSA_ALERT
PMBUSA_CTL
PMBUSA_SCL
PMBUSA_SDA
SD1_C1
SD1_C2
SD1_C3
SD1_C4
SD1_D1
SD1_D2
SD1_D3
SD1_D4
SD2_C1
SD2_C2
SD2_C3
SD2_C4
SD2_D1
SD2_D2
SD2_D3
SD2_D4
SD3_C1
SD3_C2
SD3_C3
SD3_C4
SD3_D1
SD3_D2
SD3_D3
SD3_D4
SD4_C1
SD4_C2
SD4_C3
SD4_C4
SD4_D1
SD4_D2
SD4_D3
SD4_D4
SENT1
SENT2
SENT3
SENT4
SENT5
SENT6
SPIA_CLK
SPIA_PICO
SPIA_POCI
SPIA_PTE
SPIB_CLK
SPIB_PICO
SPIB_POCI
SPIB_PTE
SPIC_CLK
SPIC_PICO
SPIC_POCI
SPIC_PTE
SPID_CLK
SPID_PICO
SPID_POCI
SPID_PTE
SPIE_CLK
SPIE_PICO
SPIE_POCI
SPIE_PTE
SYNCOUT
TDI
TDO
UARTA_RX
UARTA_TX
UARTB_RX
UARTB_TX
UARTC_RX
UARTC_TX
UARTD_RX
UARTD_TX
UARTE_RX
UARTE_TX
UARTF_RX
UARTF_TX
X1
X2
XCLKOUT

5.8.10.1.1.7. PortPhysicalPinId

Item

Name

PortPhysicalPinId

Description

Identifying The physical Pin Number on the selected Pin Package.

Origin

Texas Instruments

Post-Build-Variant-Value

false

Value-Configuration-Class

Post-Build-Time

VARIANT-POST-BUILD

Pre-Compile-Time

VARIANT-PRE-COMPILE

Default-value

PORT_PIN_1

Range

PORT_PIN_1
PORT_PIN_10
PORT_PIN_100
PORT_PIN_102
PORT_PIN_103
PORT_PIN_104
PORT_PIN_105
PORT_PIN_106
PORT_PIN_107
PORT_PIN_108
PORT_PIN_109
PORT_PIN_11
PORT_PIN_110
PORT_PIN_111
PORT_PIN_112
PORT_PIN_113
PORT_PIN_114
PORT_PIN_115
PORT_PIN_116
PORT_PIN_117
PORT_PIN_118
PORT_PIN_119
PORT_PIN_12
PORT_PIN_120
PORT_PIN_121
PORT_PIN_123
PORT_PIN_124
PORT_PIN_125
PORT_PIN_126
PORT_PIN_127
PORT_PIN_128
PORT_PIN_129
PORT_PIN_13
PORT_PIN_130
PORT_PIN_131
PORT_PIN_132
PORT_PIN_133
PORT_PIN_134
PORT_PIN_135
PORT_PIN_136
PORT_PIN_138
PORT_PIN_139
PORT_PIN_14
PORT_PIN_140
PORT_PIN_141
PORT_PIN_142
PORT_PIN_143
PORT_PIN_144
PORT_PIN_145
PORT_PIN_146
PORT_PIN_148
PORT_PIN_149
PORT_PIN_15
PORT_PIN_150
PORT_PIN_151
PORT_PIN_154
PORT_PIN_155
PORT_PIN_156
PORT_PIN_157
PORT_PIN_158
PORT_PIN_159
PORT_PIN_16
PORT_PIN_160
PORT_PIN_161
PORT_PIN_162
PORT_PIN_163
PORT_PIN_164
PORT_PIN_165
PORT_PIN_166
PORT_PIN_167
PORT_PIN_17
PORT_PIN_170
PORT_PIN_171
PORT_PIN_172
PORT_PIN_173
PORT_PIN_174
PORT_PIN_175
PORT_PIN_176
PORT_PIN_18
PORT_PIN_19
PORT_PIN_2
PORT_PIN_20
PORT_PIN_21
PORT_PIN_22
PORT_PIN_23
PORT_PIN_24
PORT_PIN_25
PORT_PIN_26
PORT_PIN_27
PORT_PIN_28
PORT_PIN_29
PORT_PIN_30
PORT_PIN_31
PORT_PIN_32
PORT_PIN_33
PORT_PIN_34
PORT_PIN_35
PORT_PIN_36
PORT_PIN_37
PORT_PIN_38
PORT_PIN_39
PORT_PIN_4
PORT_PIN_40
PORT_PIN_41
PORT_PIN_42
PORT_PIN_43
PORT_PIN_44
PORT_PIN_45
PORT_PIN_46
PORT_PIN_47
PORT_PIN_48
PORT_PIN_49
PORT_PIN_5
PORT_PIN_50
PORT_PIN_51
PORT_PIN_52
PORT_PIN_53
PORT_PIN_54
PORT_PIN_55
PORT_PIN_56
PORT_PIN_57
PORT_PIN_58
PORT_PIN_59
PORT_PIN_6
PORT_PIN_60
PORT_PIN_61
PORT_PIN_62
PORT_PIN_63
PORT_PIN_64
PORT_PIN_65
PORT_PIN_66
PORT_PIN_67
PORT_PIN_68
PORT_PIN_69
PORT_PIN_7
PORT_PIN_70
PORT_PIN_71
PORT_PIN_72
PORT_PIN_73
PORT_PIN_74
PORT_PIN_75
PORT_PIN_76
PORT_PIN_77
PORT_PIN_78
PORT_PIN_79
PORT_PIN_8
PORT_PIN_80
PORT_PIN_81
PORT_PIN_82
PORT_PIN_83
PORT_PIN_84
PORT_PIN_85
PORT_PIN_86
PORT_PIN_87
PORT_PIN_88
PORT_PIN_89
PORT_PIN_9
PORT_PIN_90
PORT_PIN_91
PORT_PIN_92
PORT_PIN_93
PORT_PIN_94
PORT_PIN_95
PORT_PIN_96
PORT_PIN_97
PORT_PIN_98
PORT_PIN_99
PORT_PIN_A10
PORT_PIN_A11
PORT_PIN_A12
PORT_PIN_A13
PORT_PIN_A14
PORT_PIN_A15
PORT_PIN_A2
PORT_PIN_A3
PORT_PIN_A4
PORT_PIN_A5
PORT_PIN_A6
PORT_PIN_A7
PORT_PIN_A8
PORT_PIN_A9
PORT_PIN_B1
PORT_PIN_B10
PORT_PIN_B11
PORT_PIN_B12
PORT_PIN_B13
PORT_PIN_B14
PORT_PIN_B15
PORT_PIN_B16
PORT_PIN_B2
PORT_PIN_B3
PORT_PIN_B4
PORT_PIN_B5
PORT_PIN_B6
PORT_PIN_B7
PORT_PIN_B8
PORT_PIN_B9
PORT_PIN_C1
PORT_PIN_C10
PORT_PIN_C11
PORT_PIN_C12
PORT_PIN_C13
PORT_PIN_C14
PORT_PIN_C15
PORT_PIN_C16
PORT_PIN_C2
PORT_PIN_C3
PORT_PIN_C4
PORT_PIN_C5
PORT_PIN_C6
PORT_PIN_C7
PORT_PIN_C8
PORT_PIN_C9
PORT_PIN_D1
PORT_PIN_D10
PORT_PIN_D11
PORT_PIN_D12
PORT_PIN_D13
PORT_PIN_D14
PORT_PIN_D15
PORT_PIN_D16
PORT_PIN_D2
PORT_PIN_D3
PORT_PIN_D4
PORT_PIN_D5
PORT_PIN_D6
PORT_PIN_D7
PORT_PIN_D8
PORT_PIN_D9
PORT_PIN_E1
PORT_PIN_E13
PORT_PIN_E14
PORT_PIN_E16
PORT_PIN_E2
PORT_PIN_E3
PORT_PIN_E4
PORT_PIN_E5
PORT_PIN_F1
PORT_PIN_F13
PORT_PIN_F16
PORT_PIN_F2
PORT_PIN_F3
PORT_PIN_F4
PORT_PIN_F5
PORT_PIN_G1
PORT_PIN_G13
PORT_PIN_G14
PORT_PIN_G15
PORT_PIN_G16
PORT_PIN_G2
PORT_PIN_G3
PORT_PIN_G4
PORT_PIN_G5
PORT_PIN_H1
PORT_PIN_H13
PORT_PIN_H14
PORT_PIN_H15
PORT_PIN_H16
PORT_PIN_H2
PORT_PIN_H3
PORT_PIN_H4
PORT_PIN_H5
PORT_PIN_J1
PORT_PIN_J13
PORT_PIN_J14
PORT_PIN_J15
PORT_PIN_J16
PORT_PIN_J2
PORT_PIN_J3
PORT_PIN_J4
PORT_PIN_J5
PORT_PIN_K1
PORT_PIN_K13
PORT_PIN_K14
PORT_PIN_K15
PORT_PIN_K16
PORT_PIN_K2
PORT_PIN_K3
PORT_PIN_K4
PORT_PIN_K5
PORT_PIN_L1
PORT_PIN_L14
PORT_PIN_L15
PORT_PIN_L16
PORT_PIN_L2
PORT_PIN_L3
PORT_PIN_L4
PORT_PIN_L5
PORT_PIN_M1
PORT_PIN_M13
PORT_PIN_M14
PORT_PIN_M15
PORT_PIN_M16
PORT_PIN_M2
PORT_PIN_M3
PORT_PIN_M4
PORT_PIN_M5
PORT_PIN_M6
PORT_PIN_M7
PORT_PIN_M8
PORT_PIN_M9
PORT_PIN_N10
PORT_PIN_N11
PORT_PIN_N12
PORT_PIN_N13
PORT_PIN_N14
PORT_PIN_N15
PORT_PIN_N16
PORT_PIN_N3
PORT_PIN_N4
PORT_PIN_N5
PORT_PIN_N6
PORT_PIN_N7
PORT_PIN_N8
PORT_PIN_N9
PORT_PIN_P1
PORT_PIN_P10
PORT_PIN_P11
PORT_PIN_P12
PORT_PIN_P13
PORT_PIN_P14
PORT_PIN_P15
PORT_PIN_P16
PORT_PIN_P2
PORT_PIN_P3
PORT_PIN_P4
PORT_PIN_P5
PORT_PIN_P6
PORT_PIN_P7
PORT_PIN_P8
PORT_PIN_P9
PORT_PIN_R1
PORT_PIN_R10
PORT_PIN_R11
PORT_PIN_R12
PORT_PIN_R13
PORT_PIN_R14
PORT_PIN_R16
PORT_PIN_R2
PORT_PIN_R3
PORT_PIN_R5
PORT_PIN_R6
PORT_PIN_R7
PORT_PIN_R8
PORT_PIN_R9
PORT_PIN_T10
PORT_PIN_T11
PORT_PIN_T12
PORT_PIN_T13
PORT_PIN_T14
PORT_PIN_T2
PORT_PIN_T3
PORT_PIN_T5
PORT_PIN_T6
PORT_PIN_T7
PORT_PIN_T8
PORT_PIN_T9

5.8.10.1.1.8. PortPinName

Item

Name

PortPinName

Description

Device Pin Name for reference.

Origin

Texas Instruments

Post-Build-Variant-Value

true

Value-Configuration-Class

Post-Build-Time

VARIANT-POST-BUILD

Pre-Compile-Time

VARIANT-PRE-COMPILE

Default-value

A0_C24_DACA_OUT

Range

A0_C24_DACA_OUT
A10_GPIO228
A11_GPIO229
A12
A13
A14_B14_C14_D14_E14
A15_B15_C15_D15_E15
A1_C25
A2_D24
A3_D25
A4_D28
A5_D29
A6_E24_GPIO224
A7_E25_GPIO225
A8_GPIO226
A9_GPIO227
B0_C26_VDAC
B10_GPIO234
B11_GPIO235
B12
B13
B16
B17
B1_C27
B2_D26
B3_D27
B4_D30
B5_D31
B6_E26_GPIO230
B7_E27_GPIO231
B8_GPIO232
B9_GPIO233
C0_E28
C10
C11
C12
C13
C16
C17
C1_E29
C2_E30
C3_E31
C4
C5
C6_GPIO236
C7_GPIO237
C8_GPIO238
C9_GPIO239
D0_B24
D10
D11
D12
D13
D16
D17
D1_B25
D2_B26
D3_B27
D4_B28_GPIO240
D5_B29_GPIO241
D6_B30_GPIO242
D7_B31_GPIO243
D8_C28_GPIO244
D9_C29_GPIO245
E0_A24_DACB_OUT
E10
E11
E12
E13
E16
E17
E1_A25
E2_A26
E3_A27
E4_A28_GPIO246
E5_A29_GPIO247
E6_A30_GPIO248
E7_A31_GPIO249
E8_C30
E9_C31
FLT3
GPIO0
GPIO1
GPIO10
GPIO100
GPIO101
GPIO103
GPIO105
GPIO11
GPIO12
GPIO127
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO2
GPIO20
GPIO21
GPIO219_ERRORSTS
GPIO22
GPIO220_X1
GPIO221_X2
GPIO222_TDI
GPIO223_TDO
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO3
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO39
GPIO4
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO48
GPIO49
GPIO5
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55
GPIO56
GPIO57
GPIO58
GPIO59
GPIO6
GPIO60
GPIO61
GPIO62
GPIO63
GPIO64
GPIO65
GPIO66
GPIO67
GPIO68
GPIO69
GPIO7
GPIO70
GPIO71
GPIO72
GPIO73
GPIO74
GPIO75
GPIO76
GPIO77
GPIO78
GPIO79
GPIO8
GPIO80
GPIO81
GPIO82
GPIO83
GPIO84
GPIO85
GPIO86
GPIO87
GPIO88
GPIO89
GPIO9
GPIO90
GPIO91
GPIO92
GPIO93
GPIO94
GPIO95
GPIO96
GPIO97
GPIO98
GPIO99
TCK
TMS
VDD
VDDA
VDDIO
VREFHIAB
VREFHICDE
VREFLOAB
VREFLOCDE
VREGENZ
VSS
VSSA
VSSOSC
XRSn

5.8.10.1.1.9. PortPinId

Item

Name

PortPinId

Description

Pin Id of the port pin. This value will be assigned to the symbolic name derived from the port pin container short name.

Origin

AUTOSAR_ECUC

Post-Build-Variant-Value

false

Value-Configuration-Class

Post-Build-Time

VARIANT-POST-BUILD

Pre-Compile-Time

VARIANT-PRE-COMPILE

Default-value

0

Max-value

256

Min-value

0

5.8.10.1.1.10. PortAnalogMode

Item

Name

PortAnalogMode

Description

Select whether the pin operates in Analog Mode.

Origin

Texas Instruments

Post-Build-Variant-Value

true

Value-Configuration-Class

Post-Build-Time

VARIANT-POST-BUILD

Pre-Compile-Time

VARIANT-PRE-COMPILE

Default-value

PORT_ANALOG_ENABLED

Range

PORT_ANALOG_DISABLED
PORT_ANALOG_ENABLED

5.8.10.1.1.11. PortPinInitialMode

Item

Name

PortPinInitialMode

Description

Port pin mode from mode list for use with Port_Init() function.

Origin

AUTOSAR_ECUC

Post-Build-Variant-Value

true

Value-Configuration-Class

Post-Build-Time

VARIANT-POST-BUILD

Pre-Compile-Time

VARIANT-PRE-COMPILE

Default-value

ADCA_EXTMUXSEL0

Range

ADCA_EXTMUXSEL0
ADCA_EXTMUXSEL1
ADCA_EXTMUXSEL2
ADCA_EXTMUXSEL3
ADCB_EXTMUXSEL0
ADCB_EXTMUXSEL1
ADCB_EXTMUXSEL2
ADCB_EXTMUXSEL3
ADCC_EXTMUXSEL0
ADCC_EXTMUXSEL1
ADCC_EXTMUXSEL2
ADCC_EXTMUXSEL3
ADCD_EXTMUXSEL0
ADCD_EXTMUXSEL1
ADCD_EXTMUXSEL2
ADCD_EXTMUXSEL3
ADCE_EXTMUXSEL0
ADCE_EXTMUXSEL1
ADCE_EXTMUXSEL2
ADCE_EXTMUXSEL3
ADCSOCAO
ADCSOCBO
AIO160
AIO161
AIO162
AIO163
AIO164
AIO165
AIO166
AIO167
AIO168
AIO169
AIO170
AIO171
AIO172
AIO173
AIO174
AIO175
AIO176
AIO177
AIO178
AIO179
AIO180
AIO181
AIO182
AIO183
AIO184
AIO185
AIO186
AIO187
AIO188
AIO189
AIO190
AIO191
AIO192
AIO193
AIO194
AIO195
AIO196
AIO197
AIO198
AIO199
AIO200
AIO201
AIO202
AIO203
AIO204
AIO205
AIO206
AIO207
AIO208
AIO209
AIO210
AIO211
AIO212
AIO213
EMIF1_A0
EMIF1_A1
EMIF1_A10
EMIF1_A11
EMIF1_A12
EMIF1_A13
EMIF1_A14
EMIF1_A15
EMIF1_A16
EMIF1_A17
EMIF1_A18
EMIF1_A19
EMIF1_A2
EMIF1_A3
EMIF1_A4
EMIF1_A5
EMIF1_A6
EMIF1_A7
EMIF1_A8
EMIF1_A9
EMIF1_BA0
EMIF1_BA1
EMIF1_CAS
EMIF1_CLK
EMIF1_CS0n
EMIF1_CS2n
EMIF1_CS3n
EMIF1_CS4n
EMIF1_D0
EMIF1_D1
EMIF1_D10
EMIF1_D11
EMIF1_D12
EMIF1_D13
EMIF1_D14
EMIF1_D15
EMIF1_D16
EMIF1_D17
EMIF1_D18
EMIF1_D19
EMIF1_D2
EMIF1_D20
EMIF1_D21
EMIF1_D22
EMIF1_D23
EMIF1_D24
EMIF1_D25
EMIF1_D26
EMIF1_D27
EMIF1_D28
EMIF1_D29
EMIF1_D3
EMIF1_D30
EMIF1_D31
EMIF1_D4
EMIF1_D5
EMIF1_D6
EMIF1_D7
EMIF1_D8
EMIF1_D9
EMIF1_DQM0
EMIF1_DQM1
EMIF1_DQM2
EMIF1_DQM3
EMIF1_OEn
EMIF1_RAS
EMIF1_RNW
EMIF1_SDCKE
EMIF1_WAIT
EMIF1_WEn
EPWM10_A
EPWM10_B
EPWM11_A
EPWM11_B
EPWM12_A
EPWM12_B
EPWM13_A
EPWM13_B
EPWM14_A
EPWM14_B
EPWM15_A
EPWM15_B
EPWM16_A
EPWM16_B
EPWM17_A
EPWM17_B
EPWM18_A
EPWM18_B
EPWM1_A
EPWM1_B
EPWM2_A
EPWM2_B
EPWM3_A
EPWM3_B
EPWM4_A
EPWM4_B
EPWM5_A
EPWM5_B
EPWM6_A
EPWM6_B
EPWM7_A
EPWM7_B
EPWM8_A
EPWM8_B
EPWM9_A
EPWM9_B
ERRORSTS
ESC_GPI0
ESC_GPI1
ESC_GPI10
ESC_GPI11
ESC_GPI12
ESC_GPI13
ESC_GPI14
ESC_GPI15
ESC_GPI16
ESC_GPI17
ESC_GPI18
ESC_GPI19
ESC_GPI2
ESC_GPI20
ESC_GPI21
ESC_GPI22
ESC_GPI23
ESC_GPI24
ESC_GPI25
ESC_GPI26
ESC_GPI27
ESC_GPI28
ESC_GPI29
ESC_GPI3
ESC_GPI30
ESC_GPI31
ESC_GPI4
ESC_GPI5
ESC_GPI6
ESC_GPI7
ESC_GPI8
ESC_GPI9
ESC_GPO0
ESC_GPO1
ESC_GPO10
ESC_GPO11
ESC_GPO12
ESC_GPO13
ESC_GPO14
ESC_GPO15
ESC_GPO16
ESC_GPO17
ESC_GPO18
ESC_GPO19
ESC_GPO2
ESC_GPO20
ESC_GPO21
ESC_GPO22
ESC_GPO23
ESC_GPO24
ESC_GPO25
ESC_GPO26
ESC_GPO27
ESC_GPO28
ESC_GPO29
ESC_GPO3
ESC_GPO30
ESC_GPO31
ESC_GPO4
ESC_GPO5
ESC_GPO6
ESC_GPO7
ESC_GPO8
ESC_GPO9
ESC_I2C_SCL
ESC_I2C_SDA
ESC_LATCH0
ESC_LATCH1
ESC_LED_ERR
ESC_LED_LINK0_ACTIVE
ESC_LED_LINK1_ACTIVE
ESC_LED_RUN
ESC_LED_STATE_RUN
ESC_MDIO_CLK
ESC_MDIO_DATA
ESC_PDI_UC_IRQ
ESC_PHY0_LINKSTATUS
ESC_PHY1_LINKSTATUS
ESC_PHY_CLK
ESC_PHY_RESETn
ESC_RX0_CLK
ESC_RX0_DATA0
ESC_RX0_DATA1
ESC_RX0_DATA2
ESC_RX0_DATA3
ESC_RX0_DV
ESC_RX0_ERR
ESC_RX1_CLK
ESC_RX1_DATA0
ESC_RX1_DATA1
ESC_RX1_DATA2
ESC_RX1_DATA3
ESC_RX1_DV
ESC_RX1_ERR
ESC_SYNC0
ESC_SYNC1
ESC_TX0_CLK
ESC_TX0_DATA0
ESC_TX0_DATA1
ESC_TX0_DATA2
ESC_TX0_DATA3
ESC_TX0_ENA
ESC_TX1_CLK
ESC_TX1_DATA0
ESC_TX1_DATA1
ESC_TX1_DATA2
ESC_TX1_DATA3
ESC_TX1_ENA
FSIRXA_CLK
FSIRXA_D0
FSIRXA_D1
FSIRXB_CLK
FSIRXB_D0
FSIRXB_D1
FSIRXC_CLK
FSIRXC_D0
FSIRXC_D1
FSIRXD_CLK
FSIRXD_D0
FSIRXD_D1
FSITXA_CLK
FSITXA_D0
FSITXA_D1
FSITXB_CLK
FSITXB_D0
FSITXB_D1
FSITXC_CLK
FSITXC_D0
FSITXC_D1
FSITXD_CLK
FSITXD_D0
FSITXD_D1
GPIO0
GPIO1
GPIO10
GPIO100
GPIO101
GPIO103
GPIO105
GPIO11
GPIO12
GPIO127
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO2
GPIO20
GPIO21
GPIO219
GPIO22
GPIO220
GPIO221
GPIO222
GPIO223
GPIO224
GPIO225
GPIO226
GPIO227
GPIO228
GPIO229
GPIO23
GPIO230
GPIO231
GPIO232
GPIO233
GPIO234
GPIO235
GPIO236
GPIO237
GPIO238
GPIO239
GPIO24
GPIO240
GPIO241
GPIO242
GPIO243
GPIO244
GPIO245
GPIO246
GPIO247
GPIO248
GPIO249
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO3
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO39
GPIO4
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO48
GPIO49
GPIO5
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55
GPIO56
GPIO57
GPIO58
GPIO59
GPIO6
GPIO60
GPIO61
GPIO62
GPIO63
GPIO64
GPIO65
GPIO66
GPIO67
GPIO68
GPIO69
GPIO7
GPIO70
GPIO71
GPIO72
GPIO73
GPIO74
GPIO75
GPIO76
GPIO77
GPIO78
GPIO79
GPIO8
GPIO80
GPIO81
GPIO82
GPIO83
GPIO84
GPIO85
GPIO86
GPIO87
GPIO88
GPIO89
GPIO9
GPIO90
GPIO91
GPIO92
GPIO93
GPIO94
GPIO95
GPIO96
GPIO97
GPIO98
GPIO99
I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
LINA_RX
LINA_TX
LINB_RX
LINB_TX
MCANA_RX
MCANA_TX
MCANB_RX
MCANB_TX
MCANC_RX
MCANC_TX
MCAND_RX
MCAND_TX
MCANE_RX
MCANE_TX
MCANF_RX
MCANF_TX
OUTPUTXBAR1
OUTPUTXBAR10
OUTPUTXBAR11
OUTPUTXBAR12
OUTPUTXBAR13
OUTPUTXBAR14
OUTPUTXBAR15
OUTPUTXBAR16
OUTPUTXBAR2
OUTPUTXBAR3
OUTPUTXBAR4
OUTPUTXBAR5
OUTPUTXBAR6
OUTPUTXBAR7
OUTPUTXBAR8
OUTPUTXBAR9
PMBUSA_ALERT
PMBUSA_CTL
PMBUSA_SCL
PMBUSA_SDA
PORT_MUXMODE_NA
SD1_C1
SD1_C2
SD1_C3
SD1_C4
SD1_D1
SD1_D2
SD1_D3
SD1_D4
SD2_C1
SD2_C2
SD2_C3
SD2_C4
SD2_D1
SD2_D2
SD2_D3
SD2_D4
SD3_C1
SD3_C2
SD3_C3
SD3_C4
SD3_D1
SD3_D2
SD3_D3
SD3_D4
SD4_C1
SD4_C2
SD4_C3
SD4_C4
SD4_D1
SD4_D2
SD4_D3
SD4_D4
SENT1
SENT2
SENT3
SENT4
SENT5
SENT6
SPIA_CLK
SPIA_PICO
SPIA_POCI
SPIA_PTE
SPIB_CLK
SPIB_PICO
SPIB_POCI
SPIB_PTE
SPIC_CLK
SPIC_PICO
SPIC_POCI
SPIC_PTE
SPID_CLK
SPID_PICO
SPID_POCI
SPID_PTE
SPIE_CLK
SPIE_PICO
SPIE_POCI
SPIE_PTE
SYNCOUT
TDI
TDO
UARTA_RX
UARTA_TX
UARTB_RX
UARTB_TX
UARTC_RX
UARTC_TX
UARTD_RX
UARTD_TX
UARTE_RX
UARTE_TX
UARTF_RX
UARTF_TX
XCLKOUT

5.8.10.1.1.12. PortPinDirection

Item

Name

PortPinDirection

Description

The initial direction of the pin (IN or OUT). If the direction is not changeable, the value configured here is fixed.

Origin

AUTOSAR_ECUC

Post-Build-Variant-Value

true

Value-Configuration-Class

Post-Build-Time

VARIANT-POST-BUILD

Pre-Compile-Time

VARIANT-PRE-COMPILE

Default-value

PORT_PIN_IN

Range

PORT_PIN_IN
PORT_PIN_NA
PORT_PIN_OUT

5.8.10.1.1.13. PortPinDirectionChangeable

Item

Name

PortPinDirectionChangeable

Description

Parameter to indicate if the direction is changeable on a port pin during runtime.

Origin

AUTOSAR_ECUC

Post-Build-Variant-Value

true

Value-Configuration-Class

Post-Build-Time

VARIANT-POST-BUILD

Pre-Compile-Time

VARIANT-PRE-COMPILE

Default-value

False

5.8.10.1.1.14. PortPinPadConfig

Item

Name

PortPinPadConfig

Description

Enable Push-Pull or Open Drain functionality.

Origin

Texas Instruments

Post-Build-Variant-Value

true

Value-Configuration-Class

Post-Build-Time

VARIANT-POST-BUILD

Pre-Compile-Time

VARIANT-PRE-COMPILE

Default-value

PORT_PIN_TYPE_STD

Range

PORT_PIN_TYPE_STD
PORT_PIN_TYPE_OPEN_DRAIN
PORT_PIN_TYPE_NA

5.8.10.1.1.15. PortPinPullUpConfig

Item

Name

PortPinPullUpConfig

Description

Enable Pull Up.

Origin

Texas Instruments

Post-Build-Variant-Value

true

Value-Configuration-Class

Post-Build-Time

VARIANT-POST-BUILD

Pre-Compile-Time

VARIANT-PRE-COMPILE

Default-value

false

5.8.10.1.1.16. PortPinQualificationMode

Item

Name

PortPinQualificationMode

Description

Synchronization mode of the peripheral signals.

Origin

Texas Instruments

Post-Build-Variant-Value

true

Value-Configuration-Class

Post-Build-Time

VARIANT-POST-BUILD

Pre-Compile-Time

VARIANT-PRE-COMPILE

Default-value

PORT_QUAL_SYNC

Range

PORT_QUAL_SYNC
PORT_QUAL_3SAMPLE
PORT_QUAL_6SAMPLE
PORT_QUAL_ASYNC
PORT_QUAL_NA

5.8.10.1.1.17. PortPinQualificationPeriod

Item

Name

PortPinQualificationPeriod

Description

Qualification period of the peripheral signals. NOTE: The PortPinQualificationPeriod should be set to the same value for each pair of 8 consecutive GPIOs. For Instance: Qualification sampling period for GPIO0 to GPIO7: 0x00,QUALPRDx = PLLSYSCLK 0x01,QUALPRDx = PLLSYSCLK/2 0x02,QUALPRDx = PLLSYSCLK/4 …. 0xFF,QUALPRDx = PLLSYSCLK/510 Reset type: SYSRSn

Origin

Texas Instruments

Post-Build-Variant-Value

true

Value-Configuration-Class

Post-Build-Time

VARIANT-POST-BUILD

Pre-Compile-Time

VARIANT-PRE-COMPILE

Default-value

1

Max-value

510

Min-value

0

5.8.10.1.1.18. PortPinLevelValue

Item

Name

PortPinLevelValue

Description

Port Pin Level value from Port pin list.

Origin

AUTOSAR_ECUC

Post-Build-Variant-Value

true

Value-Configuration-Class

Post-Build-Time

VARIANT-POST-BUILD

Pre-Compile-Time

VARIANT-PRE-COMPILE

Default-value

PORT_PIN_LEVEL_LOW

Range

PORT_PIN_LEVEL_HIGH
PORT_PIN_LEVEL_LOW
PORT_PIN_LEVEL_NA

5.8.10.1.1.19. PortPinCoreSelect

Item

Name

PortPinCoreSelect

Description

Selection of core to which pin is to be mapped.

Origin

Texas Instruments

Post-Build-Variant-Value

true

Value-Configuration-Class

Post-Build-Time

VARIANT-POST-BUILD

Pre-Compile-Time

VARIANT-PRE-COMPILE

Default-value

PORT_CORE_CPU1

Range

PORT_CORE_CPU1
PORT_CORE_CPU2
PORT_CORE_CPU3

5.8.10.1.1.20. PortEnableWakeUpPinLPM

Item

Name

PortEnableWakeUpPinLPM

Description

Use/Don’t use the GPIO Pin as a wakeup source for the low power modes - standby/halt.

Origin

Texas Instruments

Post-Build-Variant-Value

false

Value-Configuration-Class

Post-Build-Time

VARIANT-POST-BUILD

Pre-Compile-Time

VARIANT-PRE-COMPILE

Default-value

false

5.8.10.1.1.21. PortPinMode

Item

Name

PortPinMode

Description

Port pin mode from mode list. NOTE: While configuring the PortPinMode, ensure that the selected mux mode is available for the specific device variant by checking the datasheet as the pinmuxmode list contains a superset of values for all the variants.

Multiplicity-Configuration-Class

Post-Build Time

VARIANT-POST-BUILD

Pre-Compile Time

VARIANT-PRE-COMPILE

Origin

AUTOSAR_ECUC

Post-Build-Variant-Value

true

Value-Configuration-Class

Post-Build-Time

VARIANT-POST-BUILD

Pre-Compile-Time

VARIANT-PRE-COMPILE

Default-value

ADCA_EXTMUXSEL0

Range

ADCA_EXTMUXSEL0
ADCA_EXTMUXSEL1
ADCA_EXTMUXSEL2
ADCA_EXTMUXSEL3
ADCB_EXTMUXSEL0
ADCB_EXTMUXSEL1
ADCB_EXTMUXSEL2
ADCB_EXTMUXSEL3
ADCC_EXTMUXSEL0
ADCC_EXTMUXSEL1
ADCC_EXTMUXSEL2
ADCC_EXTMUXSEL3
ADCD_EXTMUXSEL0
ADCD_EXTMUXSEL1
ADCD_EXTMUXSEL2
ADCD_EXTMUXSEL3
ADCE_EXTMUXSEL0
ADCE_EXTMUXSEL1
ADCE_EXTMUXSEL2
ADCE_EXTMUXSEL3
ADCSOCAO
ADCSOCBO
AIO160
AIO161
AIO162
AIO163
AIO164
AIO165
AIO166
AIO167
AIO168
AIO169
AIO170
AIO171
AIO172
AIO173
AIO174
AIO175
AIO176
AIO177
AIO178
AIO179
AIO180
AIO181
AIO182
AIO183
AIO184
AIO185
AIO186
AIO187
AIO188
AIO189
AIO190
AIO191
AIO192
AIO193
AIO194
AIO195
AIO196
AIO197
AIO198
AIO199
AIO200
AIO201
AIO202
AIO203
AIO204
AIO205
AIO206
AIO207
AIO208
AIO209
AIO210
AIO211
AIO212
AIO213
EMIF1_A0
EMIF1_A1
EMIF1_A10
EMIF1_A11
EMIF1_A12
EMIF1_A13
EMIF1_A14
EMIF1_A15
EMIF1_A16
EMIF1_A17
EMIF1_A18
EMIF1_A19
EMIF1_A2
EMIF1_A3
EMIF1_A4
EMIF1_A5
EMIF1_A6
EMIF1_A7
EMIF1_A8
EMIF1_A9
EMIF1_BA0
EMIF1_BA1
EMIF1_CAS
EMIF1_CLK
EMIF1_CS0n
EMIF1_CS2n
EMIF1_CS3n
EMIF1_CS4n
EMIF1_D0
EMIF1_D1
EMIF1_D10
EMIF1_D11
EMIF1_D12
EMIF1_D13
EMIF1_D14
EMIF1_D15
EMIF1_D16
EMIF1_D17
EMIF1_D18
EMIF1_D19
EMIF1_D2
EMIF1_D20
EMIF1_D21
EMIF1_D22
EMIF1_D23
EMIF1_D24
EMIF1_D25
EMIF1_D26
EMIF1_D27
EMIF1_D28
EMIF1_D29
EMIF1_D3
EMIF1_D30
EMIF1_D31
EMIF1_D4
EMIF1_D5
EMIF1_D6
EMIF1_D7
EMIF1_D8
EMIF1_D9
EMIF1_DQM0
EMIF1_DQM1
EMIF1_DQM2
EMIF1_DQM3
EMIF1_OEn
EMIF1_RAS
EMIF1_RNW
EMIF1_SDCKE
EMIF1_WAIT
EMIF1_WEn
EPWM10_A
EPWM10_B
EPWM11_A
EPWM11_B
EPWM12_A
EPWM12_B
EPWM13_A
EPWM13_B
EPWM14_A
EPWM14_B
EPWM15_A
EPWM15_B
EPWM16_A
EPWM16_B
EPWM17_A
EPWM17_B
EPWM18_A
EPWM18_B
EPWM1_A
EPWM1_B
EPWM2_A
EPWM2_B
EPWM3_A
EPWM3_B
EPWM4_A
EPWM4_B
EPWM5_A
EPWM5_B
EPWM6_A
EPWM6_B
EPWM7_A
EPWM7_B
EPWM8_A
EPWM8_B
EPWM9_A
EPWM9_B
ERRORSTS
ESC_GPI0
ESC_GPI1
ESC_GPI10
ESC_GPI11
ESC_GPI12
ESC_GPI13
ESC_GPI14
ESC_GPI15
ESC_GPI16
ESC_GPI17
ESC_GPI18
ESC_GPI19
ESC_GPI2
ESC_GPI20
ESC_GPI21
ESC_GPI22
ESC_GPI23
ESC_GPI24
ESC_GPI25
ESC_GPI26
ESC_GPI27
ESC_GPI28
ESC_GPI29
ESC_GPI3
ESC_GPI30
ESC_GPI31
ESC_GPI4
ESC_GPI5
ESC_GPI6
ESC_GPI7
ESC_GPI8
ESC_GPI9
ESC_GPO0
ESC_GPO1
ESC_GPO10
ESC_GPO11
ESC_GPO12
ESC_GPO13
ESC_GPO14
ESC_GPO15
ESC_GPO16
ESC_GPO17
ESC_GPO18
ESC_GPO19
ESC_GPO2
ESC_GPO20
ESC_GPO21
ESC_GPO22
ESC_GPO23
ESC_GPO24
ESC_GPO25
ESC_GPO26
ESC_GPO27
ESC_GPO28
ESC_GPO29
ESC_GPO3
ESC_GPO30
ESC_GPO31
ESC_GPO4
ESC_GPO5
ESC_GPO6
ESC_GPO7
ESC_GPO8
ESC_GPO9
ESC_I2C_SCL
ESC_I2C_SDA
ESC_LATCH0
ESC_LATCH1
ESC_LED_ERR
ESC_LED_LINK0_ACTIVE
ESC_LED_LINK1_ACTIVE
ESC_LED_RUN
ESC_LED_STATE_RUN
ESC_MDIO_CLK
ESC_MDIO_DATA
ESC_PDI_UC_IRQ
ESC_PHY0_LINKSTATUS
ESC_PHY1_LINKSTATUS
ESC_PHY_CLK
ESC_PHY_RESETn
ESC_RX0_CLK
ESC_RX0_DATA0
ESC_RX0_DATA1
ESC_RX0_DATA2
ESC_RX0_DATA3
ESC_RX0_DV
ESC_RX0_ERR
ESC_RX1_CLK
ESC_RX1_DATA0
ESC_RX1_DATA1
ESC_RX1_DATA2
ESC_RX1_DATA3
ESC_RX1_DV
ESC_RX1_ERR
ESC_SYNC0
ESC_SYNC1
ESC_TX0_CLK
ESC_TX0_DATA0
ESC_TX0_DATA1
ESC_TX0_DATA2
ESC_TX0_DATA3
ESC_TX0_ENA
ESC_TX1_CLK
ESC_TX1_DATA0
ESC_TX1_DATA1
ESC_TX1_DATA2
ESC_TX1_DATA3
ESC_TX1_ENA
FSIRXA_CLK
FSIRXA_D0
FSIRXA_D1
FSIRXB_CLK
FSIRXB_D0
FSIRXB_D1
FSIRXC_CLK
FSIRXC_D0
FSIRXC_D1
FSIRXD_CLK
FSIRXD_D0
FSIRXD_D1
FSITXA_CLK
FSITXA_D0
FSITXA_D1
FSITXB_CLK
FSITXB_D0
FSITXB_D1
FSITXC_CLK
FSITXC_D0
FSITXC_D1
FSITXD_CLK
FSITXD_D0
FSITXD_D1
GPIO0
GPIO1
GPIO10
GPIO100
GPIO101
GPIO103
GPIO105
GPIO11
GPIO12
GPIO127
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO2
GPIO20
GPIO21
GPIO219
GPIO22
GPIO220
GPIO221
GPIO222
GPIO223
GPIO224
GPIO225
GPIO226
GPIO227
GPIO228
GPIO229
GPIO23
GPIO230
GPIO231
GPIO232
GPIO233
GPIO234
GPIO235
GPIO236
GPIO237
GPIO238
GPIO239
GPIO24
GPIO240
GPIO241
GPIO242
GPIO243
GPIO244
GPIO245
GPIO246
GPIO247
GPIO248
GPIO249
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO3
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO39
GPIO4
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47
GPIO48
GPIO49
GPIO5
GPIO50
GPIO51
GPIO52
GPIO53
GPIO54
GPIO55
GPIO56
GPIO57
GPIO58
GPIO59
GPIO6
GPIO60
GPIO61
GPIO62
GPIO63
GPIO64
GPIO65
GPIO66
GPIO67
GPIO68
GPIO69
GPIO7
GPIO70
GPIO71
GPIO72
GPIO73
GPIO74
GPIO75
GPIO76
GPIO77
GPIO78
GPIO79
GPIO8
GPIO80
GPIO81
GPIO82
GPIO83
GPIO84
GPIO85
GPIO86
GPIO87
GPIO88
GPIO89
GPIO9
GPIO90
GPIO91
GPIO92
GPIO93
GPIO94
GPIO95
GPIO96
GPIO97
GPIO98
GPIO99
I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
LINA_RX
LINA_TX
LINB_RX
LINB_TX
MCANA_RX
MCANA_TX
MCANB_RX
MCANB_TX
MCANC_RX
MCANC_TX
MCAND_RX
MCAND_TX
MCANE_RX
MCANE_TX
MCANF_RX
MCANF_TX
OUTPUTXBAR1
OUTPUTXBAR10
OUTPUTXBAR11
OUTPUTXBAR12
OUTPUTXBAR13
OUTPUTXBAR14
OUTPUTXBAR15
OUTPUTXBAR16
OUTPUTXBAR2
OUTPUTXBAR3
OUTPUTXBAR4
OUTPUTXBAR5
OUTPUTXBAR6
OUTPUTXBAR7
OUTPUTXBAR8
OUTPUTXBAR9
PMBUSA_ALERT
PMBUSA_CTL
PMBUSA_SCL
PMBUSA_SDA
PORT_MUXMODE_NA
SD1_C1
SD1_C2
SD1_C3
SD1_C4
SD1_D1
SD1_D2
SD1_D3
SD1_D4
SD2_C1
SD2_C2
SD2_C3
SD2_C4
SD2_D1
SD2_D2
SD2_D3
SD2_D4
SD3_C1
SD3_C2
SD3_C3
SD3_C4
SD3_D1
SD3_D2
SD3_D3
SD3_D4
SD4_C1
SD4_C2
SD4_C3
SD4_C4
SD4_D1
SD4_D2
SD4_D3
SD4_D4
SENT1
SENT2
SENT3
SENT4
SENT5
SENT6
SPIA_CLK
SPIA_PICO
SPIA_POCI
SPIA_PTE
SPIB_CLK
SPIB_PICO
SPIB_POCI
SPIB_PTE
SPIC_CLK
SPIC_PICO
SPIC_POCI
SPIC_PTE
SPID_CLK
SPID_PICO
SPID_POCI
SPID_PTE
SPIE_CLK
SPIE_PICO
SPIE_POCI
SPIE_PTE
SYNCOUT
TDI
TDO
UARTA_RX
UARTA_TX
UARTB_RX
UARTB_TX
UARTC_RX
UARTC_TX
UARTD_RX
UARTD_TX
UARTE_RX
UARTE_TX
UARTF_RX
UARTF_TX
XCLKOUT

5.8.10.1.1.22. PortPinModeChangeable

Item

Name

PortPinModeChangeable

Description

Parameter to indicate if the mode is changeable on a port pin during runtime. True: Port Pin mode changeable allowed. False: Port Pin mode changeable not permitted.

Origin

AUTOSAR_ECUC

Post-Build-Variant-Value

true

Value-Configuration-Class

Post-Build-Time

VARIANT-POST-BUILD

Pre-Compile-Time

VARIANT-PRE-COMPILE

Default-value

false

5.8.10.1.2. PortGeneral

Module wide configuration parameters of the PORT driver.

5.8.10.1.2.1. PortDevErrorDetect

Item

Name

PortDevErrorDetect

Description

Switches the development error detection and notification on or off.

Origin

AUTOSAR_ECUC

Post-Build-Variant-Value

false

Value-Configuration-Class

Post-Build-Time

VARIANT-POST-BUILD

Pre-Compile-Time

VARIANT-PRE-COMPILE

Default-value

false

5.8.10.1.2.2. PortSetPinDirectionApi

Item

Name

PortSetPinDirectionApi

Description

Pre-processor switch to enable / disable the use of the function Port_SetPinDirection().

Origin

AUTOSAR_ECUC

Post-Build-Variant-Value

false

Value-Configuration-Class

Post-Build-Time

VARIANT-POST-BUILD

Pre-Compile-Time

VARIANT-PRE-COMPILE

Default-value

true

5.8.10.1.2.3. PortSetPinModeApi

Item

Name

PortSetPinModeApi

Description

Pre-processor switch to enable / disable the use of the function Port_SetPinMode().

Origin

AUTOSAR_ECUC

Post-Build-Variant-Value

false

Value-Configuration-Class

Post-Build-Time

VARIANT-POST-BUILD

Pre-Compile-Time

VARIANT-PRE-COMPILE

Default-value

true

5.8.10.1.2.4. PortVersionInfoApi

Item

Name

PortVersionInfoApi

Description

Pre-processor switch to enable / disable the API to read out the modules version information.

Origin

AUTOSAR_ECUC

Post-Build-Variant-Value

false

Value-Configuration-Class

Post-Build-Time

VARIANT-POST-BUILD

Pre-Compile-Time

VARIANT-PRE-COMPILE

Default-value

false

5.8.10.1.2.5. PortLockConfiguration

Item

Name

PortLockConfiguration

Description

Lock All pins configuration.

Origin

Texas Instruments

Post-Build-Variant-Value

false

Value-Configuration-Class

Post-Build-Time

VARIANT-POST-BUILD

Pre-Compile-Time

VARIANT-PRE-COMPILE

Default-value

false

Refer AUTOSAR_SWS_PortDriver section: 10 Configuration specification for more configuration parameters details

Note

The analog signals on this device are multiplexed with digital inputs and outputs. Some of these analog IO (AIO) pins do not have digital output capability. Others of these pins are analog pins capable of full digital input and output capability (AGPIO). Analog pins with AIO (digital input only) capability contain “AIO” signals in the Pin Attributes table of the device data sheet. Analog pins with full input and output capability (AGPIO pins) contain “GPIO” signals in the Pin Attributes table of the device data sheet. AGPIO pins also have pin names with both analog signals and GPIO in the name.

5.8.10.2. Steps To Configure Port Module

  1. Open EB Tresos configurator tool and Select the Config Variant ( Precompile/Post-Build)

  2. Go to Port Container tab and create a new container

  3. Open the created container and go to PortPin container to create a portPin configuration. ( Multiple PortPin configurations can be created )

  4. Open the created Port pin, and configure the pin parameters

  5. Select the Port pin peripheral instance ( Mode ) which needs to be configured and accordingly select the Peripheral Signal. As per selected Signal, physical pin ID needs to be selected from the list

  6. Once the above options are configured, run the auto-calculate wizard before proceeding to the next step.

  7. Configure the other parameters as per pin usage.

  8. Open Port pin Mode tab and add the default port pin mode ( at least one mode is required for this field ). Other supported modes for that pin can also be configured if user needs to change the mode for the pin afterwards.

  9. Configure the number of port pins in port container general tab

  10. Save the configuration and generate the configuration.

5.8.11. Examples

The example application demonstrates use of Port module, the list below identifies key steps performed in the example.

5.8.11.1. Overview

  • Port_Example_Init

    • EcuM_Init()

      • Initializes clock to 200 MHz using Mcu_Init()

      • Initializes one pin from each port as GPIO Output using Port_Init()

    • Port_SetPinDirection Changes the direction of GPIO0 pin to Input ( LED can be connected to GPIO0 to observe the behavior )

    • Port_RefreshPinDirection will refresh the direction of the pins where direction changeable is FALSE

    • Port_SetPinMode will change the Mode from GPIO to CAND_TX of the GPIO0 pin

    • Port_GetVersionInfo will get the software version info details

5.8.11.2. Setup required to run example

5.8.11.3. How to run examples

  • Open CCS and import Port Example

  • Build project and start debug project

5.8.11.3.1. Sample Log of Port_Example_Init

PORT Driver Sample Application - Starts!!!
---------------------------------------------------------------

Test 1: Initialize Port Driver
Initializing Port Driver...
API Port_Init executed successfully

---------------------------------------------------------------

Test 2: Change direction for PortPin_0
Direction changed to INPUT for PortPin_0
API Port_SetPinDirection executed successfully

---------------------------------------------------------------

Test 3: Change Mode for PortPin_0
Mode changed to MCAND_TX for PortPin_0
API Port_SetPinMode executed successfully

---------------------------------------------------------------

Test 4: Refresh Pin direction for direction unchangeable pins
API Port_RefreshPortDirection executed successfully

---------------------------------------------------------------

Test 5: Get Version info for Port
 
API Port_GetVersionInfo executed successfully
 PORT MCAL Version Info
 ---------------------
 Vendor ID           : 44
 Module ID           : 124
 SW Major Version    : 4
 SW Minor Version    : 0
 SW Patch Version    : 0
 
---------------------------------------------------------------

Port Example App run is Completed
Result - PASS!!

5.8.11.4. File Structure

📦f29h85x_mcal
┣ 📂build
┣ 📂docs
┣ 📂drivers
┣ 📂examples
┃ ┣ 📂AppUtils
┃ ┣ 📂Can
┃ ┣ 📂DeviceSupport
┃ ┣ 📂Dio
┃ ┣ 📂Gpt
┃ ┣ 📂Mcu
┃ ┣ 📂Port
┃ ┃ ┗ 📂 Port_Example_Init
┃ ┃ ┃ ┣ 📂ccs
┃ ┃ ┃ ┃ ┗ 📜Port_Example_Init.projectspec
┃ ┃ ┃ ┣ 📂Port_Example_Init_Config
┃ ┃ ┃ ┃ ┣ 📂config
┃ ┃ ┃ ┃ ┃ ┣ 📜Dem.xdm
┃ ┃ ┃ ┃ ┃ ┣ 📜EcuM.xdm
┃ ┃ ┃ ┃ ┃ ┣ 📜Mcu.xdm
┃ ┃ ┃ ┃ ┃ ┣ 📜Os.xdm
┃ ┃ ┃ ┃ ┃ ┗ 📜Port.xdm : Generated EB Tresos config file in .xdm format
┃ ┃ ┃ ┃ ┣ 📂include
┃ ┃ ┃ ┃ ┃ ┣ 📜Dem_Cfg.h
┃ ┃ ┃ ┃ ┃ ┣ 📜EcuM_Cfg.h
┃ ┃ ┃ ┃ ┃ ┣ 📜Mcu_Cfg.h
┃ ┃ ┃ ┃ ┃ ┣ 📜Os_Cfg.h
┃ ┃ ┃ ┃ ┃ ┗ 📜Port_Cfg.h : Contains the generated pre-compiler configuration header.*
┃ ┃ ┃ ┃ ┣ 📂src
┃ ┃ ┃ ┃ ┃ ┣ 📜Dem_Cfg.c
┃ ┃ ┃ ┃ ┃ ┣ 📜EcuM_Cfg.c
┃ ┃ ┃ ┃ ┃ ┣ 📜Mcu_PBcfg.c
┃ ┃ ┃ ┃ ┃ ┣ 📜Os_Cfg.c
┃ ┃ ┃ ┃ ┃ ┗ 📜Port_PBcfg.c : Contains the Post build configuration parameters.
┃ ┃ ┃ ┃ ┗ 📜CMakeLists.txt
┃ ┃ ┃ ┣ 📜CMakeLists.txt
┃ ┃ ┗ ┗ 📜📂Port_Example_Init.c : Example application for Port
┃ ┗ 📜CMakeLists.txt
┣ 📂plugins
┣ 📜CMakeLists.txt
┗ 📜CMakePresets.json

Note

Either Port_PBcfg.c OR Port_Cfg.c will be present based on selected config variant by user