RF Core

Data Structures
struct	rfTrim_t

Functions
static void	RFCClockEnable (void)
	Enable the RF core clocks. More...
static void	RFCClockDisable (void)
	Disable the RF core clocks. More...
static void	RFCCpeIntClear (uint32_t ui32Mask)
	Clear HW interrupt flags. More...
static void	RFCHwIntClear (uint32_t ui32Mask)
	Clear CPE interrupt flags. More...
static void	RFCCpe0IntSelect (uint32_t ui32Mask)
	Select interrupt sources to CPE0 (assign to INT_RFC_CPE_0 interrupt vector). More...
static void	RFCCpe1IntSelect (uint32_t ui32Mask)
	Select interrupt sources to CPE1 (assign to INT_RFC_CPE_1 interrupt vector). More...
static void	RFCCpeIntEnable (uint32_t ui32Mask)
	Enable CPEx interrupt sources. More...
static void	RFCCpe0IntSelectClearEnable (uint32_t ui32Mask)
	Select, clear, and enable interrupt sources to CPE0. More...
static void	RFCCpe1IntSelectClearEnable (uint32_t ui32Mask)
	Select, clear, and enable interrupt sources to CPE1. More...
static void	RFCHwIntEnable (uint32_t ui32Mask)
	Enable HW interrupt sources. More...
static void	RFCCpeIntDisable (uint32_t ui32Mask)
	Disable CPE interrupt sources. More...
static void	RFCHwIntDisable (uint32_t ui32Mask)
	Disable HW interrupt sources. More...
uint32_t	RFCCpeIntGetAndClear (uint32_t ui32Mask)
	Get and clear CPE interrupt flags. More...
static void	RFCAckIntClear (void)
	Clear ACK interrupt flag. More...
uint32_t	RFCDoorbellSendTo (uint32_t pOp)
	Send a radio operation to the doorbell and wait for an acknowledgment. More...
void	RFCSynthPowerDown (void)
	This function implements a fast way to turn off the synthesizer. More...
void	RFCCpePatchReset (void)
	Reset previously patched CPE RAM to a state where it can be patched again. More...
uint8_t	RFCOverrideSearch (const uint32_t *pOverride, const uint32_t pattern, const uint32_t mask, const uint8_t searchDepth)
uint8_t	RFCOverrideUpdate (rfc_radioOp_t *pOpSetup, uint32_t *pParams)
	Function to update override list. More...
uint32_t	RFCHwIntGetAndClear (uint32_t ui32Mask)
	Get and clear HW interrupt flags. More...
void	RFCRfTrimRead (rfc_radioOp_t *pOpSetup, rfTrim_t *rfTrim)
	Get the type of currently selected PA. More...
void	RFCRfTrimSet (rfTrim_t *rfTrim)
	Write preloaded RF trim values directly into CPE. More...
uint8_t	RFCRTrim (rfc_radioOp_t *pOpSetup)
	Check Override RTrim vs FCFG RTrim. More...
void	RFCAdi3VcoLdoVoltageMode (bool bEnable)
	Function to set VCOLDO reference to voltage mode. More...

Detailed Description

Function Documentation

static void RFCAckIntClear ( void  )

inlinestatic

Clear ACK interrupt flag.

Referenced by RFCDoorbellSendTo().

{
    // Clear any pending interrupts.
    HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG) = 0x0;
}

void RFCAdi3VcoLdoVoltageMode

(

bool

bEnable

)

Function to set VCOLDO reference to voltage mode.

{
    if (bEnable)
    {
        // First make sure the REFSYSCTL0 mux output is not further muxed out
        HWREGB(0x40086200) = 0x0;

        // Set the REFSYSCTL0 mux as desired for VCOLDO voltage mode
        HWREGB(ADI3_BASE + ADI_O_DIR + ADI_3_REFSYS_O_REFSYSCTL0) = ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VREF0P8V;
    }
    else
    {
        // Revert the mux override
        HWREGB(ADI3_BASE + ADI_O_DIR + ADI_3_REFSYS_O_REFSYSCTL0) = ADI_3_REFSYS_REFSYSCTL0_TESTCTL_NC;
    }
}

static void RFCClockDisable ( void  )

inlinestatic

Disable the RF core clocks.

As soon as the RF core is started it will handle clock control autonomously. No check should be performed to check the clocks. Instead the radio can be ping'ed through the command interface.

When disabling clocks it is the programmers responsibility that the RF core clocks are safely gated. I.e. the RF core should be safely 'parked'.

Returns

None

{
    // Disable all clocks
    HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = 0x0;
}

static void RFCClockEnable ( void  )

inlinestatic

Enable the RF core clocks.

As soon as the RF core is started it will handle clock control autonomously. No check should be performed to check the clocks. Instead the radio can be ping'ed through the command interface.

Returns

None

{
    // Enable basic clocks to get the CPE run
    HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = RFC_PWR_PWMCLKEN_CPERAM
                                                    | RFC_PWR_PWMCLKEN_CPE
                                                    | RFC_PWR_PWMCLKEN_RFC;
}

static void RFCCpe0IntSelect ( uint32_t  ui32Mask )

inlinestatic

Select interrupt sources to CPE0 (assign to INT_RFC_CPE_0 interrupt vector).

Referenced by RFCCpe0IntSelectClearEnable().

{
    // Multiplex RF Core interrupts to CPE0 IRQ.
    HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEISL) &= ~ui32Mask;
}

static void RFCCpe0IntSelectClearEnable ( uint32_t  ui32Mask )

inlinestatic

Select, clear, and enable interrupt sources to CPE0.

{
    // Multiplex RF Core interrupts to CPE0 IRQ.
    RFCCpe0IntSelect(ui32Mask);

    // Clear the masked interrupts.
    RFCCpeIntClear(ui32Mask);

    // Enable the masked interrupts.
    RFCCpeIntEnable(ui32Mask);
}

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static void RFCCpe1IntSelect ( uint32_t  ui32Mask )

inlinestatic

Select interrupt sources to CPE1 (assign to INT_RFC_CPE_1 interrupt vector).

Referenced by RFCCpe1IntSelectClearEnable().

{
    // Multiplex RF Core interrupts to CPE1 IRQ.
    HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEISL) |= ui32Mask;
}

static void RFCCpe1IntSelectClearEnable ( uint32_t  ui32Mask )

inlinestatic

Select, clear, and enable interrupt sources to CPE1.

{
    // Multiplex RF Core interrupts to CPE1 IRQ.
    RFCCpe1IntSelect(ui32Mask);

    // Clear the masked interrupts.
    RFCCpeIntClear(ui32Mask);

    // Enable the masked interrupts.
    RFCCpeIntEnable(ui32Mask);
}

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static void RFCCpeIntClear ( uint32_t  ui32Mask )

inlinestatic

Clear HW interrupt flags.

Referenced by RFCCpe0IntSelectClearEnable(), RFCCpe1IntSelectClearEnable(), and RFCCpeIntGetAndClear().

{
    // Clear the masked pending interrupts.
    do
    {
        HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) = ~ui32Mask;
    }while(HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) & ui32Mask);
}

static void RFCCpeIntDisable ( uint32_t  ui32Mask )

inlinestatic

Disable CPE interrupt sources.

{
    // Disable the masked interrupts
    HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN) &= ~ui32Mask;
}

static void RFCCpeIntEnable ( uint32_t  ui32Mask )

inlinestatic

Enable CPEx interrupt sources.

Referenced by RFCCpe0IntSelectClearEnable(), and RFCCpe1IntSelectClearEnable().

{
    // Enable CPE interrupts from RF Core.
    HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN) |= ui32Mask;
}

uint32_t RFCCpeIntGetAndClear

(

uint32_t

ui32Mask

)

Get and clear CPE interrupt flags.

{
    // Read the CPE interrupt flags which match the provided bitmask
    uint32_t ui32Ifg = HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) & ui32Mask;

    // Clear the interrupt flags
    RFCCpeIntClear(ui32Ifg);

    // Return with the interrupt flags
    return (ui32Ifg);
}

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void RFCCpePatchReset

(

void

)

Reset previously patched CPE RAM to a state where it can be patched again.

{
    uint8_t *pPatchTab  = (uint8_t *) (_CPERAM_START + _PARSER_PATCH_TAB_OFFSET);
    uint32_t *pIrqPatch = (uint32_t *)(_CPERAM_START + _IRQPATCH_OFFSET);

    memset(pPatchTab, 0xFF, _IRQPATCH_OFFSET - _PARSER_PATCH_TAB_OFFSET);

    int i;
    for (i = 0; i < sizeof(rfc_defaultIrqAddr)/sizeof(rfc_defaultIrqAddr[0]); i++)
    {
        pIrqPatch[i * 2 + 1] = rfc_defaultIrqAddr[i];
    }
}

uint32_t RFCDoorbellSendTo

(

uint32_t

pOp

)

Send a radio operation to the doorbell and wait for an acknowledgment.

{
    // Wait until the doorbell becomes available
    while(HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDR) != 0);
    RFCAckIntClear();

    // Submit the command to the CM0 through the doorbell
    HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDR) = pOp;

    // Wait until the CM0 starts to parse the command
    while(!HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG));
    RFCAckIntClear();

    // Return with the content of status register
    return(HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDSTA));
}

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static void RFCHwIntClear ( uint32_t  ui32Mask )

inlinestatic

Clear CPE interrupt flags.

Referenced by RFCHwIntGetAndClear().

{
    // Clear the masked pending interrupts.
    HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIFG) = ~ui32Mask;
}

static void RFCHwIntDisable ( uint32_t  ui32Mask )

inlinestatic

Disable HW interrupt sources.

{
    // Disable the masked interrupts
    HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) &= ~ui32Mask;
}

static void RFCHwIntEnable ( uint32_t  ui32Mask )

inlinestatic

Enable HW interrupt sources.

{
    // Enable the masked interrupts
    HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) |= ui32Mask;
}

uint32_t RFCHwIntGetAndClear

(

uint32_t

ui32Mask

)

Get and clear HW interrupt flags.

{
    // Read the CPE interrupt flags which match the provided bitmask
    uint32_t ui32Ifg = HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIFG) & ui32Mask;

    // Clear the interupt flags
    RFCHwIntClear(ui32Ifg);

    // Return with the interrupt flags
    return (ui32Ifg);
}

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uint8_t RFCOverrideSearch	(	const uint32_t *	pOverride,
		const uint32_t	pattern,
		const uint32_t	mask,
		const uint8_t	searchDepth
	)

Referenced by RFCRTrim().

{
    // Search from start of the override list, to look for first override entry that matches search pattern
    uint8_t override_index;
    for(override_index = 0; (override_index < searchDepth) && (pOverride[override_index] != END_OVERRIDE); override_index++)
    {
        // Compare the value to the given pattern
        if((pOverride[override_index] & mask) == pattern)
        {
            // Return with the index of override in case of match
            return override_index;
        }
    }

    // Return with an invalid index
    return 0xFF;
}

uint8_t RFCOverrideUpdate	(	rfc_radioOp_t *	pOpSetup,
		uint32_t *	pParams
	)

Function to update override list.

{
    /* Handle RTrim values. */
    return RFCRTrim(pOpSetup);

}

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void RFCRfTrimRead	(	rfc_radioOp_t *	pOpSetup,
		rfTrim_t *	rfTrim
	)

Get the type of currently selected PA.

Read RF trim from flash using CM3.

{
    // Definition of position and bitmask of divider value
    const uint32_t CONFIG_MISC_ADC_DIVIDER    = 27;
    const uint32_t CONFIG_MISC_ADC_DIVIDER_BM = 0xF8000000U;

    // Local variable
    int32_t divider;

    // Based on the type of setup command, decode the divider value
    switch (pOpSetup->commandNo)
    {
      case CMD_RADIO_SETUP:           // Use the loDivider value
                                      divider = ((rfc_CMD_RADIO_SETUP_t *)pOpSetup)->loDivider;
                                      break;
      case CMD_PROP_RADIO_DIV_SETUP:  // Use the loDivider value
                                      divider = ((rfc_CMD_PROP_RADIO_DIV_SETUP_t *)pOpSetup)->loDivider;
                                      break;
      default:                        // Use 2.4 GHz by default
                                      divider = 0;
                                      break;
    }

    // Read trim values from FCFG1
    pRfTrim->configIfAdc = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_IF_ADC);
    switch (divider)
    {
      case 5:
              pRfTrim->configRfFrontend =  HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND_DIV5);
              pRfTrim->configSynth      =  HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH_DIV5);
              pRfTrim->configMiscAdc    = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV5)
                                        & ~CONFIG_MISC_ADC_DIVIDER_BM) | (5U << CONFIG_MISC_ADC_DIVIDER);
              break;

      case 6:
              pRfTrim->configRfFrontend =  HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND_DIV6);
              pRfTrim->configSynth      =  HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH_DIV6);
              pRfTrim->configMiscAdc    = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV6)
                                        & ~CONFIG_MISC_ADC_DIVIDER_BM) | (6U << CONFIG_MISC_ADC_DIVIDER);
              break;

      case 10:
              pRfTrim->configRfFrontend =  HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND_DIV10);
              pRfTrim->configSynth      =  HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH_DIV10);
              pRfTrim->configMiscAdc    = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV10)
                                        & ~CONFIG_MISC_ADC_DIVIDER_BM) | (10U << CONFIG_MISC_ADC_DIVIDER);
              break;

      case 12:
              pRfTrim->configRfFrontend =  HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND_DIV12);
              pRfTrim->configSynth      =  HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH_DIV12);
              pRfTrim->configMiscAdc    = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV12)
                                        & ~CONFIG_MISC_ADC_DIVIDER_BM) | (12U << CONFIG_MISC_ADC_DIVIDER);
              break;

      case 15:
              pRfTrim->configRfFrontend =  HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND_DIV15);
              pRfTrim->configSynth      =  HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH_DIV15);
              pRfTrim->configMiscAdc    = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV15)
                                        & ~CONFIG_MISC_ADC_DIVIDER_BM) | (15U << CONFIG_MISC_ADC_DIVIDER);
              break;

      case 30:
              pRfTrim->configRfFrontend =  HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND_DIV30);
              pRfTrim->configSynth      =  HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH_DIV30);
              pRfTrim->configMiscAdc    = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV30)
                                        & ~CONFIG_MISC_ADC_DIVIDER_BM) | (30U << CONFIG_MISC_ADC_DIVIDER);
              break;

      default:
              pRfTrim->configRfFrontend =  HWREG(FCFG1_BASE + FCFG1_O_CONFIG_RF_FRONTEND);
              pRfTrim->configSynth      =  HWREG(FCFG1_BASE + FCFG1_O_CONFIG_SYNTH);
              // Make sure configMiscAdc is not 0 by setting an unused bit to 1
              pRfTrim->configMiscAdc    = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC)
                                        & ~CONFIG_MISC_ADC_DIVIDER_BM) | (2U << CONFIG_MISC_ADC_DIVIDER);
              break;
    }
}

void RFCRfTrimSet

(

rfTrim_t *

rfTrim

)

Write preloaded RF trim values directly into CPE.

{
    memcpy((void*)&HWREG(0x21000018), (void*)pRfTrim, sizeof(rfTrim_t));
}

uint8_t RFCRTrim

(

rfc_radioOp_t *

pOpSetup

)

Check Override RTrim vs FCFG RTrim.

Referenced by RFCOverrideUpdate().

{
    int32_t   divider;
    uint32_t  fcfg1_rtrim;
    uint32_t *pOverride;
    int32_t   override_index;
    uint32_t  override_value;
    uint32_t  override_rtrim = 0;

    // Based on the type of setup command, decode the divider and overrides
    switch (pOpSetup->commandNo)
    {
      case CMD_RADIO_SETUP:
                                    divider   = ((rfc_CMD_RADIO_SETUP_t *)pOpSetup)->loDivider;
                                    pOverride = ((rfc_CMD_RADIO_SETUP_t *)pOpSetup)->pRegOverride;
                                    break;
      case CMD_PROP_RADIO_SETUP:
                                    divider   = 2;
                                    pOverride = ((rfc_CMD_PROP_RADIO_SETUP_t *)pOpSetup)->pRegOverride;
                                    break;
      case CMD_PROP_RADIO_DIV_SETUP:
                                    divider   = ((rfc_CMD_PROP_RADIO_DIV_SETUP_t *)pOpSetup)->loDivider;
                                    pOverride = ((rfc_CMD_PROP_RADIO_DIV_SETUP_t *)pOpSetup)->pRegOverride;
                                    break;
      default:
                                    return 1;
    }

    if (pOverride == 0)
    {
        // There is no override list provided
        return 1;
    }

    // Search for an RTRIM value within the override list.
    override_index = RFCOverrideSearch(pOverride, RFC_RTRIM_PATTERN, RFC_RTRIM_MASK, RFC_MAX_SEARCH_DEPTH);

    // If we found it, decode the value.
    if(override_index < RFC_MAX_SEARCH_DEPTH)
    {
        override_value = pOverride[override_index];
        override_rtrim = (override_value & 0xF0000) >> 16;
    }
    else
    {
        // There is no RTRIM value within the first items of the override list
        return 1;
    }

    // Read trim from FCFG1
    switch (divider)
    {
      case 2:
              fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC)
                          & FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_M) >> FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_S;
              break;
      case 5:
              // Legacy value
              fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_MISC_OTP_DATA)
                          & FCFG1_MISC_OTP_DATA_MIN_ALLOWED_RTRIM_DIV5_M) >> FCFG1_MISC_OTP_DATA_MIN_ALLOWED_RTRIM_DIV5_S;
              break;
      case 6:
              fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV6)
                          & FCFG1_CONFIG_MISC_ADC_DIV6_MIN_ALLOWED_RTRIM_M) >> FCFG1_CONFIG_MISC_ADC_DIV6_MIN_ALLOWED_RTRIM_S;
              break;
      case 10:
              fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV10)
                          & FCFG1_CONFIG_MISC_ADC_DIV10_MIN_ALLOWED_RTRIM_M) >> FCFG1_CONFIG_MISC_ADC_DIV10_MIN_ALLOWED_RTRIM_S;
              break;
      case 12:
              fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV12)
                          & FCFG1_CONFIG_MISC_ADC_DIV12_MIN_ALLOWED_RTRIM_M) >> FCFG1_CONFIG_MISC_ADC_DIV12_MIN_ALLOWED_RTRIM_S;
              break;
      case 15:
              fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV15)
                          & FCFG1_CONFIG_MISC_ADC_DIV15_MIN_ALLOWED_RTRIM_M) >> FCFG1_CONFIG_MISC_ADC_DIV15_MIN_ALLOWED_RTRIM_S;
              break;
      case 30:
              fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC_DIV30)
                          & FCFG1_CONFIG_MISC_ADC_DIV30_MIN_ALLOWED_RTRIM_M) >> FCFG1_CONFIG_MISC_ADC_DIV30_MIN_ALLOWED_RTRIM_S;
              break;
      default:
              fcfg1_rtrim = (HWREG(FCFG1_BASE + FCFG1_O_CONFIG_MISC_ADC)
                          & FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_M) >> FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_S;
              break;
    }

    // Check for value matching early device samples
    if(fcfg1_rtrim == 0xF)
    {
        // Set to default value
        switch (divider)
        {
          case 5:
          case 10:
          case 15:
          case 30:
                  pOverride[override_index] = (override_value & 0xFFF0FFFF) | (0x7 << 16);
                  break;
          case 2:
          case 6:
          case 12:
          default:
                  pOverride[override_index] = (override_value & 0xFFF0FFFF) | (0x4 << 16);
                  break;
        }
    }
    else
    {
        // Test Override vs FCFG1 limit.
        if(override_rtrim >= fcfg1_rtrim)
        {
            ; // Do nothing
        }
        else
        {
            // Set override to FCFG1 limit value
            pOverride[override_index] = (override_value & 0xFFF0FFFF) | (fcfg1_rtrim << 16);
        }
    }

    return 0;
}

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void RFCSynthPowerDown

(

void

)

This function implements a fast way to turn off the synthesizer.

{
    // Definition of reserved words
    const uint32_t RFC_RESERVED0 = 0x40044108;
    const uint32_t RFC_RESERVED1 = 0x40044114;
    const uint32_t RFC_RESERVED2 = 0x4004410C;
    const uint32_t RFC_RESERVED3 = 0x40044100;

    // Disable CPE clock, enable FSCA clock.
    HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = (HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN)
                                                    & ~RFC_PWR_PWMCLKEN_CPE_M) | RFC_PWR_PWMCLKEN_FSCA_M;

    HWREG(RFC_RESERVED0) = 3;
    HWREG(RFC_RESERVED1) = 0x1030;
    HWREG(RFC_RESERVED2) = 1;
    HWREG(RFC_RESERVED1) = 0x50;
    HWREG(RFC_RESERVED2) = 1;
    HWREG(RFC_RESERVED1) = 0x650;
    HWREG(RFC_RESERVED2) = 1;
    HWREG(RFC_RESERVED3) = 1;

}

Macro Definition Documentation

#define RFC_MAX_SEARCH_DEPTH   5

Referenced by RFCRTrim().