30 #define SYSCTL_SRAM_BANK7 SYSCTL_SRAM_BANKEN_BNK7_EN
31 #define SYSCTL_SRAM_BANK6 SYSCTL_SRAM_BANKEN_BNK6_EN
32 #define SYSCTL_SRAM_BANK5 SYSCTL_SRAM_BANKEN_BNK5_EN
33 #define SYSCTL_SRAM_BANK4 SYSCTL_SRAM_BANKEN_BNK4_EN
34 #define SYSCTL_SRAM_BANK3 SYSCTL_SRAM_BANKEN_BNK3_EN
35 #define SYSCTL_SRAM_BANK2 SYSCTL_SRAM_BANKEN_BNK2_EN
36 #define SYSCTL_SRAM_BANK1 SYSCTL_SRAM_BANKEN_BNK1_EN
38 #define SYSCTL_HARD_RESET 1
39 #define SYSCTL_SOFT_RESET 0
41 #define SYSCTL_PERIPH_DMA SYSCTL_PERIHALT_CTL_HALT_DMA
42 #define SYSCTL_PERIPH_WDT SYSCTL_PERIHALT_CTL_HALT_WDT
43 #define SYSCTL_PERIPH_ADC SYSCTL_PERIHALT_CTL_HALT_ADC
44 #define SYSCTL_PERIPH_EUSCIB3 SYSCTL_PERIHALT_CTL_HALT_EUB3
45 #define SYSCTL_PERIPH_EUSCIB2 SYSCTL_PERIHALT_CTL_HALT_EUB2
46 #define SYSCTL_PERIPH_EUSCIB1 SYSCTL_PERIHALT_CTL_HALT_EUB1
47 #define SYSCTL_PERIPH_EUSCIB0 SYSCTL_PERIHALT_CTL_HALT_EUB0
48 #define SYSCTL_PERIPH_EUSCIA3 SYSCTL_PERIHALT_CTL_HALT_EUA3
49 #define SYSCTL_PERIPH_EUSCIA2 SYSCTL_PERIHALT_CTL_HALT_EUA2
50 #define SYSCTL_PERIPH_EUSCIA1 SYSCTL_PERIHALT_CTL_HALT_EUA1
51 #define SYSCTL_PERIPH_EUSCIA0 SYSCTL_PERIHALT_CTL_HALT_EUA0
52 #define SYSCTL_PERIPH_TIMER32_0_MODULE SYSCTL_PERIHALT_CTL_HALT_T32_0
53 #define SYSCTL_PERIPH_TIMER16_3 SYSCTL_PERIHALT_CTL_HALT_T16_3
54 #define SYSCTL_PERIPH_TIMER16_2 SYSCTL_PERIHALT_CTL_HALT_T16_2
55 #define SYSCTL_PERIPH_TIMER16_1 SYSCTL_PERIHALT_CTL_HALT_T16_1
56 #define SYSCTL_PERIPH_TIMER16_0 SYSCTL_PERIHALT_CTL_HALT_T16_0
58 #define SYSCTL_NMIPIN_SRC SYSCTL_NMI_CTLSTAT_PIN_SRC
59 #define SYSCTL_PCM_SRC SYSCTL_NMI_CTLSTAT_PCM_SRC
60 #define SYSCTL_PSS_SRC SYSCTL_NMI_CTLSTAT_PSS_SRC
61 #define SYSCTL_CS_SRC SYSCTL_NMI_CTLSTAT_CS_SRC
63 #define SYSCTL_REBOOT_KEY 0x6900
65 #define SYSCTL_1_2V_REF (uint32_t)&TLV->ADC14_REF1P2V_TS30C - (uint32_t)TLV_BASE
66 #define SYSCTL_1_45V_REF (uint32_t)&TLV->ADC14_REF1P45V_TS30C - (uint32_t)TLV_BASE
67 #define SYSCTL_2_5V_REF (uint32_t)&TLV->ADC14_REF2P5V_TS30C - (uint32_t)TLV_BASE
69 #define SYSCTL_85_DEGREES_C 4
70 #define SYSCTL_30_DEGREES_C 0
73 #define TLV_START 0x00201004
74 #define TLV_TAG_RESERVED1 1
75 #define TLV_TAG_RESERVED2 2
77 #define TLV_TAG_FLASHCTL 4
78 #define TLV_TAG_ADC14 5
79 #define TLV_TAG_RESERVED6 6
80 #define TLV_TAG_RESERVED7 7
82 #define TLV_TAG_RESERVED9 9
83 #define TLV_TAG_RESERVED10 10
84 #define TLV_TAG_DEVINFO 11
85 #define TLV_TAG_DIEREC 12
86 #define TLV_TAG_RANDNUM 13
87 #define TLV_TAG_RESERVED14 14
88 #define TLV_TAG_BSL 15
89 #define TLV_TAGEND 0x0BD0E11D
199 uint_fast8_t *length, uint32_t **data_address);
490 uint32_t temperature);
508 #endif // __SYSCTL_H__
uint32_t rDCOIR_MAXNEGTUNE_RSEL5
Definition: sysctl.h:109
uint32_t maxErasePulses
Definition: sysctl.h:99
void SysCtl_enableSRAMBankRetention(uint_fast8_t sramBank)
Definition: sysctl.c:171
uint_fast16_t SysCtl_getTempCalibrationConstant(uint32_t refVoltage, uint32_t temperature)
Definition: sysctl.c:240
uint32_t rDCOIR_FCAL_RSEL5
Definition: sysctl.h:105
uint32_t rDCOIR_CONSTK_RSEL04
Definition: sysctl.h:110
uint_fast8_t SysCtl_getNMISourceStatus(void)
Definition: sysctl.c:111
void SysCtl_disableGlitchFilter(void)
Definition: sysctl.c:235
void SysCtl_getTLVInfo(uint_fast8_t tag, uint_fast8_t instance, uint_fast8_t *length, uint32_t **data_address)
Definition: sysctl.c:50
void SysCtl_enableGlitchFilter(void)
Definition: sysctl.c:230
uint32_t rDCOIR_FCAL_RSEL04
Definition: sysctl.h:104
uint_least32_t SysCtl_getFlashSize(void)
Definition: sysctl.c:96
void SysCtl_setWDTPasswordViolationResetType(uint_fast8_t resetType)
Definition: sysctl.c:219
uint32_t rDCOER_FCAL_RSEL04
Definition: sysctl.h:112
uint32_t rDCOER_MAXNEGTUNE_RSEL5
Definition: sysctl.h:117
uint_least32_t SysCtl_getSRAMSize(void)
Definition: sysctl.c:91
uint32_t rDCOIR_MAXNEGTUNE_RSEL04
Definition: sysctl.h:107
void SysCtl_disableSRAMBankRetention(uint_fast8_t sramBank)
Definition: sysctl.c:182
uint32_t rDCOER_FCAL_RSEL5
Definition: sysctl.h:113
void SysCtl_setWDTTimeoutResetType(uint_fast8_t resetType)
Definition: sysctl.c:210
uint32_t rDCOER_MAXPOSTUNE_RSEL5
Definition: sysctl.h:116
uint32_t rDCOIR_MAXPOSTUNE_RSEL04
Definition: sysctl.h:106
void SysCtl_disableSRAMBank(uint_fast8_t sramBank)
Definition: sysctl.c:127
void SysCtl_disableNMISource(uint_fast8_t flags)
Definition: sysctl.c:101
uint32_t rDCOER_MAXNEGTUNE_RSEL04
Definition: sysctl.h:115
uint32_t rDCOIR_CONSTK_RSEL5
Definition: sysctl.h:111
uint32_t rDCOER_CONSTK_RSEL04
Definition: sysctl.h:118
uint32_t rDCOIR_MAXPOSTUNE_RSEL5
Definition: sysctl.h:108
uint32_t maxProgramPulses
Definition: sysctl.h:98
uint32_t rDCOER_MAXPOSTUNE_RSEL04
Definition: sysctl.h:114
void SysCtl_enablePeripheralAtCPUHalt(uint_fast16_t devices)
Definition: sysctl.c:198
uint32_t rDCOER_CONSTK_RSEL5
Definition: sysctl.h:119
void SysCtl_disablePeripheralAtCPUHalt(uint_fast16_t devices)
Definition: sysctl.c:204
void SysCtl_rebootDevice(void)
Definition: sysctl.c:193
void SysCtl_enableNMISource(uint_fast8_t flags)
Definition: sysctl.c:106
void SysCtl_enableSRAMBank(uint_fast8_t sramBank)
Definition: sysctl.c:116