TI-RTOS Drivers  tidrivers_full_2_20_00_08
Data Structures | Typedefs | Variables
SPIMSP432DMA.h File Reference

Detailed Description

SPI driver implementation for a EUSCI peripheral on MSP432 using the micro DMA controller.

============================================================================

The SPI header file should be included in an application as follows:

Refer to SPI.h for a complete description of APIs & example of use.

This SPI driver implementation is designed to operate on a EUCSI controller in SPI mode.

SPI Chip Select

The SPIMSP432DMA operates the controller in 3-pin mode; therefore it is not safe to use in a multi-master SPI bus environment. It is the application's responsibility to assert and de-assert a GPIO pin for chip select purposes.

Chip select type SPI_MASTER mode SPI_SLAVE mode
Hardware chip select Not available on this peripheral.
Software chip select The application is responsible to ensure that correct SPI slave is selected before performing a SPI_transfer(). Up to the application's implementation.

DMA Interrupts

The MSP432 DMA controller has 4 interrupt vectors to handle all DMA related IRQ. Due to the "shared" nature of the DMA interrupts, this driver implementation requires each SPI instance to explicitly use a single DMA interrupt. It is up to the application to ensure no two peripherals are configured to respond to a given DMA interrupt at any moment.

Scratch Buffers

A uint32_t scratch buffer is used to allow SPI_transfers where txBuf or rxBuf are NULL. Rather than requiring txBuf or rxBuf to have a dummy buffer of size of the transfer count, a single DMA accessible uint32_t scratch buffer is used. When txBuf is NULL, an internal scratch buffer is initialized to the defaultTxBufValue so the DMA will send some known value. Each SPI driver instance should uses its own scratch buffer.

SPI data frames

The EUSCI controller only supports 8-bit data frames.

dataSize buffer element size
8 bits uint8_t

DMA transfer size limit

The DMA contoller only supports data transfers of upto 1024 data frames. Each SPI driver instance requires 2 DMA channels (Tx and Rx) to operate.

DMA accessible memory

Ensure that the txBuf and rxBuf (in SPI_Transaction) point to memory that is accessible by the DMA.


#include <stdint.h>
#include <ti/drivers/ports/HwiP.h>
#include <ti/drivers/ports/SemaphoreP.h>
#include <ti/drivers/Power.h>
#include <ti/drivers/SPI.h>
#include <ti/drivers/dma/UDMAMSP432.h>
Include dependency graph for SPIMSP432DMA.h:

Go to the source code of this file.

Data Structures

struct  SPIMSP432DMA_HWAttrs
 SPIMSP432DMA Hardware attributes These fields, with the exception of intPriority, are used by driverlib APIs and therefore must be populated by driverlib macro definitions. For MSP430Ware these definitions are found in: More...
 
struct  SPIMSP432DMA_Object
 SPIMSP432DMA Object. More...
 

Typedefs

typedef struct SPIMSP432DMA_HWAttrs SPIMSP432DMA_HWAttrs
 SPIMSP432DMA Hardware attributes These fields, with the exception of intPriority, are used by driverlib APIs and therefore must be populated by driverlib macro definitions. For MSP430Ware these definitions are found in: More...
 
typedef struct SPIMSP432DMA_Object SPIMSP432DMA_Object
 SPIMSP432DMA Object. More...
 
typedef struct SPIMSP432DMA_ObjectSPIMSP432DMA_Handle
 

Variables

const SPI_FxnTable SPIMSP432DMA_fxnTable
 

Typedef Documentation

SPIMSP432DMA Hardware attributes These fields, with the exception of intPriority, are used by driverlib APIs and therefore must be populated by driverlib macro definitions. For MSP430Ware these definitions are found in:

  • dma.h
  • spi.h

intPriority is the SPI peripheral's interrupt priority, as defined by the underlying OS. It is passed unmodified to the underlying OS's interrupt handler creation code, so you need to refer to the OS documentation for usage. For example, for SYS/BIOS applications, refer to the ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of interrupt priorities. If the driver uses the ti.drivers.ports interface instead of making OS calls directly, then the HwiP port handles the interrupt priority in an OS specific way. In the case of the SYS/BIOS port, intPriority is passed unmodified to Hwi_create().

A sample structure is shown below:

1 const SPIMSP432DMA_HWAttrs spiMSP432DMAHWAttrs[] = {
2  {
3  .baseAddr = EUSCI_B0_BASE,
4  .clockSource = EUSCI_B_SPI_CLOCKSOURCE_SMCLK,
5  .bitOrder = EUSCI_B_SPI_MSB_FIRST,
6 
7  .defaultTxBufValue = 0,
8 
9  .dmaIntNum = INT_DMA_INT1,
10  .intPriority = (~0),
11  .rxDMAChannelIndex = DMA_CH1_EUSCIB0RX0,
12  .txDMAChannelIndex = DMA_CH0_EUSCIB0TX0
13  },
14  {
15  .baseAddr = EUSCI_B2_BASE,
16  .clockSource = EUSCI_B_SPI_CLOCKSOURCE_SMCLK,
17  .bitOrder = EUSCI_B_SPI_MSB_FIRST,
18 
19  .defaultTxBufValue = 0,
20 
21  .dmaIntNum = INT_DMA_INT2,
22  .intPriority = (~0),
23  .rxDMAChannelIndex = DMA_CH5_EUSCIB2RX0,
24  .txDMAChannelIndex = DMA_CH4_EUSCIB2TX0
25  }
26 };

SPIMSP432DMA Object.

The application must not access any member variables of this structure!

Variable Documentation

const SPI_FxnTable SPIMSP432DMA_fxnTable
Copyright 2016, Texas Instruments Incorporated