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00053 #ifndef ti_sdo_fc_ires_edma3chan_IRES_EDMA3CHAN_
00054 #define ti_sdo_fc_ires_edma3chan_IRES_EDMA3CHAN_
00055
00058
00059 #ifdef __cplusplus
00060 extern "C" {
00061 #endif
00062
00063 #include <ti/xdais/xdas.h>
00064 #include <ti/xdais/ires_common.h>
00065
00069 #define IRES_EDMA3CHAN_PROTOCOLNAME "ti.sdo.fc.ires.edma3chan"
00070
00081 #define EDMA3CHAN_MODNAME "ti.sdo.fc.ires.edma3chan"
00082
00083
00084
00085
00086
00087
00088 #ifndef ti_sdo_fc_ires_NOPROTOCOLREV
00089
00094 static IRES_ProtocolRevision IRES_EDMA3CHAN_PROTOCOLREVISION = {1, 0, 0};
00095
00096 #endif
00097
00101 #define IRES_EDMA3CHAN_PROTOCOLREVISION_1_0_0 {1, 0, 0}
00102 #define IRES_EDMA3CHAN_SETPROTOCOLREVISION_1_0_0(rev) {(rev)->Major = 1; \
00103 (rev)->Source = 0; (rev)->Radius = 0;}
00104
00108 #define IRES_EDMA3CHAN_PROTOCOLREVISION_2_0_0 {2, 0, 0}
00109 #define IRES_EDMA3CHAN_SETPROTOCOLREVISION_2_0_0(rev) {(rev)->Major = 2; \
00110 (rev)->Source = 0; (rev)->Radius = 0;}
00111
00116 #define IRES_EDMA3CHAN_MAXPARAMS 512
00117 #define IRES_EDMA3CHAN_MAXTCCS 32
00118 #define IRES_EDMA3CHAN_NUMDESTTYPES 8
00119
00123 #define IRES_EDMA3CHAN_PARAM_ANY 512
00124 #define IRES_EDMA3CHAN_PARAM_NONE 513
00125 #define IRES_EDMA3CHAN_TCC_ANY 514
00126 #define IRES_EDMA3CHAN_TCC_NONE 515
00127 #define IRES_EDMA3CHAN_EDMACHAN_ANY 516
00128 #define IRES_EDMA3CHAN_QDMACHAN_ANY 516
00129 #define IRES_EDMA3CHAN_CHAN_NONE 518
00130
00134 typedef struct IRES_EDMA3CHAN_Obj *IRES_EDMA3CHAN_Handle;
00135
00139 typedef struct IRES_EDMA3CHAN2_Obj *IRES_EDMA3CHAN2_Handle;
00140
00146
00147 typedef struct IRES_EDMA3CHAN_PaRamStruct {
00148 unsigned int opt;
00153 unsigned int src;
00158 unsigned short acnt;
00169 unsigned short bcnt;
00179 unsigned int dst;
00184 unsigned short srcElementIndex;
00194 unsigned short dstElementIndex;
00205 unsigned short link;
00216 unsigned short bCntrld;
00227 unsigned short srcFrameIndex;
00253 unsigned short dstFrameIndex;
00281 unsigned short ccnt;
00292 unsigned short rsvd;
00293 } IRES_EDMA3CHAN_PaRamStruct;
00294
00295
00314 typedef struct IRES_EDMA3CHAN_ProtocolArgs {
00315 int size;
00316 IRES_RequestMode mode;
00320 short numPaRams;
00326 short paRamIndex;
00335 short numTccs;
00341 short tccIndex;
00350 short qdmaChan;
00356 short edmaChan;
00371 short contiguousAllocation;
00375 short shadowPaRamsAllocation;
00378 } IRES_EDMA3CHAN_ProtocolArgs;
00379
00390 typedef struct IRES_EDMA3CHAN_Obj {
00391
00392 IRES_Obj ires;
00393 IRES_EDMA3CHAN_PaRamStruct * shadowPaRams;
00396 unsigned int * assignedPaRamAddresses;
00399 short * assignedPaRamIndices;
00400 short * assignedTccIndices;
00401 short assignedNumPaRams;
00402 short assignedNumTccs;
00403 short assignedQdmaChannelIndex;
00411 short assignedEdmaChannelIndex;
00419 unsigned int esrBitMaskL;
00428 unsigned int esrBitMaskH;
00437 unsigned int iprBitMaskL;
00446 unsigned int iprBitMaskH;
00455 } IRES_EDMA3CHAN_Obj;
00456
00460 typedef struct IRES_EDMA3CHAN_EDMA3ShadowRegister {
00461 volatile unsigned int ER;
00462 volatile unsigned int ERH;
00463 volatile unsigned int ECR;
00464 volatile unsigned int ECRH;
00465 volatile unsigned int ESR;
00466 volatile unsigned int ESRH;
00467 volatile unsigned int CER;
00468 volatile unsigned int CERH;
00469 volatile unsigned int EER;
00470 volatile unsigned int EERH;
00471 volatile unsigned int EECR;
00472 volatile unsigned int EECRH;
00473 volatile unsigned int EESR;
00474 volatile unsigned int EESRH;
00475 volatile unsigned int SER;
00476 volatile unsigned int SERH;
00477 volatile unsigned int SECR;
00478 volatile unsigned int SECRH;
00479 volatile unsigned char RSVD0[8];
00480 volatile unsigned int IER;
00481 volatile unsigned int IERH;
00482 volatile unsigned int IECR;
00483 volatile unsigned int IECRH;
00484 volatile unsigned int IESR;
00485 volatile unsigned int IESRH;
00486 volatile unsigned int IPR;
00487 volatile unsigned int IPRH;
00488 volatile unsigned int ICR;
00489 volatile unsigned int ICRH;
00490 volatile unsigned int IEVAL;
00491 volatile unsigned char RSVD1[4];
00492 volatile unsigned int QER;
00493 volatile unsigned int QEER;
00494 volatile unsigned int QEECR;
00495 volatile unsigned int QEESR;
00496 volatile unsigned int QSER;
00497 volatile unsigned int QSECR;
00498 volatile unsigned char RSVD2[360];
00499
00500 } IRES_EDMA3CHAN_EDMA3ShadowRegister;
00501
00506 typedef struct IRES_EDMA3CHAN_EDMA3DraeRegister {
00507 volatile unsigned int DRAE;
00508 volatile unsigned int DRAEH;
00509 } IRES_EDMA3CHAN_EDMA3DraeRegister;
00510
00514 typedef struct IRES_EDMA3CHAN_EDMA3RegisterLayer {
00515 volatile unsigned int REV;
00516 volatile unsigned int CCCFG;
00517 volatile unsigned char RSVD0[248];
00518 volatile unsigned int DCHMAP[64];
00519 volatile unsigned int QCHMAP[8];
00520 volatile unsigned char RSVD1[32];
00521 volatile unsigned int DMAQNUM[8];
00522 volatile unsigned int QDMAQNUM;
00523 volatile unsigned char RSVD2[28];
00524 volatile unsigned int QUETCMAP;
00525 volatile unsigned int QUEPRI;
00526 volatile unsigned char RSVD3[120];
00527 volatile unsigned int EMR;
00528 volatile unsigned int EMRH;
00529 volatile unsigned int EMCR;
00530 volatile unsigned int EMCRH;
00531 volatile unsigned int QEMR;
00532 volatile unsigned int QEMCR;
00533 volatile unsigned int CCERR;
00534 volatile unsigned int CCERRCLR;
00535 volatile unsigned int EEVAL;
00536 volatile unsigned char RSVD4[28];
00537 IRES_EDMA3CHAN_EDMA3DraeRegister DRA[8];
00538 volatile unsigned int QRAE[8];
00539 volatile unsigned char RSVD5[96];
00540 volatile unsigned int QUEEVTENTRY[8][16];
00541 volatile unsigned int QSTAT[8];
00542 volatile unsigned int QWMTHRA;
00543 volatile unsigned int QWMTHRB;
00544 volatile unsigned char RSVD6[24];
00545 volatile unsigned int CCSTAT;
00546 volatile unsigned char RSVD7[188];
00547 volatile unsigned int AETCTL;
00548 volatile unsigned int AETSTAT;
00549 volatile unsigned int AETCMD;
00550 volatile unsigned char RSVD8[244];
00551 volatile unsigned int MPFAR;
00552 volatile unsigned int MPFSR;
00553 volatile unsigned int MPFCR;
00554 volatile unsigned int MPPAG;
00555 volatile unsigned int MPPA[8];
00556 volatile unsigned char RSVD9[2000];
00557 volatile unsigned int ER;
00558 volatile unsigned int ERH;
00559 volatile unsigned int ECR;
00560 volatile unsigned int ECRH;
00561 volatile unsigned int ESR;
00562 volatile unsigned int ESRH;
00563 volatile unsigned int CER;
00564 volatile unsigned int CERH;
00565 volatile unsigned int EER;
00566 volatile unsigned int EERH;
00567 volatile unsigned int EECR;
00568 volatile unsigned int EECRH;
00569 volatile unsigned int EESR;
00570 volatile unsigned int EESRH;
00571 volatile unsigned int SER;
00572 volatile unsigned int SERH;
00573 volatile unsigned int SECR;
00574 volatile unsigned int SECRH;
00575 volatile unsigned char RSVD10[8];
00576 volatile unsigned int IER;
00577 volatile unsigned int IERH;
00578 volatile unsigned int IECR;
00579 volatile unsigned int IECRH;
00580 volatile unsigned int IESR;
00581 volatile unsigned int IESRH;
00582 volatile unsigned int IPR;
00583 volatile unsigned int IPRH;
00584 volatile unsigned int ICR;
00585 volatile unsigned int ICRH;
00586 volatile unsigned int IEVAL;
00587 volatile unsigned char RSVD11[4];
00588 volatile unsigned int QER;
00589 volatile unsigned int QEER;
00590 volatile unsigned int QEECR;
00591 volatile unsigned int QEESR;
00592 volatile unsigned int QSER;
00593 volatile unsigned int QSECR;
00594 volatile unsigned char RSVD12[3944];
00595 IRES_EDMA3CHAN_EDMA3ShadowRegister SHADOW[8];
00596 volatile unsigned char RSVD13[4096];
00597 IRES_EDMA3CHAN_PaRamStruct PARAMENTRY[512];
00598 } IRES_EDMA3CHAN_EDMA3RegisterLayer;
00599
00603 typedef struct IRES_EDMA3CHAN_Properties {
00604
00605 unsigned int numDmaChannels;
00608 unsigned int numQdmaChannels;
00612 unsigned int numTccs;
00615 unsigned int numPaRAMSets;
00618 unsigned int numEvtQueue;
00621 unsigned int numTcs;
00625 unsigned int numRegions;
00636 unsigned short dmaChPaRAMMapExists;
00637
00638 unsigned short memProtectionExists;
00642 IRES_EDMA3CHAN_EDMA3RegisterLayer *globalRegs;
00646 } IRES_EDMA3CHAN_Properties;
00647
00655 typedef enum IRES_EDMA3CHAN_DmaDestType {
00656 INTMEMORY0 = 0,
00657 INTMEMORY1 = 1,
00658 INTMEMORY2 = 2,
00659 EXTMEMORY0 = 3,
00660 EXTMEMORY1 = 4,
00661 EXTMEMORY2 = 5,
00662 OTHER0 = 6,
00663 OTHER1 = 7
00664 } IRES_EDMA3CHAN_DmaDestType;
00665
00684 typedef struct IRES_EDMA3CHAN2_Obj {
00685
00686 IRES_Obj ires;
00687
00689 IRES_EDMA3CHAN_PaRamStruct * shadowPaRams;
00690
00692 unsigned int * assignedPaRamAddresses;
00693
00695 short * assignedPaRamIndices;
00696
00698 short * assignedTccIndices;
00699
00701 short assignedNumPaRams;
00702
00704 short assignedNumTccs;
00705
00707 short assignedQdmaChannelIndex;
00708
00710 short assignedEdmaChannelIndex;
00711
00713 unsigned int esrBitMaskL;
00714
00716 unsigned int esrBitMaskH;
00717
00719 unsigned int iprBitMaskL;
00720
00722 unsigned int iprBitMaskH;
00723
00724 XDAS_Int32 * queueMap;
00738 } IRES_EDMA3CHAN2_Obj;
00739
00740 #ifdef __cplusplus
00741 }
00742 #endif
00743
00746 #endif
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