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IRES EDMA3CHAN PROTOCOL Interface Definitions - Allows algorithms to request and receive handles representing EDMA3 resources associated with a single EDMA3 channel.
#include <ti/xdais/xdas.h>#include <ti/xdais/ires_common.h>
Go to the source code of this file.
Defines | |
| #define | IRES_EDMA3CHAN_PROTOCOLNAME "ti.sdo.fc.ires.edma3chan" |
| Name used to describe this protocol. | |
| #define | EDMA3CHAN_MODNAME "ti.sdo.fc.ires.edma3chan" |
| Name to pass to Diags_setMask() to enable logging for EDMA3CHAN functions. | |
| #define | IRES_EDMA3CHAN_PROTOCOLREVISION_1_0_0 {1, 0, 0} |
| Protocol Revision for the 1.0.0 version of resource. | |
| #define | IRES_EDMA3CHAN_SETPROTOCOLREVISION_1_0_0(rev) |
| #define | IRES_EDMA3CHAN_PROTOCOLREVISION_2_0_0 {2, 0, 0} |
| Protocol Revision for the 2.0.0 version of resource. | |
| #define | IRES_EDMA3CHAN_SETPROTOCOLREVISION_2_0_0(rev) |
| #define | IRES_EDMA3CHAN_MAXPARAMS 512 |
| Maximum number of params and tccs that can be requested in one handle. | |
| #define | IRES_EDMA3CHAN_MAXTCCS 32 |
| #define | IRES_EDMA3CHAN_NUMDESTTYPES 8 |
| #define | IRES_EDMA3CHAN_PARAM_ANY 512 |
| Macros to represent different PaRam, Channel and tcc types. | |
| #define | IRES_EDMA3CHAN_PARAM_NONE 513 |
| #define | IRES_EDMA3CHAN_TCC_ANY 514 |
| #define | IRES_EDMA3CHAN_TCC_NONE 515 |
| #define | IRES_EDMA3CHAN_EDMACHAN_ANY 516 |
| #define | IRES_EDMA3CHAN_QDMACHAN_ANY 516 |
| #define | IRES_EDMA3CHAN_CHAN_NONE 518 |
Data Structures | |
| struct | IRES_EDMA3CHAN_PaRamStruct |
| Representation of actual PaRam hardware registers. More... | |
| struct | IRES_EDMA3CHAN_ProtocolArgs |
| EDMA3 Linked Transfer Protocol Arguments definition. More... | |
| struct | IRES_EDMA3CHAN_Obj |
| Object returned to the algorithm requesting EDMA3 resources. More... | |
| struct | IRES_EDMA3CHAN_EDMA3ShadowRegister |
| Defines the shadow register part of the EDMA3 CC Register Layer. More... | |
| struct | IRES_EDMA3CHAN_EDMA3DraeRegister |
| Defines the Region Enable register part of the EDMA3 CC Register Layer. More... | |
| struct | IRES_EDMA3CHAN_EDMA3RegisterLayer |
| Defines the EDMA3 CC Register Layout. More... | |
| struct | IRES_EDMA3CHAN_Properties |
| Static Resource Properties. More... | |
| struct | IRES_EDMA3CHAN2_Obj |
| Object returned to the algorithm requesting EDMA3 resources. More... | |
Typedefs | |
| typedef struct IRES_EDMA3CHAN_Obj * | IRES_EDMA3CHAN_Handle |
| Handle to "logical" EDMA3CHAN resource, version {1,0,0}. | |
| typedef struct IRES_EDMA3CHAN2_Obj * | IRES_EDMA3CHAN2_Handle |
| Handle to "logical" EDMA3CHAN resource, version {2,0,0}. | |
| typedef struct IRES_EDMA3CHAN_PaRamStruct | IRES_EDMA3CHAN_PaRamStruct |
| Representation of actual PaRam hardware registers. | |
| typedef struct IRES_EDMA3CHAN_ProtocolArgs | IRES_EDMA3CHAN_ProtocolArgs |
| EDMA3 Linked Transfer Protocol Arguments definition. | |
| typedef struct IRES_EDMA3CHAN_Obj | IRES_EDMA3CHAN_Obj |
| Object returned to the algorithm requesting EDMA3 resources. | |
| typedef struct IRES_EDMA3CHAN_EDMA3ShadowRegister | IRES_EDMA3CHAN_EDMA3ShadowRegister |
| Defines the shadow register part of the EDMA3 CC Register Layer. | |
| typedef struct IRES_EDMA3CHAN_EDMA3DraeRegister | IRES_EDMA3CHAN_EDMA3DraeRegister |
| Defines the Region Enable register part of the EDMA3 CC Register Layer. | |
| typedef struct IRES_EDMA3CHAN_EDMA3RegisterLayer | IRES_EDMA3CHAN_EDMA3RegisterLayer |
| Defines the EDMA3 CC Register Layout. | |
| typedef struct IRES_EDMA3CHAN_Properties | IRES_EDMA3CHAN_Properties |
| Static Resource Properties. | |
| typedef enum IRES_EDMA3CHAN_DmaDestType | IRES_EDMA3CHAN_DmaDestType |
| Describes the Destination type of DMA writes This information is used to distribute different types of DMA writes to different EDMA3 Queues. | |
| typedef struct IRES_EDMA3CHAN2_Obj | IRES_EDMA3CHAN2_Obj |
| Object returned to the algorithm requesting EDMA3 resources. | |
Enumerations | |
| enum | IRES_EDMA3CHAN_DmaDestType { INTMEMORY0 = 0, INTMEMORY1 = 1, INTMEMORY2 = 2, EXTMEMORY0 = 3, EXTMEMORY1 = 4, EXTMEMORY2 = 5, OTHER0 = 6, OTHER1 = 7 } |
Describes the Destination type of DMA writes This information is used to distribute different types of DMA writes to different EDMA3 Queues. More... | |