metaonly module ti.sdo.fc.dskt2.DSKT2
index URL

XDAIS algorithm management library

XDCspec summary sourced in ti/sdo/fc/dskt2/DSKT2.xdc
metaonly module DSKT2 {  ...
XDCscript usage meta-domain
var DSKT2 = xdc.useModule('ti.sdo.fc.dskt2.DSKT2');
module-wide constants & types
    const DSKT2.DEFAULTSEG// Default segment to allocate memory from = "IRAM";
module-wide config parameters
    DSKT2.ALLOW_EXTERNAL_SCRATCH// Allow external memory to be used for algorithm scratch memory requests = Bool true;
    DSKT2.DARAM0// IALG memory space mapping of IALG_DARAM0. This must match a BIOS heap = String DSKT2.DEFAULTSEG;
    DSKT2.DARAM1// IALG memory space mapping of IALG_DARAM1. This must match a BIOS heap = String DSKT2.DEFAULTSEG;
    DSKT2.DARAM2// IALG memory space mapping of IALG_DARAM2. This must match a BIOS heap = String DSKT2.DEFAULTSEG;
    DSKT2.DARAM_SCRATCH_SIZES// Shared IALG_DARAM0 scratch group sizes = UInt[] [
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0
    ];
    DSKT2.DSKT2_HEAP// Memory segment for internal DSKT2 data structures = String DSKT2.DEFAULTSEG;
    DSKT2.EPROG// IALG memory space mapping of IALG_EPROG. This must match a BIOS heap = String DSKT2.DEFAULTSEG;
    DSKT2.ESDATA// IALG memory space mapping of IALG_ESDATA. This must match a BIOS heap = String DSKT2.DEFAULTSEG;
    DSKT2.IPROG// IALG memory space mapping of IALG_IPROG. This must match a BIOS heap = String DSKT2.DEFAULTSEG;
    DSKT2.SARAM0// IALG memory space mapping of IALG_SARAM0. This must match a BIOS heap = String DSKT2.DEFAULTSEG;
    DSKT2.SARAM1// IALG memory space mapping of IALG_SARAM1. This must match a BIOS heap = String DSKT2.DEFAULTSEG;
    DSKT2.SARAM2// IALG memory space mapping of IALG_SARAM2. This must match a BIOS heap = String DSKT2.DEFAULTSEG;
    DSKT2.SARAM_SCRATCH_SIZES// Shared IALG_SARAM0 scratch group sizes = UInt[] [
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0
    ];
    DSKT2.cacheWritebackInvalidateFxn// Name of function implementing cache writeback invalidate = String "BCACHE_wbInv";
 
XDCspec declarations sourced in ti/sdo/fc/dskt2/DSKT2.xdc
package ti.sdo.fc.dskt2;
 
metaonly module DSKT2 {
module-wide constants & types
    const String DEFAULTSEG// Default segment to allocate memory from = "IRAM";
module-wide config parameters
    config Bool ALLOW_EXTERNAL_SCRATCH// Allow external memory to be used for algorithm scratch memory requests = true;
    config String DARAM0// IALG memory space mapping of IALG_DARAM0. This must match a BIOS heap = DSKT2.DEFAULTSEG;
    config String DARAM1// IALG memory space mapping of IALG_DARAM1. This must match a BIOS heap = DSKT2.DEFAULTSEG;
    config String DARAM2// IALG memory space mapping of IALG_DARAM2. This must match a BIOS heap = DSKT2.DEFAULTSEG;
    config UInt DARAM_SCRATCH_SIZES// Shared IALG_DARAM0 scratch group sizes[] = [
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0
    ];
    config String DSKT2_HEAP// Memory segment for internal DSKT2 data structures = DSKT2.DEFAULTSEG;
    config String EPROG// IALG memory space mapping of IALG_EPROG. This must match a BIOS heap = DSKT2.DEFAULTSEG;
    config String ESDATA// IALG memory space mapping of IALG_ESDATA. This must match a BIOS heap = DSKT2.DEFAULTSEG;
    config String IPROG// IALG memory space mapping of IALG_IPROG. This must match a BIOS heap = DSKT2.DEFAULTSEG;
    config String SARAM0// IALG memory space mapping of IALG_SARAM0. This must match a BIOS heap = DSKT2.DEFAULTSEG;
    config String SARAM1// IALG memory space mapping of IALG_SARAM1. This must match a BIOS heap = DSKT2.DEFAULTSEG;
    config String SARAM2// IALG memory space mapping of IALG_SARAM2. This must match a BIOS heap = DSKT2.DEFAULTSEG;
    config UInt SARAM_SCRATCH_SIZES// Shared IALG_SARAM0 scratch group sizes[] = [
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0,
        0
    ];
    config String cacheWritebackInvalidateFxn// Name of function implementing cache writeback invalidate = "BCACHE_wbInv";
}
 
const DSKT2.DEFAULTSEG
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Default segment to allocate memory from

XDCscript usage meta-domain
const DSKT2.DEFAULTSEG = "IRAM";
 
 
config DSKT2.ALLOW_EXTERNAL_SCRATCH  // module-wide
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Allow external memory to be used for algorithm scratch memory requests

XDCscript usage meta-domain
DSKT2.ALLOW_EXTERNAL_SCRATCH = Bool true;
 
DETAILS
If an algorithm requests scratch memory, and insufficient scratch memory is available, scratch buffers will be allocated in external memory if property is 'true'.
 
config DSKT2.DARAM0  // module-wide
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IALG memory space mapping of IALG_DARAM0. This must match a BIOS heap

XDCscript usage meta-domain
DSKT2.DARAM0 = String DSKT2.DEFAULTSEG;
 
 
config DSKT2.DARAM1  // module-wide
index URL

IALG memory space mapping of IALG_DARAM1. This must match a BIOS heap

XDCscript usage meta-domain
DSKT2.DARAM1 = String DSKT2.DEFAULTSEG;
 
 
config DSKT2.DARAM2  // module-wide
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IALG memory space mapping of IALG_DARAM2. This must match a BIOS heap

XDCscript usage meta-domain
DSKT2.DARAM2 = String DSKT2.DEFAULTSEG;
 
 
config DSKT2.DARAM_SCRATCH_SIZES  // module-wide
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Shared IALG_DARAM0 scratch group sizes

XDCscript usage meta-domain
DSKT2.DARAM_SCRATCH_SIZES = UInt[] [
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0
];
 
 
config DSKT2.DSKT2_HEAP  // module-wide
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Memory segment for internal DSKT2 data structures

XDCscript usage meta-domain
DSKT2.DSKT2_HEAP = String DSKT2.DEFAULTSEG;
 
DETAILS
Objects internal to the DSKT2 module will be allocated from this heap.
 
config DSKT2.EPROG  // module-wide
index URL

IALG memory space mapping of IALG_EPROG. This must match a BIOS heap

XDCscript usage meta-domain
DSKT2.EPROG = String DSKT2.DEFAULTSEG;
 
 
config DSKT2.ESDATA  // module-wide
index URL

IALG memory space mapping of IALG_ESDATA. This must match a BIOS heap

XDCscript usage meta-domain
DSKT2.ESDATA = String DSKT2.DEFAULTSEG;
 
 
config DSKT2.IPROG  // module-wide
index URL

IALG memory space mapping of IALG_IPROG. This must match a BIOS heap

XDCscript usage meta-domain
DSKT2.IPROG = String DSKT2.DEFAULTSEG;
 
 
config DSKT2.SARAM0  // module-wide
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IALG memory space mapping of IALG_SARAM0. This must match a BIOS heap

XDCscript usage meta-domain
DSKT2.SARAM0 = String DSKT2.DEFAULTSEG;
 
 
config DSKT2.SARAM1  // module-wide
index URL

IALG memory space mapping of IALG_SARAM1. This must match a BIOS heap

XDCscript usage meta-domain
DSKT2.SARAM1 = String DSKT2.DEFAULTSEG;
 
 
config DSKT2.SARAM2  // module-wide
index URL

IALG memory space mapping of IALG_SARAM2. This must match a BIOS heap

XDCscript usage meta-domain
DSKT2.SARAM2 = String DSKT2.DEFAULTSEG;
 
 
config DSKT2.SARAM_SCRATCH_SIZES  // module-wide
index URL

Shared IALG_SARAM0 scratch group sizes

XDCscript usage meta-domain
DSKT2.SARAM_SCRATCH_SIZES = UInt[] [
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0
];
 
 
config DSKT2.cacheWritebackInvalidateFxn  // module-wide
index URL

Name of function implementing cache writeback invalidate

XDCscript usage meta-domain
DSKT2.cacheWritebackInvalidateFxn = String "BCACHE_wbInv";
 
DETAILS
This function must have the following signature:
  (*DSKT2_CacheWBInvFxn)(Ptr blockPtr, size_t byteCnt, bool wait)
For C6000 platforms DSKT2 calls this function to ensure that the algorithm instance memory is not resident in cache when it is instantiated. This is necessary for compliance with XDAIS C6000 DMA Rules and Guidelines.
generated on Thu, 02 Dec 2010 05:35:07 GMT