Detailed Description

Defines platform specific attributes for user applications.

============================================================================

Path:: /gpp/inc/usr/

Version:: 1.65.01.06 ============================================================================

Copyright:: Copyright (C) 2002-2009, Texas Instruments Incorporated - https://www.ti.com/

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

* Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.

* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

* Neither the name of Texas Instruments Incorporated nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ============================================================================

#include <gpptypes.h>

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Defines
#define	SHMEM_INTERFACE 0
	Interface number for shared memory interface. ============================================================================.
#define	PCI_INTERFACE 1
	Interface number for PCI interface. ============================================================================.
#define	VLYNQ_INTERFACE 2
	Interface number for VLYNQ interface. ============================================================================.
#define	DSP_MAUSIZE 1
	Size of the DSP MAU (in bytes). ============================================================================.
#define	DSPLINK_BUF_ALIGN 128
	Alignment of message buffers allocated for transfer. ============================================================================.
#define	ADD_PADDING(padVar, count) Uint16 padVar [count] ;
	Macro to add padding to a structure. ============================================================================.
#define	DSPLINK_ALIGN(x, y) (Uint32)((Uint32)((x + y - 1) / y) * y)
	Macro to align a number. x: The number to be aligned y: The value that the number should be aligned to. ============================================================================.
#define	REG(x) ((volatile Uint32 ) (x))
	Gives the value of a 32-bit register. ============================================================================.
#define	RTC_REG_VALUE(x) ((volatile Uint32 ) (x))
	Gives the value of a 32-bit register. ============================================================================.
#define	CACHE_L2_LINESIZE 128
	Line size of DSP L2 cache (in bytes). ============================================================================.
#define	DSPLINK_16BIT_PADDING ((CACHE_L2_LINESIZE - sizeof (Uint16)) / 2)
	Padding required for alignment of a 16-bit value (for L2 cache) in 16-bit words. ============================================================================.
#define	DSPLINK_32BIT_PADDING ((CACHE_L2_LINESIZE - sizeof (Uint32)) / 2)
	Padding required for alignment of a 32-bit value (for L2 cache) in 16-bit words. ============================================================================.
#define	DSPLINK_BOOL_PADDING ((CACHE_L2_LINESIZE - sizeof (Bool)) / 2)
	Padding required for alignment of a Boolean value (for L2 cache) in 16-bit words. ============================================================================.
#define	DSPLINK_PTR_PADDING ((CACHE_L2_LINESIZE - sizeof (Void *)) / 2)
	Padding required for alignment of a pointer value (for L2 cache) in 16-bit words. ============================================================================.
#define	LDRV_DRV_CTRL_SIZE
	Padding required for DSP L2 cache line alignment within LDRV_DRV control structure. ============================================================================.
#define	LDRV_DRV_PADDING
#define	LDRV_IPS_CTRL_PADDING
	Padding length for the IPS shared configuration structure. ============================================================================.
#define	IPS_EVENT_ENTRY_PADDING
#define	IPS_CTRL_PADDING
	Padding length for the IPS control structure. ============================================================================.

Define Documentation

#define SHMEM_INTERFACE 0

Interface number for shared memory interface. ============================================================================.

============================================================================

Constant:: SHMEM_INTERFACE

#define PCI_INTERFACE 1

Interface number for PCI interface. ============================================================================.

============================================================================

Constant:: PCI_INTERFACE

#define VLYNQ_INTERFACE 2

Interface number for VLYNQ interface. ============================================================================.

============================================================================

Constant:: VLYNQ_INTERFACE

#define DSP_MAUSIZE 1

Size of the DSP MAU (in bytes). ============================================================================.

============================================================================

Constant:: DSP_MAUSIZE

#define DSPLINK_BUF_ALIGN 128

Alignment of message buffers allocated for transfer. ============================================================================.

============================================================================

Constant:: DSPLINK_BUF_ALIGN

#define ADD_PADDING	(	padVar,
		count
	)	Uint16 padVar [count] ;

Macro to add padding to a structure. ============================================================================.

============================================================================

Constant:: ADD_PADDING

#define DSPLINK_ALIGN	(	x,
		y
	)	(Uint32)((Uint32)((x + y - 1) / y) * y)

Macro to align a number. x: The number to be aligned y: The value that the number should be aligned to. ============================================================================.

============================================================================

Constant:: DSPLINK_ALIGN

#define REG ( x ) *((volatile Uint32 *) (x))

Gives the value of a 32-bit register. ============================================================================.

============================================================================

Macro:: REG

#define RTC_REG_VALUE ( x ) *((volatile Uint32 *) (x))

Gives the value of a 32-bit register. ============================================================================.

============================================================================

Macro:: RTC_REG_VALUE

#define CACHE_L2_LINESIZE 128

Line size of DSP L2 cache (in bytes). ============================================================================.

============================================================================

Constant:: CACHE_L2_LINESIZE

#define DSPLINK_16BIT_PADDING ((CACHE_L2_LINESIZE - sizeof (Uint16)) / 2)

Padding required for alignment of a 16-bit value (for L2 cache) in 16-bit words. ============================================================================.

============================================================================

Constant:: DSPLINK_16BIT_PADDING

#define DSPLINK_32BIT_PADDING ((CACHE_L2_LINESIZE - sizeof (Uint32)) / 2)

Padding required for alignment of a 32-bit value (for L2 cache) in 16-bit words. ============================================================================.

============================================================================

Constant:: DSPLINK_32BIT_PADDING

#define DSPLINK_BOOL_PADDING ((CACHE_L2_LINESIZE - sizeof (Bool)) / 2)

Padding required for alignment of a Boolean value (for L2 cache) in 16-bit words. ============================================================================.

============================================================================

Constant:: DSPLINK_BOOL_PADDING

#define DSPLINK_PTR_PADDING ((CACHE_L2_LINESIZE - sizeof (Void *)) / 2)

Padding required for alignment of a pointer value (for L2 cache) in 16-bit words. ============================================================================.

============================================================================

Constant:: DSPLINK_PTR_PADDING

#define LDRV_DRV_CTRL_SIZE

Value:

(   (sizeof (Uint32) * 23)                      \
                            +  (sizeof (Char8) * DSP_MAX_STRLEN)           \
                            +  (sizeof (Uint32) * 4))

Padding required for DSP L2 cache line alignment within LDRV_DRV control structure. ============================================================================.

============================================================================

Constant:: LDRV_DRV_PADDING

#define LDRV_DRV_PADDING

Value:

((     DSPLINK_ALIGN (LDRV_DRV_CTRL_SIZE,       \
                                                 DSPLINK_BUF_ALIGN)        \
                             -    LDRV_DRV_CTRL_SIZE) / 2)

#define LDRV_IPS_CTRL_PADDING

Value:

(  (CACHE_L2_LINESIZE                    \
                                  - (   sizeof (Uint32)                   \
                                     +  (sizeof (Uint32) * 6))) / 2)

Padding length for the IPS shared configuration structure. ============================================================================.

============================================================================

Constant:: LDRV_IPS_CTRL_PADDING

#define IPS_EVENT_ENTRY_PADDING

Value:

(  (CACHE_L2_LINESIZE                          \
                                - (((sizeof (Uint32)) * 3))) / 2)

#define IPS_CTRL_PADDING

Value:

(  (CACHE_L2_LINESIZE                             \
                              - (sizeof (Void *) * 6)) / 2)

Padding length for the IPS control structure. ============================================================================.

============================================================================

Constant:: IPS_CTRL_PADDING

archdefs.h File Reference

Detailed Description

Defines

Define Documentation