J721S2 Firewall Descriptions¶
Introduction¶
This chapter provides information on firewalls that system firmware configures by default at boot time. The guide to read the tables in this chapter is provided below. For more details on firewalls, refer to the “Interconnect Firewalls” section of the TRM and Firewall TISCI Description.
Table Legend¶
Firewall ID: The unique identifier for each firewallOwner: The host ID that owns the firewallCBA_PERMISSION_x: Each permission slot takes the form of [user, permission], where “user” is a host ID and “permission” is a combination of r-read, w-write, c-cache, d-debug. Additionally, each firewall region/channel can have up to 3 slots for configuring permissions.
Table Guide¶
- If a firewall is owned by
TIFS/DMSC, it means that only TIFS/DMSC can configure it. - If a firewall is owned by
none, it means any host can configure it. - If a firewall is owned by
rm, it means that the corresponding resource is managed by the resource manager based on the RM boardcfg. - If a firewall is not listed in the table below, it does not mean it doesn’t exist. It simply means it was not one of the firewalls configured at boot time by system firmware.
Note
For additional firewall information, checkout the Firewall FAQ.
List of Region Based Firewalls¶
| Firewall ID | Region | Owner | Dev Group | Start Address | End Address | CBA_PERMISSION_0 | CBA_PERMISSION_1 | CBA_PERMISSION_2 |
|---|---|---|---|---|---|---|---|---|
| 104 | 0 | tifs | SOC_DEVGRP_MAIN | 0x00A00000 | 0x00A007FF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 105 | 0 | tifs | SOC_DEVGRP_MAIN | 0x00A10000 | 0x00A107FF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 106 | 0 | tifs | SOC_DEVGRP_MAIN | 0x00A20000 | 0x00A207FF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 168 | 0 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x42200000 | 0x422003FF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 512 | 1 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x00014000 | 0x00016FFF | tifs,rc | ||
| 513 | 0 | tifs | SOC_DEVGRP_MCU_WAKEUP | tifs,rwcd | ||||
| 514 | 0 | tifs | SOC_DEVGRP_MCU_WAKEUP | tifs,rwcd | ||||
| 582 | 0 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x44234000 | 0x44234FFF | everyone,r | everyone,r | everyone,r |
| 582 | 1 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x44235000 | 0x44237FFF | tifs,rwcd | tifs,rwcd | tifs,rwcd |
| 602 | 0 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x4423C000 | 0x4423CFFF | tifs,rwcd | ||
| 602 | 1 | hsm | SOC_DEVGRP_MCU_WAKEUP | 0x4423D000 | 0x4423DFFF | hsm,rwcd | ||
| 638 | 0 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x44800000 | 0x44FFFFFF | tifs,rwcd | hsm,rwcd | everyone,r |
| 638 | 1 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x43702000 | 0x43702FFF | tifs,rwcd | hsm,rwcd | |
| 638 | 2 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x44880000 | 0x44887FFF | everyone,rwcd | ||
| 638 | 3 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x44914000 | 0x44915FFF | tifs,rwcd | ||
| 638 | 4 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x44918000 | 0x44918FFF | tifs,rwcd | ||
| 638 | 5 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x44940000 | 0x4494FFFF | tifs,rwcd | ||
| 638 | 6 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x44960000 | 0x4496FFFF | tifs,rwcd | ||
| 638 | 7 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x44801000 | 0x44801FFF | tifs,rwcd | ||
| 639 | 0 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x45000000 | 0x45FFFFFF | tifs,rwd | ||
| 639 | 1 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x45D00000 | 0x45DFFFFF | tifs,rwd | everyone,rwcd | everyone,rwcd |
| 639 | 2 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x45B00000 | 0x45BFFFFF | tifs,rwd | everyone,r | everyone,r |
| 639 | 3 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x45000000 | 0x4507FFFF | tifs,rwd | tifs,rwd | |
| 639 | 4 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x45080000 | 0x450FFFFF | tifs,rwd | ||
| 639 | 5 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x45100000 | 0x45624FFF | tifs,rwd | tifs,rwd | |
| 639 | 6 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x45800000 | 0x458FFFFF | tifs,rwd | tifs,rwd | |
| 641 | 0 | none | SOC_DEVGRP_MCU_WAKEUP | 0x43C00000 | 0x43C2FFFF | pulsar_0,rwcd | hsm,rwcd | |
| 642 | 0 | none | SOC_DEVGRP_MCU_WAKEUP | 0x43C30000 | 0x43C3FFFF | pulsar_0,rwcd | hsm,rwcd | |
| 672 | 0 | hsm | SOC_DEVGRP_MCU_WAKEUP | 0x43936000 | 0x43936FFF | hsm,rwcd | ||
| 673 | 0 | hsm | SOC_DEVGRP_MCU_WAKEUP | 0x43935000 | 0x439350FF | hsm,rwcd | ||
| 680 | 0 | hsm | SOC_DEVGRP_MCU_WAKEUP | 0x43A00000 | 0x43A00FFF | hsm,rwcd | ||
| 690 | 0 | hsm | SOC_DEVGRP_MCU_WAKEUP | 0x43701000 | 0x437013FF | hsm,rwcd | ||
| 1050 | 1 | none | SOC_DEVGRP_MCU_WAKEUP | 0x41C00000 | 0x41CFFFFF | everyone,rwcd | everyone,rwcd | everyone,rwcd |
| 1208 | 0 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x40C00000 | 0x40C000FF | tifs,rwcd | tifs,rwcd | tifs,rwcd |
| 1276 | 1 | hsm | SOC_DEVGRP_MCU_WAKEUP | 0x43604000 | 0x43607FFF | everyone,rwcd | ||
| 1276 | 0 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x43600000 | 0x4360FFFF | tifs,rwcd | ||
| 1280 | 0 | none | SOC_DEVGRP_MCU_WAKEUP | 0x00000000 | 0xFFFFFFFFFFF | everyone,rwcd | everyone,rwcd | everyone,rwcd |
| 2306 | 0 | none | SOC_DEVGRP_MAIN | 0x00000000 | 0xFFFFFFFFFFF | everyone,rwcd | everyone,rwcd | everyone,rwcd |
| 2308 | 0 | tifs | SOC_DEVGRP_MAIN | 0x053F0000 | 0x053F00FF | tifs,rwcd | tifs,rwcd | tifs,rwcd |
| 2465 | 0 | tifs | SOC_DEVGRP_MAIN | 0x00000000 | 0xFFFFFFFFFFF | tifs,rwcd | ||
| 4160 | 0 | tifs | SOC_DEVGRP_MAIN | 0x38000000 | 0x383FFFFF | tifs,rwcd | pulsar_0,rwcd | everyone,rwcd |
| 4288 | 0 | tifs | SOC_DEVGRP_MAIN | 0x31080000 | 0x310BFFFF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 4288 | 1 | tifs | SOC_DEVGRP_MAIN | 0x31160000 | 0x311603FF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 4288 | 2 | tifs | SOC_DEVGRP_MAIN | 0x32000000 | 0x3201FFFF | tifs,rwcd | pulsar_0,rwcd | everyone,rwcd |
| 4288 | 3 | tifs | SOC_DEVGRP_MAIN | 0x3C000000 | 0x3C3FFFFF | tifs,rwcd | pulsar_0,rwcd | everyone,rwcd |
| 4352 | 0 | tifs | SOC_DEVGRP_MAIN | 0x30802000 | 0x3080201F | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 4352 | 1 | tifs | SOC_DEVGRP_MAIN | 0x30880000 | 0x3088FFFF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 4352 | 2 | tifs | SOC_DEVGRP_MAIN | 0x30940000 | 0x3094FFFF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 4352 | 3 | tifs | SOC_DEVGRP_MAIN | 0x31040000 | 0x31043FFF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 4352 | 4 | tifs | SOC_DEVGRP_MAIN | 0x31100000 | 0x31101FFF | tifs,rwcd | pulsar_0,rwcd | everyone,rwcd |
| 4352 | 5 | tifs | SOC_DEVGRP_MAIN | 0x31110000 | 0x31113FFF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 4352 | 6 | tifs | SOC_DEVGRP_MAIN | 0x33800000 | 0x339FFFFF | tifs,rwcd | pulsar_0,rwcd | everyone,rwcd |
| 4352 | 7 | tifs | SOC_DEVGRP_MAIN | 0x33D00000 | 0x33DFFFFF | tifs,rwcd | pulsar_0,rwcd | everyone,rwcd |
| 4384 | 0 | tifs | SOC_DEVGRP_MAIN | 0x30B00000 | 0x30B1FFFF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 4384 | 1 | tifs | SOC_DEVGRP_MAIN | 0x30C00000 | 0x30C07FFF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 4384 | 2 | tifs | SOC_DEVGRP_MAIN | 0x30D00000 | 0x30D03FFF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 4384 | 3 | tifs | SOC_DEVGRP_MAIN | 0x31150000 | 0x311500FF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 4384 | 4 | tifs | SOC_DEVGRP_MAIN | 0x34000000 | 0x3407FFFF | tifs,rwcd | pulsar_0,rwcd | everyone,rwcd |
| 4384 | 5 | tifs | SOC_DEVGRP_MAIN | 0x35000000 | 0x351FFFFF | tifs,rwcd | pulsar_0,rwcd | everyone,rwcd |
| 4392 | 0 | tifs | SOC_DEVGRP_MAIN | 0x311A0000 | 0x311A00FF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 4392 | 1 | tifs | SOC_DEVGRP_MAIN | 0x35840000 | 0x35840FFF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 4392 | 2 | tifs | SOC_DEVGRP_MAIN | 0x35880000 | 0x35881FFF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 4392 | 3 | tifs | SOC_DEVGRP_MAIN | 0x35900000 | 0x35903FFF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 4392 | 4 | tifs | SOC_DEVGRP_MAIN | 0x35C00000 | 0x35C0FFFF | tifs,rwcd | pulsar_0,rwcd | everyone,rwcd |
| 4392 | 5 | tifs | SOC_DEVGRP_MAIN | 0x35D00000 | 0x35D1FFFF | tifs,rwcd | pulsar_0,rwcd | everyone,rwcd |
| 4392 | 6 | tifs | SOC_DEVGRP_MAIN | 0x35E00000 | 0x35E7FFFF | tifs,rwcd | pulsar_0,rwcd | everyone,rwcd |
| 4394 | 0 | tifs | SOC_DEVGRP_MAIN | 0x31F78000 | 0x31F781FF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 4660 | 0 | tifs | SOC_DEVGRP_MAIN | 0x30800000 | 0x3080001F | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 4660 | 1 | tifs | SOC_DEVGRP_MAIN | 0x30900000 | 0x30901FFF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 4660 | 2 | tifs | SOC_DEVGRP_MAIN | 0x33C00000 | 0x33C3FFFF | tifs,rwcd | pulsar_0,rwcd | everyone,rwcd |
| 4668 | 0 | tifs | SOC_DEVGRP_MAIN | 0x30801000 | 0x3080101F | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 4668 | 1 | tifs | SOC_DEVGRP_MAIN | 0x30908000 | 0x30909FFF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 4668 | 2 | tifs | SOC_DEVGRP_MAIN | 0x33C40000 | 0x33C7FFFF | tifs,rwcd | pulsar_0,rwcd | everyone,rwcd |
| 4676 | 0 | tifs | SOC_DEVGRP_MAIN | 0x31120000 | 0x311200FF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 4676 | 1 | tifs | SOC_DEVGRP_MAIN | 0x31130000 | 0x31133FFF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 4676 | 2 | tifs | SOC_DEVGRP_MAIN | 0x33400000 | 0x3343FFFF | tifs,rwcd | pulsar_0,rwcd | everyone,rwcd |
| 4704 | 0 | tifs | SOC_DEVGRP_MAIN | 0x31140000 | 0x329FFFFF | tifs,rwcd | everyone,r | |
| 4712 | 0 | tifs | SOC_DEVGRP_MAIN | 0x33000000 | 0x3303FFFF | tifs,rwcd | pulsar_0,rwcd | everyone,rwcd |
| 4736 | 0 | tifs | SOC_DEVGRP_MAIN | everyone,rwcd | ||||
| 5140 | 0 | none | SOC_DEVGRP_MAIN | 0x70000000 | 0x703EFFFF | everyone,rwcd | everyone,rwcd | everyone,rwcd |
| 5140 | 20 | tifs | SOC_DEVGRP_MAIN | 0x60000000 | 0x6CFFFFFF | everyone,rwcd | everyone,rwcd | everyone,rwcd |
| 5140 | 21 | none | SOC_DEVGRP_MAIN | 0x6D000000 | 0x6DFFFFFF | everyone,rwcd | everyone,rwcd | everyone,rwcd |
| 5140 | 22 | tifs | SOC_DEVGRP_MAIN | 0x6E000000 | 0x6EFFFFFF | tifs,rwcd | everyone,r | |
| 5140 | 23 | tifs | SOC_DEVGRP_MAIN | sproxy_private,rwcd | ||||
| 5141 | 0 | none | SOC_DEVGRP_MAIN | 0x70000000 | 0x703EFFFF | everyone,rwcd | everyone,rwcd | everyone,rwcd |
| 5141 | 20 | tifs | SOC_DEVGRP_MAIN | 0x60000000 | 0x6CFFFFFF | everyone,rwcd | everyone,rwcd | everyone,rwcd |
| 5141 | 21 | none | SOC_DEVGRP_MAIN | 0x6D000000 | 0x6DFFFFFF | everyone,rwcd | everyone,rwcd | everyone,rwcd |
| 5141 | 22 | tifs | SOC_DEVGRP_MAIN | 0x6E000000 | 0x6EFFFFFF | tifs,rwcd | everyone,r | |
| 5141 | 23 | tifs | SOC_DEVGRP_MAIN | sproxy_private,rwcd | ||||
| 6148 | 0 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x28590000 | 0x285900FF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 6148 | 1 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x285A0000 | 0x285A3FFF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 6148 | 2 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x2A580000 | 0x2A5BFFFF | tifs,rwcd | pulsar_0,rwcd | everyone,rwcd |
| 6156 | 1 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x285B0000 | 0x2A47FFFF | tifs,rwcd | everyone,r | everyone,r |
| 6176 | 0 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x28440000 | 0x2847FFFF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 6176 | 1 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x285D0000 | 0x285D03FF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 6176 | 2 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x2A280000 | 0x2A29FFFF | tifs,rwcd | pulsar_0,rwcd | everyone,rwcd |
| 6176 | 3 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x2B800000 | 0x2BBFFFFF | tifs,rwcd | pulsar_0,rwcd | everyone,rwcd |
| 6240 | 0 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x283C0000 | 0x283C001F | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 6240 | 1 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x28480000 | 0x28481FFF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 6240 | 2 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x28560000 | 0x28563FFF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 6240 | 3 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x28570000 | 0x285701FF | tifs,rwcd | pulsar_0,rwcd | everyone,rwcd |
| 6240 | 4 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x28580000 | 0x28580FFF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 6240 | 5 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x2A600000 | 0x2A6FFFFF | tifs,rwcd | pulsar_0,rwcd | everyone,rwcd |
| 6240 | 6 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x2A700000 | 0x2A7FFFFF | tifs,rwcd | pulsar_0,rwcd | everyone,rwcd |
| 6248 | 0 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x28400000 | 0x28401FFF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 6248 | 1 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x284A0000 | 0x284A3FFF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 6248 | 2 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x284C0000 | 0x284C3FFF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 6248 | 3 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x285C0000 | 0x285C00FF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 6248 | 4 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x2A800000 | 0x2A83FFFF | tifs,rwcd | pulsar_0,rwcd | everyone,rwcd |
| 6248 | 5 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x2AA00000 | 0x2AA3FFFF | tifs,rwcd | pulsar_0,rwcd | everyone,rwcd |
| 6250 | 0 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x2A268000 | 0x2A2681FF | tifs,rwcd | pulsar_0,rwcd | everyone,r |
| 6260 | 0 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x2A500000 | 0x2A53FFFF | tifs,rwcd | pulsar_0,rwcd | everyone,rwcd |
| 6268 | 0 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x2A480000 | 0x2A4FFFFF | everyone,rwcd | everyone,rwcd | everyone,rwcd |
| 6269 | 0 | tifs | SOC_DEVGRP_MCU_WAKEUP | sproxy_private,rwcd | ||||
| 6288 | 0 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0x2B000000 | 0x2B3FFFFF | tifs,rwcd | pulsar_0,rwcd | everyone,rwcd |
Note
- For this firewall ID, region 23, the memory range will be based on the MSMC memory configuration.
- The memory range shown as “MSMC Memory (communication) 64Kbytes, at below link would be the memory range applied to region 23. [TISCI_MSG_QUERY_MSC|TISCI General Message API Documentation — TISCI User Guide]
For more details on firewalls, refer to the “Interconnect Firewalls” section of the TRM.
List of Channelized Firewalls¶
| Firewall ID | Owner | Dev Group | Start Channel | End Channel | CBA_PERMISSION_0 | CBA_PERMISSION_1 | CBA_PERMISSION_2 |
|---|---|---|---|---|---|---|---|
| 4128 | tifs | SOC_DEVGRP_MAIN | 768 | 877 | sproxy_private,rwcd | ||
| 4224 | tifs | SOC_DEVGRP_MAIN | 768 | 877 | sproxy_private,rwcd | ||
| 4224 | rm | SOC_DEVGRP_MAIN | 1024 | 1055 | everyone,r | ||
| 4320 | rm | SOC_DEVGRP_MAIN | 0 | 0 | block_everyone,r | ||
| 4320 | rm | SOC_DEVGRP_MAIN | 256 | 256 | block_everyone,r | ||
| 4368 | rm | SOC_DEVGRP_MAIN | 0 | 0 | block_everyone,r | ||
| 4368 | rm | SOC_DEVGRP_MAIN | 1 | 340 | tifs,r | ||
| 4368 | rm | SOC_DEVGRP_MAIN | 341 | 341 | block_everyone,r | ||
| 4368 | rm | SOC_DEVGRP_MAIN | 342 | 422 | tifs,r | ||
| 4388 | rm | SOC_DEVGRP_MAIN | 0 | 0 | block_everyone,r | ||
| 4388 | rm | SOC_DEVGRP_MAIN | 1 | 15 | tifs,r | ||
| 4388 | rm | SOC_DEVGRP_MAIN | 16 | 16 | block_everyone,r | ||
| 4388 | rm | SOC_DEVGRP_MAIN | 17 | 47 | tifs,r | ||
| 4656 | rm | SOC_DEVGRP_MAIN | 0 | 0 | block_everyone,r | ||
| 4664 | rm | SOC_DEVGRP_MAIN | 0 | 0 | block_everyone,r | ||
| 4672 | rm | SOC_DEVGRP_MAIN | 0 | 0 | block_everyone,r | ||
| 4688 | tifs | SOC_DEVGRP_MAIN | 0 | 369 | tifs,rwcd | everyone,r | |
| 4708 | rm | SOC_DEVGRP_MAIN | 0 | 0 | block_everyone,r | ||
| 4720 | tifs | SOC_DEVGRP_MAIN | 0 | 9 | a72_secure_supervisor,rwcd | ||
| 4720 | tifs | SOC_DEVGRP_MAIN | 10 | 24 | a72_non_secure_supervisor,rwcd | ||
| 4720 | tifs | SOC_DEVGRP_MAIN | 25 | 29 | main_0_c7x_0_secure,rwcd | ||
| 4720 | tifs | SOC_DEVGRP_MAIN | 30 | 34 | main_0_c7x_0_nonsecure,rwcd | ||
| 4720 | tifs | SOC_DEVGRP_MAIN | 35 | 39 | main_1_c7x_0_secure,rwcd | ||
| 4720 | tifs | SOC_DEVGRP_MAIN | 40 | 44 | main_1_c7x_0_nonsecure,rwcd | ||
| 4720 | tifs | SOC_DEVGRP_MAIN | 45 | 49 | gpu_0,rwcd | ||
| 4720 | tifs | SOC_DEVGRP_MAIN | 50 | 54 | main_0_r5_0_nonsecure,rwcd | ||
| 4720 | tifs | SOC_DEVGRP_MAIN | 55 | 59 | main_0_r5_0_secure,rwcd | ||
| 4720 | tifs | SOC_DEVGRP_MAIN | 60 | 64 | main_0_r5_1_nonsecure,rwcd | ||
| 4720 | tifs | SOC_DEVGRP_MAIN | 65 | 69 | main_0_r5_1_secure,rwcd | ||
| 4720 | tifs | SOC_DEVGRP_MAIN | 70 | 74 | main_1_r5_0_nonsecure,rwcd | ||
| 4720 | tifs | SOC_DEVGRP_MAIN | 75 | 79 | main_1_r5_0_secure,rwcd | ||
| 4720 | tifs | SOC_DEVGRP_MAIN | 80 | 84 | main_1_r5_1_nonsecure,rwcd | ||
| 4720 | tifs | SOC_DEVGRP_MAIN | 85 | 89 | main_1_r5_1_secure,rwcd | ||
| 4720 | tifs | SOC_DEVGRP_MAIN | 328 | 350 | dm,rwcd | ||
| 4720 | tifs | SOC_DEVGRP_MAIN | 351 | 369 | tifs,rwcd | ||
| 6146 | rm | SOC_DEVGRP_MCU_WAKEUP | 0 | 0 | block_everyone,r | ||
| 6152 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0 | 4 | tifs,rwcd | everyone,r | |
| 6152 | tifs | SOC_DEVGRP_MCU_WAKEUP | 5 | 5 | everyone,r | tifs,rwcd | |
| 6152 | tifs | SOC_DEVGRP_MCU_WAKEUP | 6 | 89 | tifs,rwcd | everyone,r | |
| 6160 | rm | SOC_DEVGRP_MCU_WAKEUP | 286 | 317 | everyone,r | ||
| 6208 | rm | SOC_DEVGRP_MCU_WAKEUP | 0 | 255 | tifs,rwcd | ||
| 6208 | rm | SOC_DEVGRP_MCU_WAKEUP | 256 | 511 | tifs,rwcd | ||
| 6244 | rm | SOC_DEVGRP_MCU_WAKEUP | 0 | 0 | block_everyone,r | ||
| 6244 | rm | SOC_DEVGRP_MCU_WAKEUP | 1 | 47 | tifs,r | ||
| 6244 | rm | SOC_DEVGRP_MCU_WAKEUP | 48 | 48 | block_everyone,r | ||
| 6244 | rm | SOC_DEVGRP_MCU_WAKEUP | 49 | 95 | tifs,r | ||
| 6256 | rm | SOC_DEVGRP_MCU_WAKEUP | 0 | 0 | block_everyone,r | ||
| 6264 | tifs | SOC_DEVGRP_MCU_WAKEUP | 0 | 9 | pulsar_0,rwcd | ||
| 6264 | tifs | SOC_DEVGRP_MCU_WAKEUP | 10 | 19 | pulsar_1,rwcd | ||
| 6264 | tifs | SOC_DEVGRP_MCU_WAKEUP | 20 | 24 | pulsar_0,rwcd | ||
| 6264 | tifs | SOC_DEVGRP_MCU_WAKEUP | 25 | 29 | tifs,rwcd | ||
| 6264 | tifs | SOC_DEVGRP_MCU_WAKEUP | 72 | 80 | dm,rwcd | ||
| 6264 | tifs | SOC_DEVGRP_MCU_WAKEUP | 81 | 89 | tifs,rwcd | ||
| 6272 | tifs | SOC_DEVGRP_MCU_WAKEUP | 256 | 285 | sproxy_private,rwcd |
List of priv-ids¶
| Master name | priv-id | secure | non-secure | privileged | user | HOST-IDs |
|---|---|---|---|---|---|---|
| a72_non_secure_supervisor | 1 | False | True | True | False | 12,13,14 |
| a72_secure_supervisor | 1 | True | False | True | False | 10,11 |
| sproxy_private | 11 | True | True | True | True | N/A |
| main_0_c7x_0_secure | 21 | True | False | True | True | 20 |
| main_0_c7x_0_nonsecure | 21 | False | True | True | True | 21 |
| main_1_c7x_0_secure | 26 | True | False | True | True | 22 |
| main_1_c7x_0_nonsecure | 26 | False | True | True | True | 23 |
| pulsar_0 | 96 | True | True | True | False | 3,4 |
| dm | 96 | True | True | True | False | N/A |
| pulsar_1 | 97 | True | True | True | False | 5,6 |
| gpu_0 | 187 | False | True | True | True | 30 |
| everyone | 195 | True | True | True | True | N/A |
| block_everyone | 197 | True | True | True | True | N/A |
| tifs | 202 | True | True | True | True | N/A |
| hsm | 204 | False | True | True | True | 253 |
| main_0_r5_0_nonsecure | 212 | False | True | True | True | 35 |
| main_0_r5_0_secure | 212 | True | False | True | True | 36 |
| main_0_r5_1_nonsecure | 213 | False | True | True | True | 37 |
| main_0_r5_1_secure | 213 | True | False | True | True | 38 |
| main_1_r5_0_nonsecure | 214 | False | True | True | True | 40 |
| main_1_r5_0_secure | 214 | True | False | True | True | 41 |
| main_1_r5_1_nonsecure | 215 | False | True | True | True | 42 |
| main_1_r5_1_secure | 215 | True | False | True | True | 43 |
Note
- NOTE: pulsar_0 refers to cores MCU_0_R5_0(Non Secure) and MCU_0_R5_1(Secure). pulsar_1 refers to MCU_0_R5_2(Non Secure)
- and MCU_0_R5_3(Secure)