Resource Management UDMAP TISCI Message Description¶
Introduction¶
This chapter provides information on usage of the RM UDMAP management TISCI message API parameters.
| TISCI Message ID | Message Name |
|---|---|
| 0x1200 | RESERVED, DO NOT (RE)USE |
| 0x1201 | RESERVED, DO NOT (RE)USE |
| 0x1210 | RESERVED, DO NOT (RE)USE |
| 0x1211 | RESERVED, DO NOT (RE)USE |
| 0x1220 | RESERVED, DO NOT (RE)USE |
| 0x1221 | RESERVED, DO NOT (RE)USE |
| 0x1205 | TISCI_MSG_RM_UDMAP_TX_CH_CFG |
| N/A | TISCI_MSG_RM_UDMAP_TX_CH_CFG Response |
| 0x1206 | RESERVED, DO NOT (RE)USE |
| 0x1215 | TISCI_MSG_RM_UDMAP_RX_CH_CFG |
| N/A | TISCI_MSG_RM_UDMAP_RX_CH_CFG Response |
| 0x1216 | RESERVED, DO NOT (RE)USE |
| 0x1230 | TISCI_MSG_RM_UDMAP_FLOW_CFG |
| N/A | TISCI_MSG_RM_UDMAP_FLOW_CFG Response |
| 0x1231 | TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG |
| N/A | TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG Response |
| 0x1232 | RESERVED, DO NOT (RE)USE |
| 0x1233 | RESERVED, DO NOT (RE)USE |
| 0x1234 | TISCI_MSG_RM_UDMAP_FLOW_DELEGATE |
| N/A | TISCI_MSG_RM_UDMAP_FLOW_DELEGATE Response |
| 0x1240 | TISCI_MSG_RM_UDMAP_GCFG_CFG |
| N/A | TISCI_MSG_RM_UDMAP_GCFG_CFG Response |
| 0x1241 | RESERVED, DO NOT (RE)USE |
UDMAP Valid Parameters Field Usage¶
Some UDMAP TISCI message APIs make use of a valid_params bit field. Bits within the valid_params field define whether or not individual TISCI message parameters are valid. When a bit corresponding to a parameter is set (to 1) the parameter is considered valid and will be programmed into its corresponding register field, assuming validation of the parameter passes. When a valid_params bit is not set, i.e. a value of 0, the corresponding register field is read and used within the validation process of the request. The register field for a parameter is not programmed if the corresponding valid_params bit is not set.
TISCI_MSG_RM_UDMAP_TX_CH_CFG - UDMAP Transmit Channel Configure¶
UDMAP Transmit Channel Configure Request¶
The UDMAP tx channel cfg TISCI message API is used to configure SoC Navigator Subsystem UDMAP transmit channels. The API only allows configuration of a transmit channel by passing the tx channel index and the Navigator SoC device ID in which the channel is located. Only the non-real-time transmit channel registers are programmed as part of the channel configuration. The host is granted access to the transmit channel real-time registers via the SoC channelized firewalls based on the RM board configuration. The OS can access the channel real-time registers directly after transmit channel configuration is complete.
The UDMAP global invalid receive flow event and per transmit channel output event (OES) and error output event (EOES) registers are not programmed as part of the UDMAP tx channel cfg API. They’re programmed internally via the RM IRQ Set message.
The UDMAP tx channel cfg API can be used to configure transmit channels within any Navigator Subsystem UDMAP on the device.
Usage¶
| Message Type | Normal |
| Secure Queue Only? | No |
TISCI Message ID¶
TISCI_MSG_RM_UDMAP_TX_CH_CFG (0x1205U)
RM TISCI message to configure a Navigator Subsystem UDMAP transmit channel
UDMAP Transmit Channel Configure Message Parameters¶
struct tisci_msg_rm_udmap_tx_ch_cfg_req
Configures a Navigator Subsystem UDMAP transmit channel
| Parameter | Type | Description |
|---|---|---|
| hdr | struct tisci_header | Standard TISCI header |
| valid_params | u32 | Bitfield defining validity of tx channel configuration parameters. The tx channel configuration fields are not valid, and will not be used for ch configuration, if their corresponding valid bit is zero. Valid bit usage: 0 - Valid bit for @ref tisci_msg_rm_udmap_tx_ch_cfg_req::tx_pause_on_err 1 - Valid bit for @ref tisci_msg_rm_udmap_tx_ch_cfg_req::tx_atype 2 - Valid bit for @ref tisci_msg_rm_udmap_tx_ch_cfg_req::tx_chan_type 3 - Valid bit for @ref tisci_msg_rm_udmap_tx_ch_cfg_req::tx_fetch_size 4 - Valid bit for @ref tisci_msg_rm_udmap_tx_ch_cfg_req::txcq_qnum 5 - Valid bit for @ref tisci_msg_rm_udmap_tx_ch_cfg_req::tx_priority 6 - Valid bit for @ref tisci_msg_rm_udmap_tx_ch_cfg_req::tx_qos 7 - Valid bit for @ref tisci_msg_rm_udmap_tx_ch_cfg_req::tx_orderid 8 - Valid bit for @ref tisci_msg_rm_udmap_tx_ch_cfg_req::tx_sched_priority 9 - Valid bit for @ref tisci_msg_rm_udmap_tx_ch_cfg_req::tx_filt_einfo 10 - Valid bit for @ref tisci_msg_rm_udmap_tx_ch_cfg_req::tx_filt_pswords 11 - Valid bit for @ref tisci_msg_rm_udmap_tx_ch_cfg_req::tx_supr_tdpkt 12 - Valid bit for @ref tisci_msg_rm_udmap_tx_ch_cfg_req::tx_credit_count 13 - Valid bit for @ref tisci_msg_rm_udmap_tx_ch_cfg_req::fdepth 14 - Valid bit for @ref tisci_msg_rm_udmap_tx_ch_cfg_req::tx_burst_size 15 - Valid bit for @ref tisci_msg_rm_udmap_tx_ch_cfg_req::tx_tdtype 16 - Valid bit for @ref tisci_msg_rm_udmap_tx_ch_cfg_req::extended_ch_type |
| nav_id | u16 | SoC device ID of Navigator Subsystem where tx channel is located |
| index | u16 | UDMAP transmit channel index. |
| tx_pause_on_err | u8 | UDMAP transmit channel pause on error configuration to be programmed into the tx_pause_on_err field of the channel’s TCHAN_TCFG register. Can be set to: @ref TISCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERROR_DISABLED @ref TISCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERROR_ENABLED |
| tx_filt_einfo | u8 | UDMAP transmit channel extended packet information passing configuration to be programmed into the tx_filt_einfo field of the channel’s TCHAN_TCFG register. Can be set to: @ref TISCI_MSG_VALUE_RM_UDMAP_TX_CH_FILT_EINFO_DISABLED @ref TISCI_MSG_VALUE_RM_UDMAP_TX_CH_FILT_EINFO_ENABLED |
| tx_filt_pswords | u8 | UDMAP transmit channel protocol specific word passing configuration to be programmed into the tx_filt_pswords field of the channel’s TCHAN_TCFG register. Can be set to: @ref TISCI_MSG_VALUE_RM_UDMAP_TX_CH_FILT_PSWORDS_DISABLED @ref TISCI_MSG_VALUE_RM_UDMAP_TX_CH_FILT_PSWORDS_ENABLED |
| tx_atype | u8 | UDMAP transmit channel non Ring Accelerator access pointer interpretation configuration to be programmed into the tx_atype field of the channel’s TCHAN_TCFG register. Can be set to @ref TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_PHYS @ref TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_INTERMEDIATE @ref TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VIRTUAL @ref TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_NON_COHERENT |
| tx_chan_type | u8 | UDMAP transmit channel functional channel type and work passing mechanism configuration to be programmed into the tx_chan_type field of the channel’s TCHAN_TCFG register. Can be set to @ref TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_PACKET @ref TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_DMA_REF @ref TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_DMA_VAL @ref TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_BLOCK_REF @ref TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_BLOCK_VAL |
| tx_supr_tdpkt | u8 | UDMAP transmit channel teardown packet generation suppression configuration to be programmed into the tx_supr_tdpkt field of the channel’s TCHAN_TCFG register. Can be set to: @ref TISCI_MSG_VALUE_RM_UDMAP_TX_CH_SUPPRESS_TD_DISABLED @ref TISCI_MSG_VALUE_RM_UDMAP_TX_CH_SUPPRESS_TD_ENABLED |
| tx_fetch_size | u16 | UDMAP transmit channel number of 32-bit descriptor words to fetch configuration to be programmed into the tx_fetch_size field of the channel’s TCHAN_TCFG register. The user must make sure to set the maximum word count that can pass through the channel for any allowed descriptor type. Cannot be greater than @ref TISCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_MAX |
| tx_credit_count | u8 | UDMAP transmit channel transfer request credit count configuration to be programmed into the count field of the TCHAN_TCREDIT register. Specifies how many credits for complete TRs are available. This field is only used when configuring a transmit channel of external type and cannot be greater than @ref TISCI_MSG_VALUE_RM_UDMAP_TX_CH_CREDIT_CNT_MAX |
| txcq_qnum | u16 | UDMAP transmit channel completion queue configuration to be programmed into the txcq_qnum field of the TCHAN_TCQ register. The specified completion queue must be assigned to the host, or a subordinate of the host, requesting configuration of the transmit channel. |
| tx_priority | u8 | UDMAP transmit channel transmit priority value to be programmed into the priority field of the channel’s TCHAN_TPRI_CTRL register. This parameter cannot be greater than @ref TISCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_MAX. |
| tx_qos | u8 | UDMAP transmit channel transmit qos value to be programmed into the qos field of the channel’s TCHAN_TPRI_CTRL register. This parameter cannot be greater than @ref TISCI_MSG_VALUE_RM_UDMAP_CH_QOS_MAX. |
| tx_orderid | u8 | UDMAP transmit channel bus order id value to be programmed into the orderid field of the channel’s TCHAN_TPRI_CTRL register. This parameter cannot be greater than @ref TISCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_MAX. |
| fdepth | u16 | UDMAP transmit channel FIFO depth configuration to be programmed into the fdepth field of the TCHAN_TFIFO_DEPTH register. Sets the number of Tx FIFO bytes which are allowed to be stored for the channel. This field is not supported for external channels. The TISCI message is rejected if a non-zero, valid, value is provided during external channel configuration. Check the UDMAP section of the TRM for restrictions regarding this parameter. |
| tx_sched_priority | u8 | UDMAP transmit channel tx scheduling priority configuration to be programmed into the priority field of the channel’s TCHAN_TST_SCHED register. Can be set to @ref TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_HIGH @ref TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_MEDHIGH @ref TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_MEDLOW @ref TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_LOW |
| tx_burst_size | u8 | UDMAP transmit channel burst size configuration to be programmed into the tx_burst_size field of the TCHAN_TCFG register. Can be set to: @ref TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_64_BYTES @ref TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_128_BYTES @ref TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_256_BYTES This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID is set in @ref tisci_msg_rm_udmap_tx_ch_cfg_req::valid_params. This field is not supported on some SoCs. On SoCs that do not support this field the input is quietly ignored even if the valid bit is set. |
| tx_tdtype | u8 | UDMAP transmit channel teardown type configuration to be programmed into the tdtype field of the TCHAN_TCFG register. Can be set to: @ref TISCI_MSG_VALUE_RM_UDMAP_TX_CH_TDTYPE_IMMEDIATE @ref TISCI_MSG_VALUE_RM_UDMAP_TX_CH_TDTYPE_WAIT This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID is set in @ref tisci_msg_rm_udmap_tx_ch_cfg_req::valid_params. This field is not supported on some SoCs. On SoCs that do not support this field the input is quietly ignored even if the valid bit is set. |
| extended_ch_type | u8 | Extended Channel Type specific to BCDMA. A value of zero is the NULL extended_ch_type and applies UDMA and PKTDMA which dont have the MMR region layout that BCDMA does. BCDMA will have an extended_ch_type of value 1 assigned to block copy channels. So for BCDMA, supplying extended_ch_type value of 0 gets you access to the split TR TX channels. A value of 1 get you access to the block copy channels. |
Configures the non-real-time registers of a Navigator Subsystem UDMAP transmit channel. The channel index must be assigned to the host defined in the TISCI header via the RM board configuration resource assignment range list. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID is set in @ref tisci_msg_rm_udmap_tx_ch_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID is set in @ref tisci_msg_rm_udmap_tx_ch_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID is set in @ref tisci_msg_rm_udmap_tx_ch_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID is set in @ref tisci_msg_rm_udmap_tx_ch_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID is set in @ref tisci_msg_rm_udmap_tx_ch_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID is set in @ref tisci_msg_rm_udmap_tx_ch_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID is set in @ref tisci_msg_rm_udmap_tx_ch_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID is set in @ref tisci_msg_rm_udmap_tx_ch_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID is set in @ref tisci_msg_rm_udmap_tx_ch_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID is set in @ref tisci_msg_rm_udmap_tx_ch_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID is set in @ref tisci_msg_rm_udmap_tx_ch_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID is set in @ref tisci_msg_rm_udmap_tx_ch_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID is set in @ref tisci_msg_rm_udmap_tx_ch_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID is set in @ref tisci_msg_rm_udmap_tx_ch_cfg_req::valid_params.
UDMAP Transmit Channel Configuration Valid Parameters¶
The following table describes the valid bit mappings for the UDMAP transmit channel configure message optional parameters:
| valid_params Bit | Corresponding tisci_msg_rm_udmap_tx_ch_cfg_req Optional Parameter |
|---|---|
| 0 | tx_pause_on_err |
| 1 | tx_atype |
| 2 | tx_chan_type |
| 3 | tx_fetch_size |
| 4 | txcq_qnum |
| 5 | tx_priority |
| 6 | tx_qos |
| 7 | tx_orderid |
| 8 | tx_sched_priority |
| 9 | tx_filt_einfo |
| 10 | tx_filt_pswords |
| 11 | tx_supr_tdpkt |
| 12 | tx_credit_count |
| 13 | fdepth |
| 14 | tx_burst_size |
| 15 | tx_tdtype |
| 16 | extended_ch_type |
UDMAP Transmit Channel Configure Response¶
The udmap tx channel cfg response message returns the result status of the processed udmap tx channel cfg message.
UDMAP Transmit Channel Configure Response Message Parameters¶
struct tisci_msg_rm_udmap_tx_ch_cfg_resp
Response to configuring a UDMAP transmit channel.
| Parameter | Type | Description |
|---|---|---|
| hdr | struct tisci_header | Standard TISCI header |
TISCI_MSG_RM_UDMAP_RX_CH_CFG - UDMAP Receive Channel Configure¶
UDMAP Receive Channel Configure¶
The UDMAP rx channel cfg TISCI message API is used to configure SoC Navigator Subsystem UDMAP receive channels. The API only allows configuration of a receive channel by passing the rx channel index and the Navigator SoC device ID in which the channel is located. Only the non-real-time receive channel registers are programmed as part of the channel configuration. The host is granted access to the receive channel real-time registers via the SoC channelized firewalls based on the RM board configuration. The OS can access the channel real-time registers directly after receive channel configuration is complete.
The UDMAP global invalid receive flow event and per receive channel output event (OES) and error output event (EOES) registers are not programmed as part of the UDMAP rx channel cfg API. They’re programmed internally via the RM IRQ Set message.
The UDMAP rx channel cfg API can be used to configure receive channels within any Navigator Subsystem UDMAP on the device.
Usage¶
| Message Type | Normal |
| Secure Queue Only? | No |
TISCI Message ID¶
TISCI_MSG_RM_UDMAP_RX_CH_CFG (0x1215U)
RM TISCI message to configure a Navigator Subsystem UDMAP receive channel
UDMAP Receive Channel Configure Message Parameters¶
struct tisci_msg_rm_udmap_rx_ch_cfg_req
Configures a Navigator Subsystem UDMAP receive channel
| Parameter | Type | Description |
|---|---|---|
| hdr | struct tisci_header | Standard TISCI header |
| valid_params | u32 | Bitfield defining validity of rx channel configuration parameters. The rx channel configuration fields are not valid, and will not be used for ch configuration, if their corresponding valid bit is zero. Valid bit usage: 0 - Valid bit for @ref tisci_msg_rm_udmap_rx_ch_cfg_req::rx_pause_on_err 1 - Valid bit for @ref tisci_msg_rm_udmap_rx_ch_cfg_req::rx_atype 2 - Valid bit for @ref tisci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type 3 - Valid bit for @ref tisci_msg_rm_udmap_rx_ch_cfg_req::rx_fetch_size 4 - Valid bit for @ref tisci_msg_rm_udmap_rx_ch_cfg_req::rxcq_qnum 5 - Valid bit for @ref tisci_msg_rm_udmap_rx_ch_cfg_req::rx_priority 6 - Valid bit for @ref tisci_msg_rm_udmap_rx_ch_cfg_req::rx_qos 7 - Valid bit for @ref tisci_msg_rm_udmap_rx_ch_cfg_req::rx_orderid 8 - Valid bit for @ref tisci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority 9 - Valid bit for @ref tisci_msg_rm_udmap_rx_ch_cfg_req::flowid_start 10 - Valid bit for @ref tisci_msg_rm_udmap_rx_ch_cfg_req::flowid_cnt 11 - Valid bit for @ref tisci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_short 12 - Valid bit for @ref tisci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_long 14 - Valid bit for @ref tisci_msg_rm_udmap_rx_ch_cfg_req::rx_burst_size |
| nav_id | u16 | SoC device ID of Navigator Subsystem where rx channel is located |
| index | u16 | UDMAP receive channel index. |
| rx_fetch_size | u16 | UDMAP receive channel number of 32-bit descriptor words to fetch configuration to be programmed into the rx_fetch_size field of the channel’s RCHAN_RCFG register. The user must make sure to set the maximum word count that can pass through the channel for any allowed descriptor type. Cannot be greater than @ref TISCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_MAX |
| rxcq_qnum | u16 | UDMAP receive channel completion queue configuration to be programmed into the rxcq_qnum field of the RCHAN_RCQ register. The specified completion queue must be assigned to the host, or a subordinate of the host, requesting configuration of the receive channel. |
| rx_priority | u8 | UDMAP receive channel receive priority value to be programmed into the priority field of the channel’s RCHAN_RPRI_CTRL register. This parameter cannot be greater than @ref TISCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_MAX. |
| rx_qos | u8 | UDMAP receive channel receive qos value to be programmed into the qos field of the channel’s RCHAN_RPRI_CTRL register. This parameter cannot be greater than @ref TISCI_MSG_VALUE_RM_UDMAP_CH_QOS_MAX. |
| rx_orderid | u8 | UDMAP receive channel bus order id value to be programmed into the orderid field of the channel’s RCHAN_RPRI_CTRL register. This parameter cannot be greater than @ref TISCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_MAX. |
| rx_sched_priority | u8 | UDMAP receive channel rx scheduling priority configuration to be programmed into the priority field of the channel’s RCHAN_RST_SCHED register. Can be set to @ref TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_HIGH @ref TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_MEDHIGH @ref TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_MEDLOW @ref TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_LOW |
| flowid_start | u16 | UDMAP receive channel additional flows starting index configuration to program into the flow_start field of the RCHAN_RFLOW_RNG register. Specifies the starting index for flow IDs the receive channel is to make use of beyond the default flow. flowid_start and @ref flowid_cnt must be set as valid and configured together. The starting flow ID set by @ref flowid_cnt must be a flow index within the Navigator Subsystem’s subset of flows beyond the default flows statically mapped to receive channels. The additional flows must be assigned to the host, or a subordinate of the host, requesting configuration of the receive channel. |
| flowid_cnt | u16 | UDMAP receive channel additional flows count configuration to program into the flowid_cnt field of the RCHAN_RFLOW_RNG register. This field specifies how many flow IDs are in the additional contiguous range of legal flow IDs for the channel. @ref flowid_start and flowid_cnt must be set as valid and configured together. Disabling the valid_params field bit for flowid_cnt indicates no flow IDs other than the default are to be allocated and used by the receive channel. @ref flowid_start plus flowid_cnt cannot be greater than the number of receive flows in the receive channel’s Navigator Subsystem. The additional flows must be assigned to the host, or a subordinate of the host, requesting configuration of the receive channel. |
| rx_pause_on_err | u8 | UDMAP receive channel pause on error configuration to be programmed into the rx_pause_on_err field of the channel’s RCHAN_RCFG register. Can be set to: @ref TISCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERROR_DISABLED @ref TISCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERROR_ENABLED |
| rx_atype | u8 | UDMAP receive channel non Ring Accelerator access pointer interpretation configuration to be programmed into the rx_atype field of the channel’s RCHAN_RCFG register. Can be set to @ref TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_PHYS @ref TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_INTERMEDIATE @ref TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VIRTUAL @ref TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_NON_COHERENT |
| rx_chan_type | u8 | UDMAP receive channel functional channel type and work passing mechanism configuration to be programmed into the rx_chan_type field of the channel’s RCHAN_RCFG register. Can be set to @ref TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_PACKET @ref TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_PACKET_SINGLE_BUF @ref TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_DMA_REF @ref TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_DMA_VAL @ref TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_BLOCK_REF @ref TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_3P_BLOCK_VAL |
| rx_ignore_short | u8 | UDMAP receive channel short packet treatment configuration to be programmed into the rx_ignore_short field of the RCHAN_RCFG register. Can be set to: @ref TISCI_MSG_VALUE_RM_UDMAP_RX_CH_PACKET_EXCEPTION @ref TISCI_MSG_VALUE_RM_UDMAP_RX_CH_PACKET_IGNORED |
| rx_ignore_long | u8 | UDMAP receive channel long packet treatment configuration to be programmed into the rx_ignore_long field of the RCHAN_RCFG register. Can be set to: @ref TISCI_MSG_VALUE_RM_UDMAP_RX_CH_PACKET_EXCEPTION @ref TISCI_MSG_VALUE_RM_UDMAP_RX_CH_PACKET_IGNORED |
| rx_burst_size | u8 | UDMAP receive channel burst size configuration to be programmed into the rx_burst_size field of the RCHAN_RCFG register. Can be set to: @ref TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_64_BYTES @ref TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_128_BYTES @ref TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_256_BYTES This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID is set in @ref tisci_msg_rm_udmap_rx_ch_cfg_req::valid_params. This field is not supported on some SoCs. On SoCs that do not support this field the input is quietly ignored even if the valid bit is set. |
Configures the non-real-time registers of a Navigator Subsystem UDMAP receive channel. The channel index must be assigned to the host defined in the TISCI header via the RM board configuration resource assignment range list. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID is set in @ref tisci_msg_rm_udmap_rx_ch_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID is set in @ref tisci_msg_rm_udmap_rx_ch_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID is set in @ref tisci_msg_rm_udmap_rx_ch_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID is set in @ref tisci_msg_rm_udmap_rx_ch_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID is set in @ref tisci_msg_rm_udmap_rx_ch_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID is set in @ref tisci_msg_rm_udmap_rx_ch_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID is set in @ref tisci_msg_rm_udmap_rx_ch_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID is set in @ref tisci_msg_rm_udmap_rx_ch_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID is set in @ref tisci_msg_rm_udmap_rx_ch_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID is set in @ref tisci_msg_rm_udmap_rx_ch_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID is set in @ref tisci_msg_rm_udmap_rx_ch_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID is set in @ref tisci_msg_rm_udmap_rx_ch_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID is set in @ref tisci_msg_rm_udmap_rx_ch_cfg_req::valid_params.
UDMAP Receive Channel Configuration Valid Parameters¶
The following table describes the valid bit mappings for the UDMAP receive channel configure message optional parameters:
| valid_params Bit | Corresponding tisci_msg_rm_udmap_rx_ch_cfg_req Optional Parameter |
|---|---|
| 0 | rx_pause_on_err |
| 1 | rx_atype |
| 2 | rx_chan_type |
| 3 | rx_fetch_size |
| 4 | rxcq_qnum |
| 5 | rx_priority |
| 6 | rx_qos |
| 7 | rx_orderid |
| 8 | rx_sched_priority |
| 9 | flowid_start |
| 10 | flowid_cnt |
| 11 | rx_ignore_short |
| 12 | rx_ignore_long |
| 14 | rx_burst_size |
UDMAP Receive Channel Configure Response¶
The udmap rx channel cfg response message returns the result status of the processed udmap rx channel cfg message.
UDMAP Receive Channel Configure Response Message Parameters¶
struct tisci_msg_rm_udmap_rx_ch_cfg_resp
Response to configuring a UDMAP receive channel.
| Parameter | Type | Description |
|---|---|---|
| hdr | struct tisci_header | Standard TISCI header |
TISCI_MSG_RM_UDMAP_FLOW_CFG - UDMAP Receive Flow Configure¶
UDMAP Receive Flow Configure Request¶
The UDMAP flow cfg TISCI message API is used to configure a SoC Navigator Subsystem UDMAP receive flow’s standard, non-size threshold registers. The flow index must be assigned to the host defined in the TISCI header via the RM board configuration resource assignment range list.
It’s the user’s responsibility to make sure any receive channels using the flow are disabled when changing the receive flow configuration. Otherwise, unknown operation may occur.
The UDMAP global invalid receive flow event register is not programmed as part of the UDMAP flow cfg API. It is programmed internally via the RM IRQ Set message.
The UDMAP flow cfg API can be used to configure receive flows within any Navigator Subsystem UDMAP on the device.
Usage¶
| Message Type | Normal |
| Secure Queue Only? | No |
TISCI Message ID¶
TISCI_MSG_RM_UDMAP_FLOW_CFG (0x1230U)
RM TISCI message to configure a Navigator Subsystem UDMAP receive flow
UDMAP Receive Flow Configure Message Parameters¶
struct tisci_msg_rm_udmap_flow_cfg_req
Configures a Navigator Subsystem UDMAP receive flow
| Parameter | Type | Description |
|---|---|---|
| hdr | struct tisci_header | Standard TISCI header |
| valid_params | u32 | Bitfield defining validity of rx flow configuration parameters. The rx flow configuration fields are not valid, and will not be used for flow configuration, if their corresponding valid bit is zero. Valid bit usage: 0 - Valid bit for @ref tisci_msg_rm_udmap_flow_cfg_req::rx_einfo_present 1 - Valid bit for @ref tisci_msg_rm_udmap_flow_cfg_req::rx_psinfo_present 2 - Valid bit for @ref tisci_msg_rm_udmap_flow_cfg_req::rx_error_handling 3 - Valid bit for @ref tisci_msg_rm_udmap_flow_cfg_req::rx_desc_type 4 - Valid bit for @ref tisci_msg_rm_udmap_flow_cfg_req::rx_sop_offset 5 - Valid bit for @ref tisci_msg_rm_udmap_flow_cfg_req::rx_dest_qnum 6 - Valid bit for @ref tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi 7 - Valid bit for @ref tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo 8 - Valid bit for @ref tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi 9 - Valid bit for @ref tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo 10 - Valid bit for @ref tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi_sel 11 - Valid bit for @ref tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo_sel 12 - Valid bit for @ref tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel 13 - Valid bit for @ref tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel 14 - Valid bit for @ref tisci_msg_rm_udmap_flow_cfg_req::rx_fdq0_sz0_qnum 15 - Valid bit for @ref tisci_msg_rm_udmap_flow_cfg_req::rx_fdq1_qnum 16 - Valid bit for @ref tisci_msg_rm_udmap_flow_cfg_req::rx_fdq2_qnum 17 - Valid bit for @ref tisci_msg_rm_udmap_flow_cfg_req::rx_fdq3_qnum 18 - Valid bit for @ref tisci_msg_rm_udmap_flow_cfg_req::rx_ps_location |
| nav_id | u16 | SoC device ID of Navigator Subsystem from which the receive flow is allocated |
| flow_index | u16 | UDMAP receive flow index for non-optional configuration. |
| rx_einfo_present | u8 | UDMAP receive flow extended packet info present configuration to be programmed into the rx_einfo_present field of the flow’s RFLOW_RFA register. Can be set to: @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_EINFO_NOT_PRESENT @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_EINFO_PRESENT |
| rx_psinfo_present | u8 | UDMAP receive flow PS words present configuration to be programmed into the rx_psinfo_present field of the flow’s RFLOW_RFA register. Can be set to: @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_PSINFO_NOT_PRESENT @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_PSINFO_PRESENT |
| rx_error_handling | u8 | UDMAP receive flow error handling configuration to be programmed into the rx_error_handling field of the flow’s RFLOW_RFA register. Can be set to: @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_ERR_DROP @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_ERR_RETRY |
| rx_desc_type | u8 | UDMAP receive flow descriptor type configuration to be programmed into the rx_desc_type field field of the flow’s RFLOW_RFA register. Can be set to @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DESC_HOST @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DESC_MONO |
| rx_sop_offset | u16 | UDMAP receive flow start of packet offset configuration to be programmed into the rx_sop_offset field of the RFLOW_RFA register. See the UDMAP section of the TRM for more information on this setting. Valid values for this field are 0-255 bytes. The allocation request will be NACK’d if specified offset is greater than @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SOP_MAX. |
| rx_dest_qnum | u16 | UDMAP receive flow destination queue configuration to be programmed into the rx_dest_qnum field of the flow’s RFLOW_RFA register. The specified destination queue must be valid within the Navigator Subsystem and must be owned by the host, or a subordinate of the host, requesting allocation and configuration of the receive flow. |
| rx_src_tag_hi | u8 | UDMAP receive flow source tag high byte constant configuration to be programmed into the rx_src_tag_hi field of the flow’s RFLOW_RFB register. See the UDMAP section of the TRM for more information on this setting. |
| rx_src_tag_lo | u8 | UDMAP receive flow source tag low byte constant configuration to be programmed into the rx_src_tag_lo field of the flow’s RFLOW_RFB register. See the UDMAP section of the TRM for more information on this setting. |
| rx_dest_tag_hi | u8 | UDMAP receive flow destination tag high byte constant configuration to be programmed into the rx_dest_tag_hi field of the flow’s RFLOW_RFB register. See the UDMAP section of the TRM for more information on this setting. |
| rx_dest_tag_lo | u8 | UDMAP receive flow destination tag low byte constant configuration to be programmed into the rx_dest_tag_lo field of the flow’s RFLOW_RFB register. See the UDMAP section of the TRM for more information on this setting. |
| rx_src_tag_hi_sel | u8 | UDMAP receive flow source tag high byte selector configuration to be programmed into the rx_src_tag_hi_sel field of the RFLOW_RFC register. See the UDMAP section of the TRM for more information on this setting. Can be set to @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SRC_SELECT_NONE @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SRC_SELECT_CFG_TAG @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SRC_SELECT_FLOW_ID @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SRC_SELECT_SRC_TAG |
| rx_src_tag_lo_sel | u8 | UDMAP receive flow source tag low byte selector configuration to be programmed into the rx_src_tag_lo_sel field of the RFLOW_RFC register. See the UDMAP section of the TRM for more information on this setting. Can be set to @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SRC_SELECT_NONE @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SRC_SELECT_CFG_TAG @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SRC_SELECT_FLOW_ID @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SRC_SELECT_SRC_TAG |
| rx_dest_tag_hi_sel | u8 | UDMAP receive flow destination tag high byte selector configuration to be programmed into the rx_dest_tag_hi_sel field of the RFLOW_RFC register. See the UDMAP section of the TRM for more information on this setting. Can be set to @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DEST_SELECT_NONE @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DEST_SELECT_CFG_TAG @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DEST_SELECT_FLOW_ID @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DEST_SELECT_DEST_TAG_LO @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DEST_SELECT_DEST_TAG_HI |
| rx_dest_tag_lo_sel | u8 | UDMAP receive flow destination tag low byte selector configuration to be programmed into the rx_dest_tag_lo_sel field of the RFLOW_RFC register. See the UDMAP section of the TRM for more information on this setting. Can be set to @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DEST_SELECT_NONE @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DEST_SELECT_CFG_TAG @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DEST_SELECT_FLOW_ID @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DEST_SELECT_DEST_TAG_LO @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_DEST_SELECT_DEST_TAG_HI |
| rx_fdq0_sz0_qnum | u16 | UDMAP receive flow free descriptor queue 0 configuration to be programmed into the rx_fdq0_sz0_qnum field of the flow’s RFLOW_RFD register. See the UDMAP section of the TRM for more information on this setting. The specified free queue must be valid within the Navigator Subsystem and must be owned by the host, or a subordinate of the host, requesting allocation and configuration of the receive flow. |
| rx_fdq1_qnum | u16 | UDMAP receive flow free descriptor queue 1 configuration to be programmed into the rx_fdq1_qnum field of the flow’s RFLOW_RFD register. See the UDMAP section of the TRM for more information on this setting. The specified free queue must be valid within the Navigator Subsystem and must be owned by the host, or a subordinate of the host, requesting allocation and configuration of the receive flow. |
| rx_fdq2_qnum | u16 | UDMAP receive flow free descriptor queue 2 configuration to be programmed into the rx_fdq2_qnum field of the flow’s RFLOW_RFE register. See the UDMAP section of the TRM for more information on this setting. The specified free queue must be valid within the Navigator Subsystem and must be owned by the host, or a subordinate of the host, requesting allocation and configuration of the receive flow. |
| rx_fdq3_qnum | u16 | UDMAP receive flow free descriptor queue 3 configuration to be programmed into the rx_fdq3_qnum field of the flow’s RFLOW_RFE register. See the UDMAP section of the TRM for more information on this setting. The specified free queue must be valid within the Navigator Subsystem and must be owned by the host, or a subordinate of the host, requesting allocation and configuration of the receive flow. |
| rx_ps_location | u8 | UDMAP receive flow PS words location configuration to be programmed into the rx_ps_location field of the flow’s RFLOW_RFA register. Can be set to: @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_PS_END_PD @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_PS_BEGIN_DB |
Configures a Navigator Subsystem UDMAP receive flow’s registers. Configuration does not include the flow registers which handle size-based free descriptor queue routing. The @ref tisci_msg_rm_udmap_flow_size_thresh_cfg_req message is used to configure register fields related to size based free descriptor queues. The flow index must be assigned to the host defined in the TISCI header via the RM board configuration resource assignment range list. It’s the user’s responsibility to make sure any receive channels using the flow are disabled when changing the receive flow configuration. Otherwise, unknown operation may occur. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID is set in @ref tisci_msg_rm_udmap_flow_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID is set in @ref tisci_msg_rm_udmap_flow_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID is set in @ref tisci_msg_rm_udmap_flow_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID is set in @ref tisci_msg_rm_udmap_flow_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_SOP_OFFSET_VALID is set in @ref tisci_msg_rm_udmap_flow_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID is set in @ref tisci_msg_rm_udmap_flow_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_VALID is set in @ref tisci_msg_rm_udmap_flow_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_VALID is set in @ref tisci_msg_rm_udmap_flow_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_VALID is set in @ref tisci_msg_rm_udmap_flow_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_VALID is set in @ref tisci_msg_rm_udmap_flow_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID is set in @ref tisci_msg_rm_udmap_flow_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID is set in @ref tisci_msg_rm_udmap_flow_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID is set in @ref tisci_msg_rm_udmap_flow_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID is set in @ref tisci_msg_rm_udmap_flow_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID is set in @ref tisci_msg_rm_udmap_flow_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID is set in @ref tisci_msg_rm_udmap_flow_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID is set in @ref tisci_msg_rm_udmap_flow_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID is set in @ref tisci_msg_rm_udmap_flow_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID is set in @ref tisci_msg_rm_udmap_flow_cfg_req::valid_params.
UDMAP Receive Flow Configure Valid Parameters¶
The following table describes the valid bit mappings for the UDMAP receive flow configure message parameters:
| valid_params Bit | Corresponding tisci_msg_rm_udmap_flow_cfg_req Parameter |
|---|---|
| 0 | rx_einfo_present |
| 1 | rx_psinfo_present |
| 2 | rx_error_handling |
| 3 | rx_desc_type |
| 4 | rx_sop_offset |
| 5 | rx_dest_qnum |
| 6 | rx_src_tag_hi |
| 7 | rx_src_tag_lo |
| 8 | rx_dest_tag_hi |
| 9 | rx_dest_tag_lo |
| 10 | rx_src_tag_hi_sel |
| 11 | rx_src_tag_lo_sel |
| 12 | rx_dest_tag_hi_sel |
| 13 | rx_dest_tag_lo_sel |
| 14 | rx_fdq0_sz0_qnum |
| 15 | rx_fdq1_sz0_qnum |
| 16 | rx_fdq2_sz0_qnum |
| 17 | rx_fdq3_sz0_qnum |
| 18 | rx_ps_location |
UDMAP Receive Flow Configure Response¶
The udmap flow cfg response message returns the result status of the processed udmap flow cfg message.
UDMAP Receive Flow Configure Response Message Parameters¶
struct tisci_msg_rm_udmap_flow_cfg_resp
Response to configuring a Navigator Subsystem UDMAP receive flow
| Parameter | Type | Description |
|---|---|---|
| hdr | struct tisci_header | Standard TISCI header |
TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG - UDMAP Receive Flow Size Threshold Configure¶
UDMAP Receive Flow Size Threshold Configure Request¶
The UDMAP flow size threshold cfg TISCI message API is used to configure the size-based free descriptor queue routing registers for flow. The flow index must be assigned to the host defined in the TISCI header via the RM board configuration resource assignment range list.
It’s the user’s responsibility to make sure any receive channels using the flow are disabled when changing the receive flow configuration. Otherwise, unknown operation may occur.
The UDMAP flow size threshold cfg API can be used to configure receive flows within any Navigator Subsystem UDMAP on the device.
Usage¶
| Message Type | Normal |
| Secure Queue Only? | No |
TISCI Message ID¶
TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG (0x1231U)
RM TISCI message to configure a Navigator Subsystem UDMAP receive flow’s optional, size based free descriptor queue registers
UDMAP Receive Flow Size Threshold Configure Message Parameters¶
struct tisci_msg_rm_udmap_flow_size_thresh_cfg_req
Configures a Navigator Subsystem UDMAP receive flow’s size threshold fields.
| Parameter | Type | Description |
|---|---|---|
| hdr | struct tisci_header | Standard TISCI header |
| valid_params | u32 | Bitfield defining validity of rx flow configuration parameters. The rx flow configuration fields are not valid, and will not be used for flow configuration, if their corresponding valid bit is zero. Valid bit usage: 0 - Valid bit for @ref tisci_msg_rm_udmap_flow_size_thresh_cfg_req::rx_size_thresh0 1 - Valid bit for @ref tisci_msg_rm_udmap_flow_size_thresh_cfg_req::rx_size_thresh1 2 - Valid bit for @ref tisci_msg_rm_udmap_flow_size_thresh_cfg_req::rx_size_thresh2 3 - Valid bit for @ref tisci_msg_rm_udmap_flow_size_thresh_cfg_req::rx_fdq0_sz1_qnum 4 - Valid bit for @ref tisci_msg_rm_udmap_flow_size_thresh_cfg_req::rx_fdq0_sz2_qnum 5 - Valid bit for @ref tisci_msg_rm_udmap_flow_size_thresh_cfg_req::rx_fdq0_sz3_qnum 6 - Valid bit for @ref tisci_msg_rm_udmap_flow_size_thresh_cfg_req::rx_size_thresh_en |
| nav_id | u16 | SoC device ID of Navigator Subsystem from which the receive flow is allocated |
| flow_index | u16 | UDMAP receive flow index for optional configuration. |
| rx_size_thresh0 | u16 | UDMAP receive flow packet size threshold 0 configuration to be programmed into the rx_size_thresh0 field of the flow’s RFLOW_RFF register. The value must be provided in 32-byte units due to a 5-bit left shift performed by the hardware prior to comparison to packet size. See the UDMAP section of the TRM for more information on this setting and the shift on comparison. |
| rx_size_thresh1 | u16 | UDMAP receive flow packet size threshold 1 configuration to be programmed into the rx_size_thresh1 field of the flow’s RFLOW_RFF register. The value must be provided in 32-byte units due to a 5-bit left shift performed by the hardware prior to comparison to packet size. See the UDMAP section of the TRM for more information on this setting and the shift on comparison. |
| rx_size_thresh2 | u16 | UDMAP receive flow packet size threshold 2 configuration to be programmed into the rx_size_thresh2 field of the flow’s RFLOW_RFG register. The value must be provided in 32-byte units due to a 5-bit left shift performed by the hardware prior to comparison to packet size. See the UDMAP section of the TRM for more information on this setting and the shift on comparison. |
| rx_fdq0_sz1_qnum | u16 | UDMAP receive flow free descriptor queue for size threshold 1 configuration to be programmed into the rx_fdq0_sz1_qnum field of the flow’s RFLOW_RFG register. See the UDMAP section of the TRM for more information on this setting. The specified free queue must be valid within the Navigator Subsystem and must be owned by the host, or a subordinate of the host, who owns the receive flow index and who is making the optional configuration request. |
| rx_fdq0_sz2_qnum | u16 | UDMAP receive flow free descriptor queue for size threshold 2 configuration to be programmed into the rx_fdq0_sz2_qnum field of the flow’s RFLOW_RFH register. See the UDMAP section of the TRM for more information on this setting. The specified free queue must be valid within the Navigator Subsystem and must be owned by the host, or a subordinate of the host, who owns the receive flow index and who is making the optional configuration request. |
| rx_fdq0_sz3_qnum | u16 | UDMAP receive flow free descriptor queue for size threshold 3 configuration to be programmed into the rx_fdq0_sz3_qnum field of the flow’s RFLOW_RFH register. See the UDMAP section of the TRM for more information on this setting. The specified free queue must be valid within the Navigator Subsystem and must be owned by the host, or a subordinate of the host, who owns the receive flow index and who is making the optional configuration request. |
| rx_size_thresh_en | u8 | UDMAP receive flow packet size based free buffer queue enable configuration to be programmed into the rx_size_thresh_en field of the RFLOW_RFC register. See the UDMAP section of the TRM for more information on this setting. This parameter can be no greater than @ref TISCI_MSG_VALUE_RM_UDMAP_RX_FLOW_SIZE_THRESH_MAX |
Configures a Navigator Subsystem UDMAP receive flow’s size threshold fields The flow index must be assigned to the host defined in the TISCI header via the RM board configuration resource assignment range list. It’s the user’s responsibility to make sure any receive channels using the flow are disabled when changing the receive flow configuration. Otherwise, unknown operation may occur. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_SIZE_THRESH0_VALID is set in @ref tisci_msg_rm_udmap_flow_size_thresh_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_SIZE_THRESH1_VALID is set in @ref tisci_msg_rm_udmap_flow_size_thresh_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_SIZE_THRESH2_VALID is set in @ref tisci_msg_rm_udmap_flow_size_thresh_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ1_QNUM_VALID is set in @ref tisci_msg_rm_udmap_flow_size_thresh_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ2_QNUM_VALID is set in @ref tisci_msg_rm_udmap_flow_size_thresh_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ3_QNUM_VALID is set in @ref tisci_msg_rm_udmap_flow_size_thresh_cfg_req::valid_params. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_SIZE_THRESH_EN_VALID is set in @ref tisci_msg_rm_udmap_flow_size_thresh_cfg_req::valid_params.
UDMAP Receive Flow Size Threshold Configure Valid Parameters¶
The following table describes the valid bit mappings for the UDMAP receive flow size threshold configure message parameters:
| valid_params Bit | Corresponding tisci_msg_rm_udmap_flow_size_thresh_cfg_req Parameter |
|---|---|
| 0 | rx_size_thresh0 |
| 1 | rx_size_thresh1 |
| 2 | rx_size_thresh2 |
| 3 | rx_fdq0_sz1_qnum |
| 4 | rx_fdq0_sz2_qnum |
| 5 | rx_fdq0_sz3_qnum |
| 6 | rx_size_thresh_en |
UDMAP Receive Flow Size Threshold Configure Response¶
The udmap flow size threshold cfg response message returns the result status of the processed udmap flow size threshold cfg message.
UDMAP Receive Flow Size Threshold Configure Response Message Parameters¶
struct tisci_msg_rm_udmap_flow_size_thresh_cfg_resp
Response to configuring a Navigator Subsystem UDMAP receive flow’s size threshold fields.
| Parameter | Type | Description |
|---|---|---|
| hdr | struct tisci_header | Standard TISCI header |
TISCI_MSG_RM_UDMAP_FLOW_DELEGATE - UDMAP Flow Delegate¶
UDMAP Flow Delegate Request¶
The UDMAP flow delegate TISCI message API is used by a host to delegate configuration of an owned, according to the RM board configuration, common DMA flow to another host. After delegation the host owning the flow and the delegated host are allowed to configure the flow via the flow configuration TISCI messages. The delegation can be cleared by the host who owns the flow by setting the clear parameter of the flow delegate message.
The flow index set for delegation must be assigned to the host defined in the TISCI header via the RM board configuration resource assignment range list.
Usage¶
| Message Type | Normal |
| Secure Queue Only? | No |
TISCI Message ID¶
TISCI_MSG_RM_UDMAP_FLOW_DELEGATE (0x1234U)
RM TISCI message to delegate a DMA flow to another host for configuration
UDMAP Flow Delegate Message Parameters¶
struct tisci_msg_rm_udmap_flow_delegate_req
Delegates the specified flow to another host for configuration. Only the original owner of the flow, as specified in the RM board configuration resource entries, can delegate an additional host as able to configure the flow. A flow’s delegation can be cleared by the original owner of the flow using the clear parameter.
| Parameter | Type | Description |
|---|---|---|
| hdr | struct tisci_header | Standard TISCI header |
| valid_params | u32 | Bitfield defining validity of flow delegation parameters. The flow delegation fields are not valid, and will not be used, if their corresponding valid bit is zero. Valid bit usage: 0 - Valid bit for @ref tisci_msg_rm_udmap_flow_delegate_req::delegated_host 1 - Valid bit for @ref tisci_msg_rm_udmap_flow_delegate_req::clear |
| dev_id | u16 | SoC device ID of DMA in which the common flow exists. |
| flow_index | u16 | DMA common flow being delegated for configuration. |
| delegated_host | u8 | The host delegated configuration access to the flow. The host must be a valid host within the SoC. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_DELEGATE_HOST_VALID is set in @ref tisci_msg_rm_udmap_flow_delegate_req::valid_params. |
| clear | u8 | Clears the flow delegation when enabled. Set this parameter to @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_DELEGATE_CLEAR. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_FLOW_DELEGATE_CLEAR_VALID is set in @ref tisci_msg_rm_udmap_flow_delegate_req::valid_params. |
UDMAP Flow Delegate Valid Parameters¶
The following table describes the valid bit mappings for the UDMAP flow delegate message parameters:
| valid_params Bit | Corresponding tisci_msg_rm_udmap_flow_delegate_req Parameter |
|---|---|
| 0 | delegated_host |
| 1 | clear |
UDMAP Flow Delegate Response¶
The udmap flow delegate response message returns the result status of the processed udmap flow delegate message.
UDMAP Flow Delegate Response Message Parameters¶
struct tisci_msg_rm_udmap_flow_delegate_resp
Response to delegating a flow to another host for configuration.
| Parameter | Type | Description |
|---|---|---|
| hdr | struct tisci_header | Standard TISCI header |
TISCI_MSG_RM_UDMAP_GCFG_CFG - UDMAP Global Configuration Configure¶
UDMAP Global Configuration Configure Request¶
The udmap_gcfg_cfg TISCI message API is used to configure non-real-time registers in the UDMAP subsystem’s global configuration region. The host, or a supervisor of the host, who owns the global configuration region must be the requesting host. The API allows configuration of the global configuration region by passing the Navigator SoC device ID of the UDMAP subsystem in which the region is located.
Usage¶
| Message Type | Normal |
| Secure Queue Only? | No |
TISCI Message ID¶
TISCI_MSG_RM_UDMAP_GCFG_CFG (0x1240U)
RM TISCI message to configure a Navigator Subsystem UDMAP global configuration
UDMAP Global Configuration Configure Message Parameters¶
struct tisci_msg_rm_udmap_gcfg_cfg_req
Configures a Navigator Subsystem UDMAP global configuration region. Configures the non-real-time registers of a Navigator Subsystem UDMAP global configuration region. The GCFG region being programmed must be assigned to the host defined in the TISCI header via the RM board configuration resource assignment array. Individual fields for registers specified as valid are not checked for correctness. It is the application’s responsibility to verify if the register fields are being set according to the device specification.
| Parameter | Type | Description |
|---|---|---|
| hdr | struct tisci_header | Standard TISCI header |
| valid_params | u32 | Bitfield defining validity of global configuration parameters. The configuration fields are not valid, and will not be used for global configuration, if their corresponding valid bit is zero. Valid bit usage: 0 - Valid bit for @ref tisci_msg_rm_udmap_gcfg_cfg_req::perf_ctrl 1 - Valid bit for @ref tisci_msg_rm_udmap_gcfg_cfg_req::emu_ctrl 2 - Valid bit for @ref tisci_msg_rm_udmap_gcfg_cfg_req::psil_to 3 - Valid bit for @ref tisci_msg_rm_udmap_gcfg_cfg_req::rflowfwstat |
| nav_id | u16 | SoC device ID of Navigator Subsystem where global configuration is located |
| perf_ctrl | u32 | Configures the performance control register. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_GCFG_PERF_CTRL_VALID is set in @ref tisci_msg_rm_udmap_gcfg_cfg_req::valid_params. |
| emu_ctrl | u32 | Configures the emulation control register. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_GCFG_EMU_CTRL_VALID is set in @ref tisci_msg_rm_udmap_gcfg_cfg_req::valid_params. |
| psil_to | u32 | Configures the PSI-L proxy timeout register. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_GCFG_PSIL_TO_VALID is set in @ref tisci_msg_rm_udmap_gcfg_cfg_req::valid_params. |
| rflowfwstat | u32 | Writes the rx flow ID firewall status register. This field is only valid if @ref TISCI_MSG_VALUE_RM_UDMAP_GCFG_RFLOWFWSTAT_VALID is set in @ref tisci_msg_rm_udmap_gcfg_cfg_req::valid_params. |
UDMAP Global Configuration Configure Valid Parameters¶
The following table describes the valid bit mappings for the UDMAP global configuration configure parameters:
| valid_params Bit | Corresponding tisci_msg_rm_udmap_gcfg_cfg_req Parameter |
|---|---|
| 0 | perf_ctrl_timeout_cnt |
| 1 | emu_ctrl_soft |
| 2 | emu_ctrl_free |
| 3 | psil_to_tout |
| 4 | psil_to_tout_cnt |
| 5 | utc_chan_start |
| 6 | rflowfwstat_pend |
UDMAP Global Configuration Configure Response¶
The udmap_gcfg_cfg_response message returns the result status of the processed udmap_gcfg_cfg message.
UDMAP Global Configuration Configure Response Message Parameters¶
struct tisci_msg_rm_udmap_gcfg_cfg_resp
Response to configuring UDMAP global configuration.
| Parameter | Type | Description |
|---|---|---|
| hdr | struct tisci_header | Standard TISCI header |