AM64X Clock Identifiers

Clock for AM64X Device

This chapter provides information on clock IDs that identify clocks incoming and outgoing from devices identified via device IDs in AM64X SoC.

TISCI message Power Management APIs define a device ID and clock ID as parameters allowing a user to specify granular control of clocks for a particular SoC subsystem.

Device wise clock ID list for AM64X SoC

This is an enumerated list of clocks per device ID that can be controlled via the power management clock APIs

The following table describes functions implemented by clocks

Function Description
Input clock Clock input to the SoC subsystem
Output clock Clock output from the SoC subsystem
Input muxed clock Clock input to the SoC subsystem, but can choose one of the parent clocks as a clock source
Parent input clock option to XYZ One of the parent clocks that can be used as a source clock to a input muxed clock

Also note: There are devices which do not have clock information. These do have chapters in this document associated with them, however, these would be marked as:

This device has no defined clocks.

The chapters corresponding to the devices are organized alphabetically per device name for ease of readability.

Clocks for A53SS0 Device

Device: AM64X_DEV_A53SS0 (ID = 137)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_A53SS0_COREPAC_ARM_CLK_CLK Input clock
1 DEV_A53SS0_PLL_CTRL_CLK Input clock
2 DEV_A53SS0_A53_DIVH_CLK4_OBSCLK_OUT_CLK Output clock

Clocks for A53SS0_CORE_0 Device

Device: AM64X_DEV_A53SS0_CORE_0 (ID = 135)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_A53SS0_CORE_0_A53_CORE0_ARM_CLK_CLK Input clock

Clocks for A53SS0_CORE_1 Device

Device: AM64X_DEV_A53SS0_CORE_1 (ID = 136)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_A53SS0_CORE_1_A53_CORE1_ARM_CLK_CLK Input clock

Clocks for ADC0 Device

Device: AM64X_DEV_ADC0 (ID = 0)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_ADC0_ADC_CLK Input muxed clock
1 DEV_ADC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_ADC0_ADC_CLK
2 DEV_ADC0_ADC_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK Parent input clock option to DEV_ADC0_ADC_CLK
3 DEV_ADC0_ADC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK Parent input clock option to DEV_ADC0_ADC_CLK
4 DEV_ADC0_ADC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_ADC0_ADC_CLK
5 DEV_ADC0_SYS_CLK Input clock
6 DEV_ADC0_VBUS_CLK Input clock

Clocks for BOARD0 Device

Device: AM64X_DEV_BOARD0 (ID = 157)

Note

BOARD0 is a special device that represents the board on which the SoC is mounted.

Clocks that are incoming to or outgoing from the SoC are represented in this section from the perspective of the board.

Function documented here implies:

Function Description
Input clock Clock is supplied from SoC to the board (It is an output of the SoC)
Output clock Clock is supplied from board to the SoC (It is an output of the Board and input to the SoC)

NOTE: Clocks which can be bi-directional are listed as Output clock

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_BOARD0_FSI_TX0_CLK_IN Input clock
1 DEV_BOARD0_FSI_TX1_CLK_IN Input clock
2 DEV_BOARD0_GPMC0_CLKLB_IN Input clock
3 DEV_BOARD0_GPMC0_CLK_IN Input clock
4 DEV_BOARD0_GPMC0_FCLK_MUX_IN Input muxed clock
5 DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK Parent input clock option to DEV_BOARD0_GPMC0_FCLK_MUX_IN
6 DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK Parent input clock option to DEV_BOARD0_GPMC0_FCLK_MUX_IN
7 DEV_BOARD0_I2C0_SCL_IN Input clock
8 DEV_BOARD0_I2C1_SCL_IN Input clock
9 DEV_BOARD0_I2C2_SCL_IN Input clock
10 DEV_BOARD0_I2C3_SCL_IN Input clock
11 DEV_BOARD0_MCU_I2C0_SCL_IN Input clock
12 DEV_BOARD0_MCU_I2C1_SCL_IN Input clock
13 DEV_BOARD0_MCU_OBSCLK0_IN Input muxed clock
14 DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0 Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN
15 DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN
16 DEV_BOARD0_MCU_SPI0_CLK_IN Input clock
17 DEV_BOARD0_MCU_SPI1_CLK_IN Input clock
18 DEV_BOARD0_MCU_SYSCLKOUT0_IN Input clock
19 DEV_BOARD0_MCU_TIMER_IO0_IN Input clock
20 DEV_BOARD0_MCU_TIMER_IO1_IN Input clock
21 DEV_BOARD0_MCU_TIMER_IO2_IN Input clock
22 DEV_BOARD0_MCU_TIMER_IO3_IN Input clock
23 DEV_BOARD0_MMC1_CLK_IN Input clock
24 DEV_BOARD0_OBSCLK0_IN Input clock
25 DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK Parent input clock option to DEV_BOARD0_OBSCLK0_IN
26 DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK Parent input clock option to DEV_BOARD0_OBSCLK0_IN
27 DEV_BOARD0_OBSCLK0_IN_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_BOARD0_OBSCLK0_IN
28 DEV_BOARD0_OBSCLK0_IN_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_BOARD0_OBSCLK0_IN
29 DEV_BOARD0_OBSCLK0_IN_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_BOARD0_OBSCLK0_IN
30 DEV_BOARD0_OBSCLK0_IN_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2 Parent input clock option to DEV_BOARD0_OBSCLK0_IN
31 DEV_BOARD0_OBSCLK0_IN_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3 Parent input clock option to DEV_BOARD0_OBSCLK0_IN
32 DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK Parent input clock option to DEV_BOARD0_OBSCLK0_IN
33 DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK Parent input clock option to DEV_BOARD0_OBSCLK0_IN
34 DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_8_HSDIVOUT0_CLK Parent input clock option to DEV_BOARD0_OBSCLK0_IN
35 DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK Parent input clock option to DEV_BOARD0_OBSCLK0_IN
36 DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_BOARD0_OBSCLK0_IN
37 DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8 Parent input clock option to DEV_BOARD0_OBSCLK0_IN
38 DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0 Parent input clock option to DEV_BOARD0_OBSCLK0_IN
39 DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_BOARD0_OBSCLK0_IN
40 DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 Parent input clock option to DEV_BOARD0_OBSCLK0_IN
41 DEV_BOARD0_OSPI0_LBCLKO_IN Input clock
42 DEV_BOARD0_PRG0_MDIO0_MDC_IN Input clock
43 DEV_BOARD0_PRG0_RGMII1_TXC_IN Input clock
44 DEV_BOARD0_PRG0_RGMII2_TXC_IN Input clock
45 DEV_BOARD0_PRG1_MDIO0_MDC_IN Input clock
46 DEV_BOARD0_PRG1_RGMII1_TXC_IN Input clock
47 DEV_BOARD0_PRG1_RGMII2_TXC_IN Input clock
48 DEV_BOARD0_RGMII1_TXC_IN Input clock
49 DEV_BOARD0_RGMII2_TXC_IN Input clock
50 DEV_BOARD0_SPI0_CLK_IN Input clock
51 DEV_BOARD0_SPI1_CLK_IN Input clock
52 DEV_BOARD0_SPI2_CLK_IN Input clock
53 DEV_BOARD0_SPI3_CLK_IN Input clock
54 DEV_BOARD0_SPI4_CLK_IN Input clock
55 DEV_BOARD0_SYSCLKOUT0_IN Input clock
56 DEV_BOARD0_TIMER_IO0_IN Input clock
57 DEV_BOARD0_TIMER_IO10_IN Input clock
58 DEV_BOARD0_TIMER_IO11_IN Input clock
59 DEV_BOARD0_TIMER_IO1_IN Input clock
60 DEV_BOARD0_TIMER_IO2_IN Input clock
61 DEV_BOARD0_TIMER_IO3_IN Input clock
62 DEV_BOARD0_TIMER_IO4_IN Input clock
63 DEV_BOARD0_TIMER_IO5_IN Input clock
64 DEV_BOARD0_TIMER_IO6_IN Input clock
65 DEV_BOARD0_TIMER_IO7_IN Input clock
66 DEV_BOARD0_TIMER_IO8_IN Input clock
67 DEV_BOARD0_TIMER_IO9_IN Input clock
68 DEV_BOARD0_CPTS0_RFT_CLK_OUT Output clock
69 DEV_BOARD0_CP_GEMAC_CPTS0_RFT_CLK_OUT Output clock
70 DEV_BOARD0_EXT_REFCLK1_OUT Output clock
71 DEV_BOARD0_FSI_RX0_CLK_OUT Output clock
72 DEV_BOARD0_FSI_RX1_CLK_OUT Output clock
73 DEV_BOARD0_FSI_RX2_CLK_OUT Output clock
74 DEV_BOARD0_FSI_RX3_CLK_OUT Output clock
75 DEV_BOARD0_FSI_RX4_CLK_OUT Output clock
76 DEV_BOARD0_FSI_RX5_CLK_OUT Output clock
77 DEV_BOARD0_GPMC0_CLKLB_OUT Output clock
78 DEV_BOARD0_I2C0_SCL_OUT Output clock
79 DEV_BOARD0_I2C1_SCL_OUT Output clock
80 DEV_BOARD0_I2C2_SCL_OUT Output clock
81 DEV_BOARD0_I2C3_SCL_OUT Output clock
82 DEV_BOARD0_LED_CLK_OUT Output clock
83 DEV_BOARD0_MCU_EXT_REFCLK0_OUT Output clock
84 DEV_BOARD0_MCU_I2C0_SCL_OUT Output clock
85 DEV_BOARD0_MCU_I2C1_SCL_OUT Output clock
86 DEV_BOARD0_MCU_SPI0_CLK_OUT Output clock
87 DEV_BOARD0_MCU_SPI1_CLK_OUT Output clock
88 DEV_BOARD0_MMC1_CLKLB_OUT Output clock
89 DEV_BOARD0_OSPI0_DQS_OUT Output clock
90 DEV_BOARD0_OSPI0_LBCLKO_OUT Output clock
91 DEV_BOARD0_PRG0_RGMII1_RXC_OUT Output clock
92 DEV_BOARD0_PRG0_RGMII1_TXC_OUT Output clock
93 DEV_BOARD0_PRG0_RGMII2_RXC_OUT Output clock
94 DEV_BOARD0_PRG0_RGMII2_TXC_OUT Output clock
95 DEV_BOARD0_PRG1_RGMII1_RXC_OUT Output clock
96 DEV_BOARD0_PRG1_RGMII1_TXC_OUT Output clock
97 DEV_BOARD0_PRG1_RGMII2_RXC_OUT Output clock
98 DEV_BOARD0_PRG1_RGMII2_TXC_OUT Output clock
99 DEV_BOARD0_RGMII1_RXC_OUT Output clock
100 DEV_BOARD0_RGMII1_TXC_OUT Output clock
101 DEV_BOARD0_RGMII2_RXC_OUT Output clock
102 DEV_BOARD0_RGMII2_TXC_OUT Output clock
103 DEV_BOARD0_RMII_REF_CLK_OUT Output clock
104 DEV_BOARD0_SPI0_CLK_OUT Output clock
105 DEV_BOARD0_SPI1_CLK_OUT Output clock
106 DEV_BOARD0_SPI2_CLK_OUT Output clock
107 DEV_BOARD0_SPI3_CLK_OUT Output clock
108 DEV_BOARD0_SPI4_CLK_OUT Output clock
109 DEV_BOARD0_TCK_OUT Output clock

Clocks for CMP_EVENT_INTROUTER0 Device

Device: AM64X_DEV_CMP_EVENT_INTROUTER0 (ID = 1)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_CMP_EVENT_INTROUTER0_INTR_CLK Input clock

Clocks for COMPUTE_CLUSTER0 Device

This device has no defined clocks.

Clocks for COMPUTE_CLUSTER0_PBIST_0 Device

This device has no defined clocks.

Clocks for CPSW0 Device

Device: AM64X_DEV_CPSW0 (ID = 13)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_CPSW0_CPPI_CLK_CLK Input clock
1 DEV_CPSW0_CPTS_RFT_CLK Input muxed clock
2 DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK
3 DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK
4 DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK
5 DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK
6 DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK
7 DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK
8 DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK
9 DEV_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK
10 DEV_CPSW0_GMII1_MR_CLK Input clock
11 DEV_CPSW0_GMII1_MT_CLK Input clock
12 DEV_CPSW0_GMII2_MR_CLK Input clock
13 DEV_CPSW0_GMII2_MT_CLK Input clock
14 DEV_CPSW0_GMII_RFT_CLK Input clock
15 DEV_CPSW0_RGMII1_RXC_I Input clock
16 DEV_CPSW0_RGMII1_TXC_I Input clock
17 DEV_CPSW0_RGMII2_RXC_I Input clock
18 DEV_CPSW0_RGMII2_TXC_I Input clock
19 DEV_CPSW0_RGMII_MHZ_250_CLK Input clock
20 DEV_CPSW0_RGMII_MHZ_50_CLK Input clock
21 DEV_CPSW0_RGMII_MHZ_5_CLK Input clock
22 DEV_CPSW0_RMII_MHZ_50_CLK Input clock
23 DEV_CPSW0_CPTS_GENF0 Output clock
24 DEV_CPSW0_CPTS_GENF1 Output clock
25 DEV_CPSW0_RGMII1_TXC_O Output clock
26 DEV_CPSW0_RGMII2_TXC_O Output clock

Clocks for CPT2_AGGR0 Device

Device: AM64X_DEV_CPT2_AGGR0 (ID = 14)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_CPT2_AGGR0_VCLK_CLK Input clock

Clocks for CPTS0 Device

Device: AM64X_DEV_CPTS0 (ID = 84)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_CPTS0_CPTS_RFT_CLK Input muxed clock
1 DEV_CPTS0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK
2 DEV_CPTS0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK
3 DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK
4 DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK
5 DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK
6 DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK
7 DEV_CPTS0_CPTS_RFT_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK
8 DEV_CPTS0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK Parent input clock option to DEV_CPTS0_CPTS_RFT_CLK
9 DEV_CPTS0_VBUSP_CLK Input clock
10 DEV_CPTS0_CPTS_GENF1 Output clock
11 DEV_CPTS0_CPTS_GENF2 Output clock
12 DEV_CPTS0_CPTS_GENF3 Output clock
13 DEV_CPTS0_CPTS_GENF4 Output clock

Clocks for DBGSUSPENDROUTER0 Device

Device: AM64X_DEV_DBGSUSPENDROUTER0 (ID = 2)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DBGSUSPENDROUTER0_INTR_CLK Input clock

Clocks for DCC0 Device

Device: AM64X_DEV_DCC0 (ID = 16)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DCC0_DCC_CLKSRC0_CLK Input clock
1 DEV_DCC0_DCC_CLKSRC1_CLK Input clock
2 DEV_DCC0_DCC_CLKSRC2_CLK Input clock
3 DEV_DCC0_DCC_CLKSRC3_CLK Input clock
4 DEV_DCC0_DCC_CLKSRC4_CLK Input clock
5 DEV_DCC0_DCC_CLKSRC5_CLK Input clock
6 DEV_DCC0_DCC_CLKSRC6_CLK Input clock
7 DEV_DCC0_DCC_CLKSRC7_CLK Input clock
8 DEV_DCC0_DCC_INPUT00_CLK Input clock
9 DEV_DCC0_DCC_INPUT01_CLK Input clock
10 DEV_DCC0_DCC_INPUT02_CLK Input clock
11 DEV_DCC0_DCC_INPUT10_CLK Input clock
12 DEV_DCC0_VBUS_CLK Input clock

Clocks for DCC1 Device

Device: AM64X_DEV_DCC1 (ID = 17)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DCC1_DCC_CLKSRC0_CLK Input clock
1 DEV_DCC1_DCC_CLKSRC1_CLK Input clock
2 DEV_DCC1_DCC_CLKSRC2_CLK Input clock
3 DEV_DCC1_DCC_CLKSRC3_CLK Input clock
4 DEV_DCC1_DCC_CLKSRC4_CLK Input clock
5 DEV_DCC1_DCC_CLKSRC5_CLK Input clock
6 DEV_DCC1_DCC_CLKSRC6_CLK Input clock
7 DEV_DCC1_DCC_CLKSRC7_CLK Input clock
8 DEV_DCC1_DCC_INPUT00_CLK Input clock
9 DEV_DCC1_DCC_INPUT01_CLK Input clock
10 DEV_DCC1_DCC_INPUT02_CLK Input clock
11 DEV_DCC1_DCC_INPUT10_CLK Input clock
12 DEV_DCC1_VBUS_CLK Input clock

Clocks for DCC2 Device

Device: AM64X_DEV_DCC2 (ID = 18)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DCC2_DCC_CLKSRC0_CLK Input clock
1 DEV_DCC2_DCC_CLKSRC1_CLK Input clock
2 DEV_DCC2_DCC_CLKSRC2_CLK Input clock
3 DEV_DCC2_DCC_CLKSRC3_CLK Input clock
4 DEV_DCC2_DCC_CLKSRC4_CLK Input clock
5 DEV_DCC2_DCC_CLKSRC5_CLK Input clock
6 DEV_DCC2_DCC_CLKSRC6_CLK Input clock
7 DEV_DCC2_DCC_CLKSRC7_CLK Input clock
8 DEV_DCC2_DCC_INPUT00_CLK Input clock
9 DEV_DCC2_DCC_INPUT01_CLK Input clock
10 DEV_DCC2_DCC_INPUT02_CLK Input clock
11 DEV_DCC2_DCC_INPUT10_CLK Input clock
12 DEV_DCC2_VBUS_CLK Input clock

Clocks for DCC3 Device

Device: AM64X_DEV_DCC3 (ID = 19)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DCC3_DCC_CLKSRC0_CLK Input clock
1 DEV_DCC3_DCC_CLKSRC1_CLK Input clock
2 DEV_DCC3_DCC_CLKSRC2_CLK Input clock
3 DEV_DCC3_DCC_CLKSRC3_CLK Input clock
4 DEV_DCC3_DCC_CLKSRC4_CLK Input clock
5 DEV_DCC3_DCC_CLKSRC5_CLK Input clock
6 DEV_DCC3_DCC_CLKSRC6_CLK Input clock
7 DEV_DCC3_DCC_CLKSRC7_CLK Input clock
8 DEV_DCC3_DCC_INPUT00_CLK Input clock
9 DEV_DCC3_DCC_INPUT01_CLK Input clock
10 DEV_DCC3_DCC_INPUT02_CLK Input clock
11 DEV_DCC3_DCC_INPUT10_CLK Input clock
12 DEV_DCC3_VBUS_CLK Input clock

Clocks for DCC4 Device

Device: AM64X_DEV_DCC4 (ID = 20)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DCC4_DCC_CLKSRC0_CLK Input muxed clock
1 DEV_DCC4_DCC_CLKSRC0_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK Parent input clock option to DEV_DCC4_DCC_CLKSRC0_CLK
2 DEV_DCC4_DCC_CLKSRC0_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK Parent input clock option to DEV_DCC4_DCC_CLKSRC0_CLK
3 DEV_DCC4_DCC_CLKSRC1_CLK Input clock
4 DEV_DCC4_DCC_CLKSRC2_CLK Input clock
5 DEV_DCC4_DCC_CLKSRC3_CLK Input clock
6 DEV_DCC4_DCC_CLKSRC4_CLK Input clock
7 DEV_DCC4_DCC_CLKSRC5_CLK Input clock
8 DEV_DCC4_DCC_CLKSRC6_CLK Input clock
9 DEV_DCC4_DCC_CLKSRC7_CLK Input clock
10 DEV_DCC4_DCC_INPUT00_CLK Input clock
11 DEV_DCC4_DCC_INPUT01_CLK Input clock
12 DEV_DCC4_DCC_INPUT02_CLK Input clock
13 DEV_DCC4_DCC_INPUT10_CLK Input clock
14 DEV_DCC4_VBUS_CLK Input clock

Clocks for DCC5 Device

Device: AM64X_DEV_DCC5 (ID = 21)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DCC5_DCC_CLKSRC0_CLK Input clock
1 DEV_DCC5_DCC_CLKSRC1_CLK Input clock
2 DEV_DCC5_DCC_CLKSRC2_CLK Input clock
3 DEV_DCC5_DCC_CLKSRC3_CLK Input clock
4 DEV_DCC5_DCC_CLKSRC4_CLK Input clock
5 DEV_DCC5_DCC_CLKSRC5_CLK Input clock
6 DEV_DCC5_DCC_CLKSRC6_CLK Input clock
7 DEV_DCC5_DCC_CLKSRC7_CLK Input clock
8 DEV_DCC5_DCC_INPUT00_CLK Input clock
9 DEV_DCC5_DCC_INPUT01_CLK Input clock
10 DEV_DCC5_DCC_INPUT02_CLK Input clock
11 DEV_DCC5_DCC_INPUT10_CLK Input clock
12 DEV_DCC5_VBUS_CLK Input clock

Clocks for DDPA0 Device

Device: AM64X_DEV_DDPA0 (ID = 85)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DDPA0_DDPA_CLK Input clock

Clocks for DDR16SS0 Device

Device: AM64X_DEV_DDR16SS0 (ID = 138)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DDR16SS0_DDRSS_DDR_PLL_CLK Input clock
1 DEV_DDR16SS0_PLL_CTRL_CLK Input clock

Clocks for DEBUGSS_WRAP0 Device

Device: AM64X_DEV_DEBUGSS_WRAP0 (ID = 24)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DEBUGSS_WRAP0_ATB_CLK Input clock
1 DEV_DEBUGSS_WRAP0_CORE_CLK Input clock
2 DEV_DEBUGSS_WRAP0_JTAG_TCK Input clock
3 DEV_DEBUGSS_WRAP0_TREXPT_CLK Input clock

Clocks for DMASS0 Device

This device has no defined clocks.

Clocks for DMASS0_BCDMA_0 Device

Device: AM64X_DEV_DMASS0_BCDMA_0 (ID = 26)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DMASS0_BCDMA_0_CLK Input clock

Clocks for DMASS0_CBASS_0 Device

Device: AM64X_DEV_DMASS0_CBASS_0 (ID = 27)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DMASS0_CBASS_0_CLK Input clock

Clocks for DMASS0_INTAGGR_0 Device

Device: AM64X_DEV_DMASS0_INTAGGR_0 (ID = 28)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DMASS0_INTAGGR_0_CLK Input clock

Clocks for DMASS0_IPCSS_0 Device

Device: AM64X_DEV_DMASS0_IPCSS_0 (ID = 29)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DMASS0_IPCSS_0_CLK Input clock

Clocks for DMASS0_PKTDMA_0 Device

Device: AM64X_DEV_DMASS0_PKTDMA_0 (ID = 30)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DMASS0_PKTDMA_0_CLK Input clock

Clocks for DMASS0_PSILCFG_0 Device

Device: AM64X_DEV_DMASS0_PSILCFG_0 (ID = 31)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DMASS0_PSILCFG_0_CLK Input clock

Clocks for DMASS0_PSILSS_0 Device

Device: AM64X_DEV_DMASS0_PSILSS_0 (ID = 32)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DMASS0_PSILSS_0_PDMA_MAIN0_CLK Input clock
1 DEV_DMASS0_PSILSS_0_PDMA_MAIN1_CLK Input clock
2 DEV_DMASS0_PSILSS_0_VD2CLK Input clock

Clocks for DMASS0_RINGACC_0 Device

Device: AM64X_DEV_DMASS0_RINGACC_0 (ID = 33)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_DMASS0_RINGACC_0_CLK Input clock

Clocks for DMSC0 Device

This device has no defined clocks.

Clocks for ECAP0 Device

Device: AM64X_DEV_ECAP0 (ID = 51)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_ECAP0_VBUS_CLK Input clock

Clocks for ECAP1 Device

Device: AM64X_DEV_ECAP1 (ID = 52)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_ECAP1_VBUS_CLK Input clock

Clocks for ECAP2 Device

Device: AM64X_DEV_ECAP2 (ID = 53)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_ECAP2_VBUS_CLK Input clock

Clocks for ELM0 Device

Device: AM64X_DEV_ELM0 (ID = 54)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_ELM0_VBUSP_CLK Input clock

Clocks for EMIF_DATA_0_VD Device

This device has no defined clocks.

Clocks for EPWM0 Device

Device: AM64X_DEV_EPWM0 (ID = 86)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_EPWM0_VBUSP_CLK Input clock

Clocks for EPWM1 Device

Device: AM64X_DEV_EPWM1 (ID = 87)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_EPWM1_VBUSP_CLK Input clock

Clocks for EPWM2 Device

Device: AM64X_DEV_EPWM2 (ID = 88)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_EPWM2_VBUSP_CLK Input clock

Clocks for EPWM3 Device

Device: AM64X_DEV_EPWM3 (ID = 89)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_EPWM3_VBUSP_CLK Input clock

Clocks for EPWM4 Device

Device: AM64X_DEV_EPWM4 (ID = 90)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_EPWM4_VBUSP_CLK Input clock

Clocks for EPWM5 Device

Device: AM64X_DEV_EPWM5 (ID = 91)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_EPWM5_VBUSP_CLK Input clock

Clocks for EPWM6 Device

Device: AM64X_DEV_EPWM6 (ID = 92)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_EPWM6_VBUSP_CLK Input clock

Clocks for EPWM7 Device

Device: AM64X_DEV_EPWM7 (ID = 93)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_EPWM7_VBUSP_CLK Input clock

Clocks for EPWM8 Device

Device: AM64X_DEV_EPWM8 (ID = 94)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_EPWM8_VBUSP_CLK Input clock

Clocks for EQEP0 Device

Device: AM64X_DEV_EQEP0 (ID = 59)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_EQEP0_VBUS_CLK Input clock

Clocks for EQEP1 Device

Device: AM64X_DEV_EQEP1 (ID = 60)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_EQEP1_VBUS_CLK Input clock

Clocks for EQEP2 Device

Device: AM64X_DEV_EQEP2 (ID = 62)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_EQEP2_VBUS_CLK Input clock

Clocks for ESM0 Device

Device: AM64X_DEV_ESM0 (ID = 63)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_ESM0_CLK Input clock

Clocks for FSIRX0 Device

Device: AM64X_DEV_FSIRX0 (ID = 65)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_FSIRX0_FSI_RX_CK Input clock
1 DEV_FSIRX0_FSI_RX_LPBK_CK Input clock
2 DEV_FSIRX0_FSI_RX_VBUS_CLK Input clock

Clocks for FSIRX1 Device

Device: AM64X_DEV_FSIRX1 (ID = 66)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_FSIRX1_FSI_RX_CK Input clock
1 DEV_FSIRX1_FSI_RX_LPBK_CK Input clock
2 DEV_FSIRX1_FSI_RX_VBUS_CLK Input clock

Clocks for FSIRX2 Device

Device: AM64X_DEV_FSIRX2 (ID = 67)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_FSIRX2_FSI_RX_CK Input clock
1 DEV_FSIRX2_FSI_RX_LPBK_CK Input clock
2 DEV_FSIRX2_FSI_RX_VBUS_CLK Input clock

Clocks for FSIRX3 Device

Device: AM64X_DEV_FSIRX3 (ID = 68)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_FSIRX3_FSI_RX_CK Input clock
1 DEV_FSIRX3_FSI_RX_LPBK_CK Input clock
2 DEV_FSIRX3_FSI_RX_VBUS_CLK Input clock

Clocks for FSIRX4 Device

Device: AM64X_DEV_FSIRX4 (ID = 69)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_FSIRX4_FSI_RX_CK Input clock
1 DEV_FSIRX4_FSI_RX_LPBK_CK Input clock
2 DEV_FSIRX4_FSI_RX_VBUS_CLK Input clock

Clocks for FSIRX5 Device

Device: AM64X_DEV_FSIRX5 (ID = 70)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_FSIRX5_FSI_RX_CK Input clock
1 DEV_FSIRX5_FSI_RX_LPBK_CK Input clock
2 DEV_FSIRX5_FSI_RX_VBUS_CLK Input clock

Clocks for FSITX0 Device

Device: AM64X_DEV_FSITX0 (ID = 71)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_FSITX0_FSI_TX_PLL_CLK Input clock
1 DEV_FSITX0_FSI_TX_VBUS_CLK Input clock
2 DEV_FSITX0_FSI_TX_CK Output clock

Clocks for FSITX1 Device

Device: AM64X_DEV_FSITX1 (ID = 72)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_FSITX1_FSI_TX_PLL_CLK Input clock
1 DEV_FSITX1_FSI_TX_VBUS_CLK Input clock
2 DEV_FSITX1_FSI_TX_CK Output clock

Clocks for FSS0 Device

This device has no defined clocks.

Clocks for FSS0_FSAS_0 Device

Device: AM64X_DEV_FSS0_FSAS_0 (ID = 74)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_FSS0_FSAS_0_GCLK Input clock

Clocks for FSS0_OSPI_0 Device

Device: AM64X_DEV_FSS0_OSPI_0 (ID = 75)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_FSS0_OSPI_0_OSPI_DQS_CLK Input clock
1 DEV_FSS0_OSPI_0_OSPI_HCLK_CLK Input clock
2 DEV_FSS0_OSPI_0_OSPI_ICLK_CLK Input muxed clock
3 DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_DQS_OUT Parent input clock option to DEV_FSS0_OSPI_0_OSPI_ICLK_CLK
4 DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_LBCLKO_OUT Parent input clock option to DEV_FSS0_OSPI_0_OSPI_ICLK_CLK
5 DEV_FSS0_OSPI_0_OSPI_PCLK_CLK Input clock
6 DEV_FSS0_OSPI_0_OSPI_RCLK_CLK Input muxed clock
7 DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK Parent input clock option to DEV_FSS0_OSPI_0_OSPI_RCLK_CLK
8 DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT5_CLK Parent input clock option to DEV_FSS0_OSPI_0_OSPI_RCLK_CLK
9 DEV_FSS0_OSPI_0_OSPI_OCLK_CLK Output clock

Clocks for GICSS0 Device

Device: AM64X_DEV_GICSS0 (ID = 76)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_GICSS0_VCLK_CLK Input clock

Clocks for GPIO0 Device

Device: AM64X_DEV_GPIO0 (ID = 77)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_GPIO0_MMR_CLK Input clock

Clocks for GPIO1 Device

Device: AM64X_DEV_GPIO1 (ID = 78)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_GPIO1_MMR_CLK Input clock

Clocks for GPMC0 Device

Device: AM64X_DEV_GPMC0 (ID = 80)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_GPMC0_FUNC_CLK Input muxed clock
1 DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK Parent input clock option to DEV_GPMC0_FUNC_CLK
2 DEV_GPMC0_FUNC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK Parent input clock option to DEV_GPMC0_FUNC_CLK
3 DEV_GPMC0_PI_GPMC_RET_CLK Input clock
4 DEV_GPMC0_VBUSM_CLK Input clock
5 DEV_GPMC0_PO_GPMC_DEV_CLK Output clock

Clocks for GTC0 Device

Device: AM64X_DEV_GTC0 (ID = 61)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_GTC0_GTC_CLK Input muxed clock
1 DEV_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK Parent input clock option to DEV_GTC0_GTC_CLK
2 DEV_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK Parent input clock option to DEV_GTC0_GTC_CLK
3 DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_GTC0_GTC_CLK
4 DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_GTC0_GTC_CLK
5 DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_GTC0_GTC_CLK
6 DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_GTC0_GTC_CLK
7 DEV_GTC0_GTC_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK Parent input clock option to DEV_GTC0_GTC_CLK
8 DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK Parent input clock option to DEV_GTC0_GTC_CLK
9 DEV_GTC0_VBUSP_CLK Input clock

Clocks for I2C0 Device

Device: AM64X_DEV_I2C0 (ID = 102)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_I2C0_CLK Input clock
1 DEV_I2C0_PISCL Input clock
2 DEV_I2C0_PISYS_CLK Input clock
3 DEV_I2C0_PORSCL Output clock

Clocks for I2C1 Device

Device: AM64X_DEV_I2C1 (ID = 103)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_I2C1_CLK Input clock
1 DEV_I2C1_PISCL Input clock
2 DEV_I2C1_PISYS_CLK Input clock
3 DEV_I2C1_PORSCL Output clock

Clocks for I2C2 Device

Device: AM64X_DEV_I2C2 (ID = 104)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_I2C2_CLK Input clock
1 DEV_I2C2_PISCL Input clock
2 DEV_I2C2_PISYS_CLK Input clock
3 DEV_I2C2_PORSCL Output clock

Clocks for I2C3 Device

Device: AM64X_DEV_I2C3 (ID = 105)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_I2C3_CLK Input clock
1 DEV_I2C3_PISCL Input clock
2 DEV_I2C3_PISYS_CLK Input clock
3 DEV_I2C3_PORSCL Output clock

Clocks for LED0 Device

Device: AM64X_DEV_LED0 (ID = 83)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_LED0_LED_CLK Input clock
1 DEV_LED0_VBUSP_CLK Input clock

Clocks for MAILBOX0 Device

This device has no defined clocks.

Clocks for MAIN2MCU_VD Device

This device has no defined clocks.

Clocks for MAIN_GPIOMUX_INTROUTER0 Device

Device: AM64X_DEV_MAIN_GPIOMUX_INTROUTER0 (ID = 3)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MAIN_GPIOMUX_INTROUTER0_INTR_CLK Input clock

Clocks for MCAN0 Device

Device: AM64X_DEV_MCAN0 (ID = 98)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCAN0_MCANSS_CCLK_CLK Input muxed clock
1 DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK
2 DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK
3 DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK
4 DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK
5 DEV_MCAN0_MCANSS_HCLK_CLK Input clock

Clocks for MCAN1 Device

Device: AM64X_DEV_MCAN1 (ID = 99)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCAN1_MCANSS_CCLK_CLK Input muxed clock
1 DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK
2 DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK
3 DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK
4 DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK
5 DEV_MCAN1_MCANSS_HCLK_CLK Input clock

Clocks for MCSPI0 Device

Device: AM64X_DEV_MCSPI0 (ID = 141)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCSPI0_CLKSPIREF_CLK Input clock
1 DEV_MCSPI0_IO_CLKSPII_CLK Input muxed clock
2 DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI0_CLK_OUT Parent input clock option to DEV_MCSPI0_IO_CLKSPII_CLK
3 DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MAIN_0_IO_CLKSPIO_CLK Parent input clock option to DEV_MCSPI0_IO_CLKSPII_CLK
4 DEV_MCSPI0_VBUSP_CLK Input clock
5 DEV_MCSPI0_IO_CLKSPIO_CLK Output clock

Clocks for MCSPI1 Device

Device: AM64X_DEV_MCSPI1 (ID = 142)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCSPI1_CLKSPIREF_CLK Input clock
1 DEV_MCSPI1_IO_CLKSPII_CLK Input muxed clock
2 DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI1_CLK_OUT Parent input clock option to DEV_MCSPI1_IO_CLKSPII_CLK
3 DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_1_IO_CLKSPIO_CLK Parent input clock option to DEV_MCSPI1_IO_CLKSPII_CLK
4 DEV_MCSPI1_VBUSP_CLK Input clock
5 DEV_MCSPI1_IO_CLKSPIO_CLK Output clock

Clocks for MCSPI2 Device

Device: AM64X_DEV_MCSPI2 (ID = 143)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCSPI2_CLKSPIREF_CLK Input clock
1 DEV_MCSPI2_IO_CLKSPII_CLK Input muxed clock
2 DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI2_CLK_OUT Parent input clock option to DEV_MCSPI2_IO_CLKSPII_CLK
3 DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_SPI_MAIN_2_IO_CLKSPIO_CLK Parent input clock option to DEV_MCSPI2_IO_CLKSPII_CLK
4 DEV_MCSPI2_VBUSP_CLK Input clock
5 DEV_MCSPI2_IO_CLKSPIO_CLK Output clock

Clocks for MCSPI3 Device

Device: AM64X_DEV_MCSPI3 (ID = 144)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCSPI3_CLKSPIREF_CLK Input clock
1 DEV_MCSPI3_IO_CLKSPII_CLK Input muxed clock
2 DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI3_CLK_OUT Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK
3 DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK
4 DEV_MCSPI3_VBUSP_CLK Input clock
5 DEV_MCSPI3_IO_CLKSPIO_CLK Output clock

Clocks for MCSPI4 Device

Device: AM64X_DEV_MCSPI4 (ID = 145)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCSPI4_CLKSPIREF_CLK Input clock
1 DEV_MCSPI4_IO_CLKSPII_CLK Input muxed clock
2 DEV_MCSPI4_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI4_CLK_OUT Parent input clock option to DEV_MCSPI4_IO_CLKSPII_CLK
3 DEV_MCSPI4_IO_CLKSPII_CLK_PARENT_SPI_MAIN_4_IO_CLKSPIO_CLK Parent input clock option to DEV_MCSPI4_IO_CLKSPII_CLK
4 DEV_MCSPI4_VBUSP_CLK Input clock
5 DEV_MCSPI4_IO_CLKSPIO_CLK Output clock

Clocks for MCU2MAIN_VD Device

This device has no defined clocks.

Clocks for MCU_DCC0 Device

Device: AM64X_DEV_MCU_DCC0 (ID = 23)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_DCC0_DCC_CLKSRC0_CLK Input clock
1 DEV_MCU_DCC0_DCC_CLKSRC1_CLK Input clock
2 DEV_MCU_DCC0_DCC_CLKSRC2_CLK Input clock
3 DEV_MCU_DCC0_DCC_CLKSRC3_CLK Input clock
4 DEV_MCU_DCC0_DCC_CLKSRC4_CLK Input clock
5 DEV_MCU_DCC0_DCC_CLKSRC5_CLK Input clock
6 DEV_MCU_DCC0_DCC_CLKSRC6_CLK Input clock
7 DEV_MCU_DCC0_DCC_CLKSRC7_CLK Input clock
8 DEV_MCU_DCC0_DCC_INPUT00_CLK Input clock
9 DEV_MCU_DCC0_DCC_INPUT01_CLK Input clock
10 DEV_MCU_DCC0_DCC_INPUT02_CLK Input clock
11 DEV_MCU_DCC0_DCC_INPUT10_CLK Input clock
12 DEV_MCU_DCC0_VBUS_CLK Input clock

Clocks for MCU_ESM0 Device

Device: AM64X_DEV_MCU_ESM0 (ID = 64)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_ESM0_CLK Input clock

Clocks for MCU_GPIO0 Device

Device: AM64X_DEV_MCU_GPIO0 (ID = 79)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_GPIO0_MMR_CLK Input clock

Clocks for MCU_I2C0 Device

Device: AM64X_DEV_MCU_I2C0 (ID = 106)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_I2C0_CLK Input clock
1 DEV_MCU_I2C0_PISCL Input clock
2 DEV_MCU_I2C0_PISYS_CLK Input clock
3 DEV_MCU_I2C0_PORSCL Output clock

Clocks for MCU_I2C1 Device

Device: AM64X_DEV_MCU_I2C1 (ID = 107)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_I2C1_CLK Input clock
1 DEV_MCU_I2C1_PISCL Input clock
2 DEV_MCU_I2C1_PISYS_CLK Input clock
3 DEV_MCU_I2C1_PORSCL Output clock

Clocks for MCU_M4FSS0 Device

This device has no defined clocks.

Clocks for MCU_M4FSS0_CORE0 Device

Device: AM64X_DEV_MCU_M4FSS0_CORE0 (ID = 9)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_M4FSS0_CORE0_DAP_CLK Input clock
1 DEV_MCU_M4FSS0_CORE0_VBUS_CLK Input muxed clock
2 DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK Parent input clock option to DEV_MCU_M4FSS0_CORE0_VBUS_CLK
3 DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK2 Parent input clock option to DEV_MCU_M4FSS0_CORE0_VBUS_CLK

Clocks for MCU_MCRC64_0 Device

Device: AM64X_DEV_MCU_MCRC64_0 (ID = 100)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_MCRC64_0_CLK Input clock

Clocks for MCU_MCSPI0 Device

Device: AM64X_DEV_MCU_MCSPI0 (ID = 147)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_MCSPI0_CLKSPIREF_CLK Input clock
1 DEV_MCU_MCSPI0_IO_CLKSPII_CLK Input muxed clock
2 DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI0_CLK_OUT Parent input clock option to DEV_MCU_MCSPI0_IO_CLKSPII_CLK
3 DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MCU_0_IO_CLKSPIO_CLK Parent input clock option to DEV_MCU_MCSPI0_IO_CLKSPII_CLK
4 DEV_MCU_MCSPI0_VBUSP_CLK Input clock
5 DEV_MCU_MCSPI0_IO_CLKSPIO_CLK Output clock

Clocks for MCU_MCSPI1 Device

Device: AM64X_DEV_MCU_MCSPI1 (ID = 148)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_MCSPI1_CLKSPIREF_CLK Input clock
1 DEV_MCU_MCSPI1_IO_CLKSPII_CLK Input muxed clock
2 DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI1_CLK_OUT Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK
3 DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MCU_1_IO_CLKSPIO_CLK Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK
4 DEV_MCU_MCSPI1_VBUSP_CLK Input clock
5 DEV_MCU_MCSPI1_IO_CLKSPIO_CLK Output clock

Clocks for MCU_MCU_GPIOMUX_INTROUTER0 Device

Device: AM64X_DEV_MCU_MCU_GPIOMUX_INTROUTER0 (ID = 5)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_MCU_GPIOMUX_INTROUTER0_INTR_CLK Input clock

Clocks for MCU_PSC0 Device

Device: AM64X_DEV_MCU_PSC0 (ID = 140)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_PSC0_CLK Input clock
1 DEV_MCU_PSC0_SLOW_CLK Input clock

Clocks for MCU_RTI0 Device

Device: AM64X_DEV_MCU_RTI0 (ID = 132)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_RTI0_RTI_CLK Input muxed clock
1 DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCU_RTI0_RTI_CLK
2 DEV_MCU_RTI0_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8 Parent input clock option to DEV_MCU_RTI0_RTI_CLK
3 DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_MCU_RTI0_RTI_CLK
4 DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 Parent input clock option to DEV_MCU_RTI0_RTI_CLK
5 DEV_MCU_RTI0_VBUSP_CLK Input clock

Clocks for MCU_TIMER0 Device

Device: AM64X_DEV_MCU_TIMER0 (ID = 35)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_TIMER0_TIMER_HCLK_CLK Input clock
1 DEV_MCU_TIMER0_TIMER_TCLK_CLK Input muxed clock
2 DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
3 DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4 Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
4 DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
5 DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
6 DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
7 DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8 Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
8 DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
9 DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK
10 DEV_MCU_TIMER0_TIMER_PWM Output clock

Clocks for MCU_TIMER1 Device

Device: AM64X_DEV_MCU_TIMER1 (ID = 48)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_TIMER1_TIMER_HCLK_CLK Input clock
1 DEV_MCU_TIMER1_TIMER_TCLK_CLK Input muxed clock
2 DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK
3 DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4 Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK
4 DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK
5 DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK
6 DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK
7 DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8 Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK
8 DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK
9 DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK
10 DEV_MCU_TIMER1_TIMER_PWM Output clock

Clocks for MCU_TIMER2 Device

Device: AM64X_DEV_MCU_TIMER2 (ID = 49)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_TIMER2_TIMER_HCLK_CLK Input clock
1 DEV_MCU_TIMER2_TIMER_TCLK_CLK Input muxed clock
2 DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
3 DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4 Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
4 DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
5 DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
6 DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
7 DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8 Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
8 DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
9 DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK
10 DEV_MCU_TIMER2_TIMER_PWM Output clock

Clocks for MCU_TIMER3 Device

Device: AM64X_DEV_MCU_TIMER3 (ID = 50)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_TIMER3_TIMER_HCLK_CLK Input clock
1 DEV_MCU_TIMER3_TIMER_TCLK_CLK Input muxed clock
2 DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK
3 DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4 Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK
4 DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK
5 DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK
6 DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK
7 DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8 Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK
8 DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK
9 DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK
10 DEV_MCU_TIMER3_TIMER_PWM Output clock

Clocks for MCU_UART0 Device

Device: AM64X_DEV_MCU_UART0 (ID = 149)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_UART0_FCLK_CLK Input clock
1 DEV_MCU_UART0_VBUSP_CLK Input clock

Clocks for MCU_UART1 Device

Device: AM64X_DEV_MCU_UART1 (ID = 160)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MCU_UART1_FCLK_CLK Input clock
1 DEV_MCU_UART1_VBUSP_CLK Input clock

Clocks for MMCSD0 Device

Device: AM64X_DEV_MMCSD0 (ID = 57)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MMCSD0_EMMCSS_VBUS_CLK Input clock
1 DEV_MMCSD0_EMMCSS_XIN_CLK Input muxed clock
2 DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK
3 DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK

Clocks for MMCSD1 Device

Device: AM64X_DEV_MMCSD1 (ID = 58)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MMCSD1_EMMCSDSS_IO_CLK_I Input muxed clock
1 DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC1_CLKLB_OUT Parent input clock option to DEV_MMCSD1_EMMCSDSS_IO_CLK_I
2 DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_EMMCSD4SS_MAIN_0_EMMCSDSS_IO_CLK_O Parent input clock option to DEV_MMCSD1_EMMCSDSS_IO_CLK_I
3 DEV_MMCSD1_EMMCSDSS_VBUS_CLK Input clock
4 DEV_MMCSD1_EMMCSDSS_XIN_CLK Input muxed clock
5 DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK
6 DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK
7 DEV_MMCSD1_EMMCSDSS_IO_CLK_O Output clock

Clocks for MSRAM_256K0 Device

Device: AM64X_DEV_MSRAM_256K0 (ID = 108)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MSRAM_256K0_CCLK_CLK Input clock
1 DEV_MSRAM_256K0_VCLK_CLK Input clock

Clocks for MSRAM_256K1 Device

Device: AM64X_DEV_MSRAM_256K1 (ID = 109)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MSRAM_256K1_CCLK_CLK Input clock
1 DEV_MSRAM_256K1_VCLK_CLK Input clock

Clocks for MSRAM_256K2 Device

Device: AM64X_DEV_MSRAM_256K2 (ID = 110)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MSRAM_256K2_CCLK_CLK Input clock
1 DEV_MSRAM_256K2_VCLK_CLK Input clock

Clocks for MSRAM_256K3 Device

Device: AM64X_DEV_MSRAM_256K3 (ID = 111)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MSRAM_256K3_CCLK_CLK Input clock
1 DEV_MSRAM_256K3_VCLK_CLK Input clock

Clocks for MSRAM_256K4 Device

Device: AM64X_DEV_MSRAM_256K4 (ID = 112)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MSRAM_256K4_CCLK_CLK Input clock
1 DEV_MSRAM_256K4_VCLK_CLK Input clock

Clocks for MSRAM_256K5 Device

Device: AM64X_DEV_MSRAM_256K5 (ID = 113)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_MSRAM_256K5_CCLK_CLK Input clock
1 DEV_MSRAM_256K5_VCLK_CLK Input clock

Clocks for PBIST0 Device

Device: AM64X_DEV_PBIST0 (ID = 163)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_PBIST0_CLK8_CLK Input clock

Clocks for PBIST1 Device

Device: AM64X_DEV_PBIST1 (ID = 164)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_PBIST1_CLK8_CLK Input clock

Clocks for PBIST2 Device

Device: AM64X_DEV_PBIST2 (ID = 165)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_PBIST2_CLK8_CLK Input clock

Clocks for PBIST3 Device

Device: AM64X_DEV_PBIST3 (ID = 166)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_PBIST3_CLK8_CLK Input clock

Clocks for PCIE0 Device

Device: AM64X_DEV_PCIE0 (ID = 114)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_PCIE0_PCIE_CBA_CLK Input clock
1 DEV_PCIE0_PCIE_CPTS_RCLK_CLK Input muxed clock
2 DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK
3 DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK
4 DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK
5 DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK
6 DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK
7 DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK
8 DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK
10 DEV_PCIE0_PCIE_LANE0_REFCLK Input clock
11 DEV_PCIE0_PCIE_LANE0_RXCLK Input clock
12 DEV_PCIE0_PCIE_LANE0_RXFCLK Input clock
13 DEV_PCIE0_PCIE_LANE0_TXFCLK Input clock
14 DEV_PCIE0_PCIE_LANE0_TXMCLK Input clock
15 DEV_PCIE0_PCIE_PM_CLK Input clock
16 DEV_PCIE0_PCIE_LANE0_TXCLK Output clock

Clocks for POSTDIV1_16FFT1 Device

Device: AM64X_DEV_POSTDIV1_16FFT1 (ID = 115)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_POSTDIV1_16FFT1_FREF_CLK Input clock
1 DEV_POSTDIV1_16FFT1_POSTDIV_CLKIN_CLK Input clock
2 DEV_POSTDIV1_16FFT1_HSDIVOUT5_CLK Output clock
3 DEV_POSTDIV1_16FFT1_HSDIVOUT6_CLK Output clock

Clocks for POSTDIV4_16FF0 Device

Device: AM64X_DEV_POSTDIV4_16FF0 (ID = 116)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_POSTDIV4_16FF0_FREF_CLK Input clock
1 DEV_POSTDIV4_16FF0_POSTDIV_CLKIN_CLK Input clock
2 DEV_POSTDIV4_16FF0_HSDIVOUT5_CLK Output clock
3 DEV_POSTDIV4_16FF0_HSDIVOUT6_CLK Output clock
4 DEV_POSTDIV4_16FF0_HSDIVOUT7_CLK Output clock
5 DEV_POSTDIV4_16FF0_HSDIVOUT8_CLK Output clock
6 DEV_POSTDIV4_16FF0_HSDIVOUT9_CLK Output clock

Clocks for POSTDIV4_16FF2 Device

Device: AM64X_DEV_POSTDIV4_16FF2 (ID = 117)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_POSTDIV4_16FF2_FREF_CLK Input clock
1 DEV_POSTDIV4_16FF2_POSTDIV_CLKIN_CLK Input clock
2 DEV_POSTDIV4_16FF2_HSDIVOUT5_CLK Output clock
3 DEV_POSTDIV4_16FF2_HSDIVOUT6_CLK Output clock
4 DEV_POSTDIV4_16FF2_HSDIVOUT7_CLK Output clock
5 DEV_POSTDIV4_16FF2_HSDIVOUT8_CLK Output clock
6 DEV_POSTDIV4_16FF2_HSDIVOUT9_CLK Output clock

Clocks for PRU_ICSSG0 Device

Device: AM64X_DEV_PRU_ICSSG0 (ID = 81)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_PRU_ICSSG0_CORE_CLK Input muxed clock
1 DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK
2 DEV_PRU_ICSSG0_CORE_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK
3 DEV_PRU_ICSSG0_IEP_CLK Input muxed clock
4 DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK
5 DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK
6 DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK
7 DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK
8 DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK
9 DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK
10 DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK
11 DEV_PRU_ICSSG0_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK
12 DEV_PRU_ICSSG0_PR1_RGMII0_RXC_I Input clock
13 DEV_PRU_ICSSG0_PR1_RGMII0_TXC_I Input clock
14 DEV_PRU_ICSSG0_PR1_RGMII1_RXC_I Input clock
15 DEV_PRU_ICSSG0_PR1_RGMII1_TXC_I Input clock
16 DEV_PRU_ICSSG0_RGMII_MHZ_250_CLK Input clock
17 DEV_PRU_ICSSG0_RGMII_MHZ_50_CLK Input clock
18 DEV_PRU_ICSSG0_RGMII_MHZ_5_CLK Input clock
19 DEV_PRU_ICSSG0_UCLK_CLK Input clock
20 DEV_PRU_ICSSG0_VCLK_CLK Input clock
21 DEV_PRU_ICSSG0_PR1_MDIO_MDCLK_O Output clock
22 DEV_PRU_ICSSG0_PR1_RGMII0_TXC_O Output clock
23 DEV_PRU_ICSSG0_PR1_RGMII1_TXC_O Output clock

Clocks for PRU_ICSSG1 Device

Device: AM64X_DEV_PRU_ICSSG1 (ID = 82)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_PRU_ICSSG1_CORE_CLK Input muxed clock
1 DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK
2 DEV_PRU_ICSSG1_CORE_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK
3 DEV_PRU_ICSSG1_IEP_CLK Input muxed clock
4 DEV_PRU_ICSSG1_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK
5 DEV_PRU_ICSSG1_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK
6 DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK
7 DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK
8 DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK
9 DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK
10 DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK
11 DEV_PRU_ICSSG1_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK
12 DEV_PRU_ICSSG1_PR1_RGMII0_RXC_I Input clock
13 DEV_PRU_ICSSG1_PR1_RGMII0_TXC_I Input clock
14 DEV_PRU_ICSSG1_PR1_RGMII1_RXC_I Input clock
15 DEV_PRU_ICSSG1_PR1_RGMII1_TXC_I Input clock
16 DEV_PRU_ICSSG1_RGMII_MHZ_250_CLK Input clock
17 DEV_PRU_ICSSG1_RGMII_MHZ_50_CLK Input clock
18 DEV_PRU_ICSSG1_RGMII_MHZ_5_CLK Input clock
19 DEV_PRU_ICSSG1_UCLK_CLK Input clock
20 DEV_PRU_ICSSG1_VCLK_CLK Input clock
21 DEV_PRU_ICSSG1_PR1_MDIO_MDCLK_O Output clock
22 DEV_PRU_ICSSG1_PR1_RGMII0_TXC_O Output clock
23 DEV_PRU_ICSSG1_PR1_RGMII1_TXC_O Output clock

Clocks for PSC0 Device

Device: AM64X_DEV_PSC0 (ID = 139)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_PSC0_CLK Input clock
1 DEV_PSC0_SLOW_CLK Input clock

Clocks for PSRAMECC0 Device

Device: AM64X_DEV_PSRAMECC0 (ID = 118)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_PSRAMECC0_CLK_CLK Input clock

Clocks for R5FSS0 Device

This device has no defined clocks.

Clocks for R5FSS0_CORE0 Device

Device: AM64X_DEV_R5FSS0_CORE0 (ID = 121)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_R5FSS0_CORE0_CPU_CLK Input clock
1 DEV_R5FSS0_CORE0_INTERFACE_CLK Input clock

Clocks for R5FSS0_CORE1 Device

Device: AM64X_DEV_R5FSS0_CORE1 (ID = 122)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_R5FSS0_CORE1_CPU_CLK Input clock
1 DEV_R5FSS0_CORE1_INTERFACE_CLK Input clock

Clocks for R5FSS1 Device

This device has no defined clocks.

Clocks for R5FSS1_CORE0 Device

Device: AM64X_DEV_R5FSS1_CORE0 (ID = 123)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_R5FSS1_CORE0_CPU_CLK Input clock
1 DEV_R5FSS1_CORE0_INTERFACE_CLK Input clock

Clocks for R5FSS1_CORE1 Device

Device: AM64X_DEV_R5FSS1_CORE1 (ID = 124)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_R5FSS1_CORE1_CPU_CLK Input clock
1 DEV_R5FSS1_CORE1_INTERFACE_CLK Input clock

Clocks for RTI0 Device

Device: AM64X_DEV_RTI0 (ID = 125)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_RTI0_RTI_CLK Input muxed clock
1 DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_RTI0_RTI_CLK
2 DEV_RTI0_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8 Parent input clock option to DEV_RTI0_RTI_CLK
3 DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_RTI0_RTI_CLK
4 DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 Parent input clock option to DEV_RTI0_RTI_CLK
5 DEV_RTI0_VBUSP_CLK Input clock

Clocks for RTI1 Device

Device: AM64X_DEV_RTI1 (ID = 126)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_RTI1_RTI_CLK Input muxed clock
1 DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_RTI1_RTI_CLK
2 DEV_RTI1_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8 Parent input clock option to DEV_RTI1_RTI_CLK
3 DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_RTI1_RTI_CLK
4 DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 Parent input clock option to DEV_RTI1_RTI_CLK
5 DEV_RTI1_VBUSP_CLK Input clock

Clocks for RTI10 Device

Device: AM64X_DEV_RTI10 (ID = 130)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_RTI10_RTI_CLK Input muxed clock
1 DEV_RTI10_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_RTI10_RTI_CLK
2 DEV_RTI10_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8 Parent input clock option to DEV_RTI10_RTI_CLK
3 DEV_RTI10_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_RTI10_RTI_CLK
4 DEV_RTI10_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 Parent input clock option to DEV_RTI10_RTI_CLK
5 DEV_RTI10_VBUSP_CLK Input clock

Clocks for RTI11 Device

Device: AM64X_DEV_RTI11 (ID = 131)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_RTI11_RTI_CLK Input muxed clock
1 DEV_RTI11_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_RTI11_RTI_CLK
2 DEV_RTI11_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8 Parent input clock option to DEV_RTI11_RTI_CLK
3 DEV_RTI11_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_RTI11_RTI_CLK
4 DEV_RTI11_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 Parent input clock option to DEV_RTI11_RTI_CLK
5 DEV_RTI11_VBUSP_CLK Input clock

Clocks for RTI8 Device

Device: AM64X_DEV_RTI8 (ID = 127)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_RTI8_RTI_CLK Input muxed clock
1 DEV_RTI8_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_RTI8_RTI_CLK
2 DEV_RTI8_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8 Parent input clock option to DEV_RTI8_RTI_CLK
3 DEV_RTI8_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_RTI8_RTI_CLK
4 DEV_RTI8_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 Parent input clock option to DEV_RTI8_RTI_CLK
5 DEV_RTI8_VBUSP_CLK Input clock

Clocks for RTI9 Device

Device: AM64X_DEV_RTI9 (ID = 128)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_RTI9_RTI_CLK Input muxed clock
1 DEV_RTI9_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_RTI9_RTI_CLK
2 DEV_RTI9_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8 Parent input clock option to DEV_RTI9_RTI_CLK
3 DEV_RTI9_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_RTI9_RTI_CLK
4 DEV_RTI9_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3 Parent input clock option to DEV_RTI9_RTI_CLK
5 DEV_RTI9_VBUSP_CLK Input clock

Clocks for SA2_UL0 Device

Device: AM64X_DEV_SA2_UL0 (ID = 133)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_SA2_UL0_PKA_IN_CLK Input clock
1 DEV_SA2_UL0_X1_CLK Input clock
2 DEV_SA2_UL0_X2_CLK Input clock

Clocks for SERDES_10G0 Device

Device: AM64X_DEV_SERDES_10G0 (ID = 162)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_SERDES_10G0_CLK Input clock
1 DEV_SERDES_10G0_CORE_REF_CLK Input muxed clock
2 DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK
3 DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK
4 DEV_SERDES_10G0_CORE_REF_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK
5 DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK
6 DEV_SERDES_10G0_IP1_LN0_TXCLK Input clock
7 DEV_SERDES_10G0_IP2_LN0_TXCLK Input clock
8 DEV_SERDES_10G0_IP1_LN0_REFCLK Output clock
9 DEV_SERDES_10G0_IP1_LN0_RXCLK Output clock
10 DEV_SERDES_10G0_IP1_LN0_RXFCLK Output clock
11 DEV_SERDES_10G0_IP1_LN0_TXFCLK Output clock
12 DEV_SERDES_10G0_IP1_LN0_TXMCLK Output clock
13 DEV_SERDES_10G0_IP2_LN0_REFCLK Output clock
14 DEV_SERDES_10G0_IP2_LN0_RXCLK Output clock
15 DEV_SERDES_10G0_IP2_LN0_RXFCLK Output clock
16 DEV_SERDES_10G0_IP2_LN0_TXFCLK Output clock
17 DEV_SERDES_10G0_IP2_LN0_TXMCLK Output clock

Clocks for SPINLOCK0 Device

Device: AM64X_DEV_SPINLOCK0 (ID = 150)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_SPINLOCK0_VCLK_CLK Input clock

Clocks for STM0 Device

Device: AM64X_DEV_STM0 (ID = 15)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_STM0_ATB_CLK Input clock
1 DEV_STM0_CORE_CLK Input clock
2 DEV_STM0_VBUSP_CLK Input clock

Clocks for TIMER0 Device

Device: AM64X_DEV_TIMER0 (ID = 36)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER0_TIMER_HCLK_CLK Input clock
1 DEV_TIMER0_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
3 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8 Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
4 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
5 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
6 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
7 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2 Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
8 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3 Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
9 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4 Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
10 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
11 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
12 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
13 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
14 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
15 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
16 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
17 DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK
18 DEV_TIMER0_TIMER_PWM Output clock

Clocks for TIMER1 Device

Device: AM64X_DEV_TIMER1 (ID = 37)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER1_TIMER_HCLK_CLK Input clock
1 DEV_TIMER1_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK
3 DEV_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8 Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK
4 DEV_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK
5 DEV_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK
6 DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK
7 DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2 Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK
8 DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3 Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK
9 DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4 Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK
10 DEV_TIMER1_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK
11 DEV_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK
12 DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK
13 DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK
14 DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK
15 DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK
16 DEV_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK
17 DEV_TIMER1_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK
18 DEV_TIMER1_TIMER_PWM Output clock

Clocks for TIMER10 Device

Device: AM64X_DEV_TIMER10 (ID = 46)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER10_TIMER_HCLK_CLK Input clock
1 DEV_TIMER10_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
3 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8 Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
4 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
5 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
6 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
7 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2 Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
8 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3 Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
9 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4 Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
10 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
11 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
12 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
13 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
14 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
15 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
16 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
17 DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK
18 DEV_TIMER10_TIMER_PWM Output clock

Clocks for TIMER11 Device

Device: AM64X_DEV_TIMER11 (ID = 47)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER11_TIMER_HCLK_CLK Input clock
1 DEV_TIMER11_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER11_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK
3 DEV_TIMER11_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8 Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK
4 DEV_TIMER11_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK
5 DEV_TIMER11_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK
6 DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK
7 DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2 Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK
8 DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3 Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK
9 DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4 Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK
10 DEV_TIMER11_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK
11 DEV_TIMER11_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK
12 DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK
13 DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK
14 DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK
15 DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK
16 DEV_TIMER11_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK
17 DEV_TIMER11_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK
18 DEV_TIMER11_TIMER_PWM Output clock

Clocks for TIMER2 Device

Device: AM64X_DEV_TIMER2 (ID = 38)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER2_TIMER_HCLK_CLK Input clock
1 DEV_TIMER2_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
3 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8 Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
4 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
5 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
6 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
7 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2 Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
8 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3 Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
9 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4 Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
10 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
11 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
12 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
13 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
14 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
15 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
16 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
17 DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK
18 DEV_TIMER2_TIMER_PWM Output clock

Clocks for TIMER3 Device

Device: AM64X_DEV_TIMER3 (ID = 39)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER3_TIMER_HCLK_CLK Input clock
1 DEV_TIMER3_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK
3 DEV_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8 Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK
4 DEV_TIMER3_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK
5 DEV_TIMER3_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK
6 DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK
7 DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2 Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK
8 DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3 Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK
9 DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4 Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK
10 DEV_TIMER3_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK
11 DEV_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK
12 DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK
13 DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK
14 DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK
15 DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK
16 DEV_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK
17 DEV_TIMER3_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK
18 DEV_TIMER3_TIMER_PWM Output clock

Clocks for TIMER4 Device

Device: AM64X_DEV_TIMER4 (ID = 40)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER4_TIMER_HCLK_CLK Input clock
1 DEV_TIMER4_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
3 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8 Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
4 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
5 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
6 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
7 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2 Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
8 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3 Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
9 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4 Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
10 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
11 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
12 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
13 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
14 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
15 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
16 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
17 DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK
18 DEV_TIMER4_TIMER_PWM Output clock

Clocks for TIMER5 Device

Device: AM64X_DEV_TIMER5 (ID = 41)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER5_TIMER_HCLK_CLK Input clock
1 DEV_TIMER5_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER5_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK
3 DEV_TIMER5_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8 Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK
4 DEV_TIMER5_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK
5 DEV_TIMER5_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK
6 DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK
7 DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2 Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK
8 DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3 Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK
9 DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4 Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK
10 DEV_TIMER5_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK
11 DEV_TIMER5_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK
12 DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK
13 DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK
14 DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK
15 DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK
16 DEV_TIMER5_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK
17 DEV_TIMER5_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK
18 DEV_TIMER5_TIMER_PWM Output clock

Clocks for TIMER6 Device

Device: AM64X_DEV_TIMER6 (ID = 42)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER6_TIMER_HCLK_CLK Input clock
1 DEV_TIMER6_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
3 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8 Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
4 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
5 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
6 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
7 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2 Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
8 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3 Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
9 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4 Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
10 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
11 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
12 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
13 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
14 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
15 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
16 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
17 DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK
18 DEV_TIMER6_TIMER_PWM Output clock

Clocks for TIMER7 Device

Device: AM64X_DEV_TIMER7 (ID = 43)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER7_TIMER_HCLK_CLK Input clock
1 DEV_TIMER7_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER7_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK
3 DEV_TIMER7_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8 Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK
4 DEV_TIMER7_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK
5 DEV_TIMER7_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK
6 DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK
7 DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2 Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK
8 DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3 Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK
9 DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4 Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK
10 DEV_TIMER7_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK
11 DEV_TIMER7_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK
12 DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK
13 DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK
14 DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK
15 DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK
16 DEV_TIMER7_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK
17 DEV_TIMER7_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK
18 DEV_TIMER7_TIMER_PWM Output clock

Clocks for TIMER8 Device

Device: AM64X_DEV_TIMER8 (ID = 44)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER8_TIMER_HCLK_CLK Input clock
1 DEV_TIMER8_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
3 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8 Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
4 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
5 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
6 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
7 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2 Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
8 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3 Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
9 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4 Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
10 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
11 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
12 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
13 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
14 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
15 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
16 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
17 DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK
18 DEV_TIMER8_TIMER_PWM Output clock

Clocks for TIMER9 Device

Device: AM64X_DEV_TIMER9 (ID = 45)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMER9_TIMER_HCLK_CLK Input clock
1 DEV_TIMER9_TIMER_TCLK_CLK Input muxed clock
2 DEV_TIMER9_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK
3 DEV_TIMER9_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8 Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK
4 DEV_TIMER9_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0 Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK
5 DEV_TIMER9_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK
6 DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1 Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK
7 DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2 Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK
8 DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3 Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK
9 DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4 Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK
10 DEV_TIMER9_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK
11 DEV_TIMER9_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK
12 DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK
13 DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK
14 DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK
15 DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK
16 DEV_TIMER9_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK
17 DEV_TIMER9_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK
18 DEV_TIMER9_TIMER_PWM Output clock

Clocks for TIMERMGR0 Device

Device: AM64X_DEV_TIMERMGR0 (ID = 151)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMERMGR0_VCLK_CLK Input clock

Clocks for TIMESYNC_EVENT_INTROUTER0 Device

Device: AM64X_DEV_TIMESYNC_EVENT_INTROUTER0 (ID = 6)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_TIMESYNC_EVENT_INTROUTER0_INTR_CLK Input clock

Clocks for UART0 Device

Device: AM64X_DEV_UART0 (ID = 146)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_UART0_FCLK_CLK Input muxed clock
1 DEV_UART0_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT0 Parent input clock option to DEV_UART0_FCLK_CLK
2 DEV_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK Parent input clock option to DEV_UART0_FCLK_CLK
3 DEV_UART0_VBUSP_CLK Input clock

Clocks for UART1 Device

Device: AM64X_DEV_UART1 (ID = 152)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_UART1_FCLK_CLK Input muxed clock
1 DEV_UART1_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT1 Parent input clock option to DEV_UART1_FCLK_CLK
2 DEV_UART1_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK Parent input clock option to DEV_UART1_FCLK_CLK
3 DEV_UART1_VBUSP_CLK Input clock

Clocks for UART2 Device

Device: AM64X_DEV_UART2 (ID = 153)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_UART2_FCLK_CLK Input muxed clock
1 DEV_UART2_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT2 Parent input clock option to DEV_UART2_FCLK_CLK
2 DEV_UART2_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK Parent input clock option to DEV_UART2_FCLK_CLK
3 DEV_UART2_VBUSP_CLK Input clock

Clocks for UART3 Device

Device: AM64X_DEV_UART3 (ID = 154)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_UART3_FCLK_CLK Input muxed clock
1 DEV_UART3_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT3 Parent input clock option to DEV_UART3_FCLK_CLK
2 DEV_UART3_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK Parent input clock option to DEV_UART3_FCLK_CLK
3 DEV_UART3_VBUSP_CLK Input clock

Clocks for UART4 Device

Device: AM64X_DEV_UART4 (ID = 155)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_UART4_FCLK_CLK Input muxed clock
1 DEV_UART4_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT4 Parent input clock option to DEV_UART4_FCLK_CLK
2 DEV_UART4_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK Parent input clock option to DEV_UART4_FCLK_CLK
3 DEV_UART4_VBUSP_CLK Input clock

Clocks for UART5 Device

Device: AM64X_DEV_UART5 (ID = 156)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_UART5_FCLK_CLK Input muxed clock
1 DEV_UART5_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT5 Parent input clock option to DEV_UART5_FCLK_CLK
2 DEV_UART5_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK Parent input clock option to DEV_UART5_FCLK_CLK
3 DEV_UART5_VBUSP_CLK Input clock

Clocks for UART6 Device

Device: AM64X_DEV_UART6 (ID = 158)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_UART6_FCLK_CLK Input muxed clock
1 DEV_UART6_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT6 Parent input clock option to DEV_UART6_FCLK_CLK
2 DEV_UART6_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK Parent input clock option to DEV_UART6_FCLK_CLK
3 DEV_UART6_VBUSP_CLK Input clock

Clocks for USB0 Device

Device: AM64X_DEV_USB0 (ID = 161)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_USB0_ACLK_CLK Input clock
1 DEV_USB0_CLK_LPM_CLK Input clock
2 DEV_USB0_PCLK_CLK Input clock
3 DEV_USB0_PIPE_REFCLK Input clock
4 DEV_USB0_PIPE_RXCLK Input clock
5 DEV_USB0_PIPE_RXFCLK Input clock
6 DEV_USB0_PIPE_TXFCLK Input clock
7 DEV_USB0_PIPE_TXMCLK Input clock
8 DEV_USB0_USB2_APB_PCLK_CLK Input clock
9 DEV_USB0_USB2_REFCLOCK_CLK Input muxed clock
10 DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK
11 DEV_USB0_USB2_REFCLOCK_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK
12 DEV_USB0_PIPE_TXCLK Output clock

Clocks for VTM0 Device

Device: AM64X_DEV_VTM0 (ID = 95)

Following is a mapping of Clocks IDs to function:

Clock ID Name Function
0 DEV_VTM0_FIX_REF2_CLK Input clock
1 DEV_VTM0_FIX_REF_CLK Input clock
2 DEV_VTM0_VBUSP_CLK Input clock