AM65X_SR1 Interrupt Management Device Descriptions¶
Introduction¶
This chapter provides information on the Interrupt Management devices in the AM6 SoC. Some System Firmware TISCI messages take device specific inputs. This chapter provides information on the valid values for Interrupt Management TISCI message parameters.
Interrupt Router Device IDs¶
Some System Firmware TISCI message APIs require the Interrupt Router device ID be provided as part of the request. Based on AM6 Device IDs these are the valid Interrupt Router device IDs.
| Interrupt Router Device Name | Interrupt Router Device ID |
|---|---|
| AM6_DEV_CMPEVENT_INTRTR0 | 3 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 |
| AM6_DEV_NAVSS0_INTR_ROUTER_0 | 182 |
| AM6_DEV_MCU_NAVSS0_INTR_ROUTER_0 | 190 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 |
CMPEVENT_INTRTR0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 0 | Not Connected | ||
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 1 | Not Connected | ||
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 2 | Not Connected | ||
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 3 | Not Connected | ||
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 4 | AM6_DEV_NAVSS0 | cpts0_comp | 0 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 5 | AM6_DEV_PCIE0 | pcie_cpts_comp | 0 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 6 | AM6_DEV_PCIE1 | pcie_cpts_comp | 0 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 7 | AM6_DEV_MCU_CPSW0 | cpts_comp | 0 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 8 | AM6_DEV_PRU_ICSSG0 | pr1_host_intr_req | 0 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 9 | AM6_DEV_PRU_ICSSG0 | pr1_host_intr_req | 1 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 10 | AM6_DEV_PRU_ICSSG0 | pr1_host_intr_req | 2 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 11 | AM6_DEV_PRU_ICSSG0 | pr1_host_intr_req | 3 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 12 | AM6_DEV_PRU_ICSSG0 | pr1_host_intr_req | 4 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 13 | AM6_DEV_PRU_ICSSG0 | pr1_host_intr_req | 5 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 14 | AM6_DEV_PRU_ICSSG0 | pr1_host_intr_req | 6 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 15 | AM6_DEV_PRU_ICSSG0 | pr1_host_intr_req | 7 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 16 | AM6_DEV_PRU_ICSSG1 | pr1_host_intr_req | 0 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 17 | AM6_DEV_PRU_ICSSG1 | pr1_host_intr_req | 1 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 18 | AM6_DEV_PRU_ICSSG1 | pr1_host_intr_req | 2 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 19 | AM6_DEV_PRU_ICSSG1 | pr1_host_intr_req | 3 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 20 | AM6_DEV_PRU_ICSSG1 | pr1_host_intr_req | 4 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 21 | AM6_DEV_PRU_ICSSG1 | pr1_host_intr_req | 5 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 22 | AM6_DEV_PRU_ICSSG1 | pr1_host_intr_req | 6 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 23 | AM6_DEV_PRU_ICSSG1 | pr1_host_intr_req | 7 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 24 | AM6_DEV_PRU_ICSSG2 | pr1_host_intr_req | 0 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 25 | AM6_DEV_PRU_ICSSG2 | pr1_host_intr_req | 1 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 26 | AM6_DEV_PRU_ICSSG2 | pr1_host_intr_req | 2 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 27 | AM6_DEV_PRU_ICSSG2 | pr1_host_intr_req | 3 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 28 | AM6_DEV_PRU_ICSSG2 | pr1_host_intr_req | 4 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 29 | AM6_DEV_PRU_ICSSG2 | pr1_host_intr_req | 5 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 30 | AM6_DEV_PRU_ICSSG2 | pr1_host_intr_req | 6 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 31 | AM6_DEV_PRU_ICSSG2 | pr1_host_intr_req | 7 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 32 | AM6_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 0 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 33 | AM6_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 1 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 34 | AM6_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 2 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 35 | AM6_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 3 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 36 | AM6_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 4 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 37 | AM6_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 5 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 38 | AM6_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 6 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 39 | AM6_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 7 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 40 | AM6_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 8 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 41 | AM6_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 9 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 42 | AM6_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 10 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 43 | AM6_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 11 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 44 | AM6_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 12 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 45 | AM6_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 13 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 46 | AM6_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 14 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 47 | AM6_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 15 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 48 | AM6_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 0 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 49 | AM6_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 1 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 50 | AM6_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 2 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 51 | AM6_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 3 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 52 | AM6_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 4 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 53 | AM6_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 5 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 54 | AM6_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 6 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 55 | AM6_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 7 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 56 | AM6_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 8 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 57 | AM6_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 9 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 58 | AM6_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 10 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 59 | AM6_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 11 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 60 | AM6_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 12 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 61 | AM6_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 13 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 62 | AM6_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 14 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 63 | AM6_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 15 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 64 | AM6_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 0 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 65 | AM6_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 1 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 66 | AM6_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 2 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 67 | AM6_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 3 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 68 | AM6_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 4 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 69 | AM6_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 5 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 70 | AM6_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 6 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 71 | AM6_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 7 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 72 | AM6_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 8 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 73 | AM6_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 9 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 74 | AM6_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 10 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 75 | AM6_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 11 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 76 | AM6_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 12 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 77 | AM6_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 13 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 78 | AM6_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 14 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 79 | AM6_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 15 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 80 | AM6_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 0 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 81 | AM6_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 1 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 82 | AM6_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 2 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 83 | AM6_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 3 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 84 | AM6_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 4 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 85 | AM6_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 5 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 86 | AM6_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 6 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 87 | AM6_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 7 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 88 | AM6_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 8 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 89 | AM6_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 9 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 90 | AM6_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 10 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 91 | AM6_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 11 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 92 | AM6_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 12 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 93 | AM6_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 13 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 94 | AM6_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 14 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 95 | AM6_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 15 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 96 | AM6_DEV_PRU_ICSSG2 | pr1_iep0_cmp_intr_req | 0 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 97 | AM6_DEV_PRU_ICSSG2 | pr1_iep0_cmp_intr_req | 1 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 98 | AM6_DEV_PRU_ICSSG2 | pr1_iep0_cmp_intr_req | 2 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 99 | AM6_DEV_PRU_ICSSG2 | pr1_iep0_cmp_intr_req | 3 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 100 | AM6_DEV_PRU_ICSSG2 | pr1_iep0_cmp_intr_req | 4 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 101 | AM6_DEV_PRU_ICSSG2 | pr1_iep0_cmp_intr_req | 5 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 102 | AM6_DEV_PRU_ICSSG2 | pr1_iep0_cmp_intr_req | 6 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 103 | AM6_DEV_PRU_ICSSG2 | pr1_iep0_cmp_intr_req | 7 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 104 | AM6_DEV_PRU_ICSSG2 | pr1_iep0_cmp_intr_req | 8 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 105 | AM6_DEV_PRU_ICSSG2 | pr1_iep0_cmp_intr_req | 9 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 106 | AM6_DEV_PRU_ICSSG2 | pr1_iep0_cmp_intr_req | 10 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 107 | AM6_DEV_PRU_ICSSG2 | pr1_iep0_cmp_intr_req | 11 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 108 | AM6_DEV_PRU_ICSSG2 | pr1_iep0_cmp_intr_req | 12 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 109 | AM6_DEV_PRU_ICSSG2 | pr1_iep0_cmp_intr_req | 13 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 110 | AM6_DEV_PRU_ICSSG2 | pr1_iep0_cmp_intr_req | 14 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 111 | AM6_DEV_PRU_ICSSG2 | pr1_iep0_cmp_intr_req | 15 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 112 | AM6_DEV_PRU_ICSSG2 | pr1_iep1_cmp_intr_req | 0 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 113 | AM6_DEV_PRU_ICSSG2 | pr1_iep1_cmp_intr_req | 1 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 114 | AM6_DEV_PRU_ICSSG2 | pr1_iep1_cmp_intr_req | 2 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 115 | AM6_DEV_PRU_ICSSG2 | pr1_iep1_cmp_intr_req | 3 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 116 | AM6_DEV_PRU_ICSSG2 | pr1_iep1_cmp_intr_req | 4 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 117 | AM6_DEV_PRU_ICSSG2 | pr1_iep1_cmp_intr_req | 5 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 118 | AM6_DEV_PRU_ICSSG2 | pr1_iep1_cmp_intr_req | 6 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 119 | AM6_DEV_PRU_ICSSG2 | pr1_iep1_cmp_intr_req | 7 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 120 | AM6_DEV_PRU_ICSSG2 | pr1_iep1_cmp_intr_req | 8 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 121 | AM6_DEV_PRU_ICSSG2 | pr1_iep1_cmp_intr_req | 9 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 122 | AM6_DEV_PRU_ICSSG2 | pr1_iep1_cmp_intr_req | 10 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 123 | AM6_DEV_PRU_ICSSG2 | pr1_iep1_cmp_intr_req | 11 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 124 | AM6_DEV_PRU_ICSSG2 | pr1_iep1_cmp_intr_req | 12 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 125 | AM6_DEV_PRU_ICSSG2 | pr1_iep1_cmp_intr_req | 13 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 126 | AM6_DEV_PRU_ICSSG2 | pr1_iep1_cmp_intr_req | 14 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 127 | AM6_DEV_PRU_ICSSG2 | pr1_iep1_cmp_intr_req | 15 |
CMPEVENT_INTRTR0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 0 | AM6_DEV_GIC0 | spi | 544 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 1 | AM6_DEV_GIC0 | spi | 545 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 2 | AM6_DEV_GIC0 | spi | 546 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 3 | AM6_DEV_GIC0 | spi | 547 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 4 | AM6_DEV_GIC0 | spi | 548 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 5 | AM6_DEV_GIC0 | spi | 549 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 6 | AM6_DEV_GIC0 | spi | 550 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 7 | AM6_DEV_GIC0 | spi | 551 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 8 | AM6_DEV_GIC0 | spi | 552 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 9 | AM6_DEV_GIC0 | spi | 553 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 10 | AM6_DEV_GIC0 | spi | 554 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 11 | AM6_DEV_GIC0 | spi | 555 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 12 | AM6_DEV_GIC0 | spi | 556 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 13 | AM6_DEV_GIC0 | spi | 557 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 14 | AM6_DEV_GIC0 | spi | 558 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 15 | AM6_DEV_GIC0 | spi | 559 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 16 | Not Connected | ||
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 17 | Not Connected | ||
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 18 | Not Connected | ||
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 19 | Not Connected | ||
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 20 | Not Connected | ||
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 21 | Not Connected | ||
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 22 | Not Connected | ||
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 23 | Not Connected | ||
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 24 | AM6_DEV_PDMA1 | levent_in | 8 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 25 | AM6_DEV_PDMA1 | levent_in | 9 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 26 | AM6_DEV_PDMA1 | levent_in | 10 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 27 | AM6_DEV_PDMA1 | levent_in | 11 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 28 | AM6_DEV_PDMA1 | levent_in | 12 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 29 | AM6_DEV_PDMA1 | levent_in | 13 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 30 | AM6_DEV_PDMA1 | levent_in | 14 |
| AM6_DEV_CMPEVENT_INTRTR0 | 3 | 31 | AM6_DEV_PDMA1 | levent_in | 15 |
MAIN2MCU_LVL_INTRTR0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 0 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 1 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 2 | AM6_DEV_DSS0 | dispc_intr_req_0 | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 3 | AM6_DEV_DSS0 | dispc_intr_req_1 | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 4 | AM6_DEV_SA2_UL0 | sa_ul_trng | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 5 | AM6_DEV_SA2_UL0 | sa_ul_pka | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 6 | AM6_DEV_CTRL_MMR0 | access_err | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 7 | AM6_DEV_ELM0 | elm_porocpsinterrupt_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 8 | AM6_DEV_GPMC0 | gpmc_sinterrupt | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 9 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 10 | AM6_DEV_DDRSS0 | ddrss_v2h_other_err_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 11 | AM6_DEV_CAL0 | int_cal_l | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 12 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 13 | AM6_DEV_CCDEBUGSS0 | aqcmpintr_level | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 14 | AM6_DEV_DEBUGSS0 | aqcmpintr_level | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 15 | AM6_DEV_DEBUGSS0 | ctm_level | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 16 | AM6_DEV_MCASP0 | xmit_intr_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 17 | AM6_DEV_MCASP0 | rec_intr_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 18 | AM6_DEV_MCASP1 | xmit_intr_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 19 | AM6_DEV_MCASP1 | rec_intr_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 20 | AM6_DEV_MCASP2 | xmit_intr_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 21 | AM6_DEV_MCASP2 | rec_intr_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 22 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 23 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 24 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 25 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 26 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 27 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 28 | AM6_DEV_MMCSD1 | emmcsdss_intr | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 29 | AM6_DEV_MMCSD0 | emmcsdss_intr | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 30 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 31 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 32 | AM6_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 33 | AM6_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 1 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 34 | AM6_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 2 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 35 | AM6_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 3 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 36 | AM6_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 4 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 37 | AM6_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 5 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 38 | AM6_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 6 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 39 | AM6_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 7 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 40 | AM6_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 41 | AM6_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 1 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 42 | AM6_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 2 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 43 | AM6_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 3 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 44 | AM6_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 4 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 45 | AM6_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 5 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 46 | AM6_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 6 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 47 | AM6_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 7 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 48 | AM6_DEV_PRU_ICSSG2 | pr1_host_intr_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 49 | AM6_DEV_PRU_ICSSG2 | pr1_host_intr_pend | 1 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 50 | AM6_DEV_PRU_ICSSG2 | pr1_host_intr_pend | 2 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 51 | AM6_DEV_PRU_ICSSG2 | pr1_host_intr_pend | 3 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 52 | AM6_DEV_PRU_ICSSG2 | pr1_host_intr_pend | 4 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 53 | AM6_DEV_PRU_ICSSG2 | pr1_host_intr_pend | 5 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 54 | AM6_DEV_PRU_ICSSG2 | pr1_host_intr_pend | 6 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 55 | AM6_DEV_PRU_ICSSG2 | pr1_host_intr_pend | 7 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 56 | AM6_DEV_GPU0 | gpu_irq | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 57 | AM6_DEV_GPU0 | exp_intr | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 58 | AM6_DEV_GPU0 | init_err | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 59 | AM6_DEV_GPU0 | target_err | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 60 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 61 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 62 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 63 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 64 | AM6_DEV_PCIE0 | pcie0_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 65 | AM6_DEV_PCIE0 | pcie1_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 66 | AM6_DEV_PCIE0 | pcie2_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 67 | AM6_DEV_PCIE0 | pcie3_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 68 | AM6_DEV_PCIE0 | pcie4_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 69 | AM6_DEV_PCIE0 | pcie5_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 70 | AM6_DEV_PCIE0 | pcie6_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 71 | AM6_DEV_PCIE0 | pcie7_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 72 | AM6_DEV_PCIE0 | pcie8_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 73 | AM6_DEV_PCIE0 | pcie9_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 74 | AM6_DEV_PCIE0 | pcie10_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 75 | AM6_DEV_PCIE0 | pcie11_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 76 | AM6_DEV_PCIE0 | pcie12_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 77 | AM6_DEV_PCIE0 | pcie13_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 78 | AM6_DEV_PCIE0 | pcie14_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 79 | AM6_DEV_PCIE0 | pcie_cpts_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 80 | AM6_DEV_PCIE1 | pcie0_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 81 | AM6_DEV_PCIE1 | pcie1_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 82 | AM6_DEV_PCIE1 | pcie2_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 83 | AM6_DEV_PCIE1 | pcie3_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 84 | AM6_DEV_PCIE1 | pcie4_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 85 | AM6_DEV_PCIE1 | pcie5_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 86 | AM6_DEV_PCIE1 | pcie6_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 87 | AM6_DEV_PCIE1 | pcie7_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 88 | AM6_DEV_PCIE1 | pcie8_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 89 | AM6_DEV_PCIE1 | pcie9_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 90 | AM6_DEV_PCIE1 | pcie10_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 91 | AM6_DEV_PCIE1 | pcie11_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 92 | AM6_DEV_PCIE1 | pcie12_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 93 | AM6_DEV_PCIE1 | pcie13_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 94 | AM6_DEV_PCIE1 | pcie14_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 95 | AM6_DEV_PCIE1 | pcie_cpts_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 96 | AM6_DEV_MCSPI0 | intr_spi | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 97 | AM6_DEV_MCSPI1 | intr_spi | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 98 | AM6_DEV_MCSPI2 | intr_spi | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 99 | AM6_DEV_MCSPI3 | intr_spi | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 100 | AM6_DEV_I2C0 | pointrpend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 101 | AM6_DEV_I2C1 | pointrpend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 102 | AM6_DEV_I2C2 | pointrpend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 103 | AM6_DEV_I2C3 | pointrpend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 104 | AM6_DEV_UART0 | usart_irq | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 105 | AM6_DEV_UART1 | usart_irq | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 106 | AM6_DEV_UART2 | usart_irq | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 107 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 108 | AM6_DEV_TIMER0 | intr_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 109 | AM6_DEV_TIMER1 | intr_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 110 | AM6_DEV_TIMER2 | intr_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 111 | AM6_DEV_TIMER3 | intr_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 112 | AM6_DEV_TIMER4 | intr_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 113 | AM6_DEV_TIMER5 | intr_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 114 | AM6_DEV_TIMER6 | intr_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 115 | AM6_DEV_TIMER7 | intr_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 116 | AM6_DEV_TIMER8 | intr_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 117 | AM6_DEV_TIMER9 | intr_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 118 | AM6_DEV_TIMER10 | intr_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 119 | AM6_DEV_TIMER11 | intr_pend | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 120 | AM6_DEV_DCC0 | intr_done_level | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 121 | AM6_DEV_DCC1 | intr_done_level | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 122 | AM6_DEV_DCC2 | intr_done_level | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 123 | AM6_DEV_DCC3 | intr_done_level | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 124 | AM6_DEV_DCC4 | intr_done_level | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 125 | AM6_DEV_DCC5 | intr_done_level | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 126 | AM6_DEV_DCC6 | intr_done_level | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 127 | AM6_DEV_DCC7 | intr_done_level | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 128 | AM6_DEV_USB3SS0 | otg_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 129 | AM6_DEV_USB3SS0 | misc_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 130 | AM6_DEV_USB3SS0 | bc_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 131 | AM6_DEV_USB3SS0 | pme_gen_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 132 | AM6_DEV_USB3SS0 | i00_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 133 | AM6_DEV_USB3SS0 | i01_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 134 | AM6_DEV_USB3SS0 | i02_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 135 | AM6_DEV_USB3SS0 | i03_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 136 | AM6_DEV_USB3SS0 | i04_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 137 | AM6_DEV_USB3SS0 | i05_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 138 | AM6_DEV_USB3SS0 | i06_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 139 | AM6_DEV_USB3SS0 | i07_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 140 | AM6_DEV_USB3SS0 | i08_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 141 | AM6_DEV_USB3SS0 | i09_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 142 | AM6_DEV_USB3SS0 | i10_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 143 | AM6_DEV_USB3SS0 | i11_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 144 | AM6_DEV_USB3SS0 | i12_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 145 | AM6_DEV_USB3SS0 | i13_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 146 | AM6_DEV_USB3SS0 | i14_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 147 | AM6_DEV_USB3SS0 | i15_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 148 | AM6_DEV_USB3SS1 | otg_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 149 | AM6_DEV_USB3SS1 | misc_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 150 | AM6_DEV_USB3SS1 | bc_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 151 | AM6_DEV_USB3SS1 | pme_gen_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 152 | AM6_DEV_USB3SS1 | i00_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 153 | AM6_DEV_USB3SS1 | i01_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 154 | AM6_DEV_USB3SS1 | i02_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 155 | AM6_DEV_USB3SS1 | i03_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 156 | AM6_DEV_USB3SS1 | i04_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 157 | AM6_DEV_USB3SS1 | i05_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 158 | AM6_DEV_USB3SS1 | i06_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 159 | AM6_DEV_USB3SS1 | i07_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 160 | AM6_DEV_USB3SS1 | i08_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 161 | AM6_DEV_USB3SS1 | i09_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 162 | AM6_DEV_USB3SS1 | i10_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 163 | AM6_DEV_USB3SS1 | i11_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 164 | AM6_DEV_USB3SS1 | i12_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 165 | AM6_DEV_USB3SS1 | i13_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 166 | AM6_DEV_USB3SS1 | i14_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 167 | AM6_DEV_USB3SS1 | i15_lvl | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 168 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 169 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 170 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 171 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 172 | AM6_DEV_CBASS0 | LPSC_per_common_err_intr | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 173 | AM6_DEV_CBASS_DEBUG0 | LPSC_main_debug_err_intr | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 174 | AM6_DEV_CBASS_FW0 | LPSC_main_infra_err_intr | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 175 | AM6_DEV_CBASS_INFRA0 | LPSC_main_infra_err_intr | 0 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 176 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 177 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 178 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 179 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 180 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 181 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 182 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 183 | Not Connected | ||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 184 | AM6_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 120 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 185 | AM6_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 121 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 186 | AM6_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 122 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 187 | AM6_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 123 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 188 | AM6_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 124 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 189 | AM6_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 125 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 190 | AM6_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 126 |
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 191 | AM6_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 127 |
MAIN2MCU_LVL_INTRTR0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 0 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 160 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 160 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 1 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 161 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 161 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 2 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 162 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 162 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 3 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 163 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 163 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 4 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 164 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 164 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 5 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 165 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 165 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 6 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 166 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 166 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 7 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 167 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 167 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 8 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 168 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 168 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 9 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 169 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 169 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 10 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 170 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 170 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 11 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 171 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 171 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 12 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 172 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 172 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 13 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 173 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 173 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 14 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 174 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 174 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 15 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 175 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 175 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 16 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 176 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 176 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 17 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 177 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 177 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 18 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 178 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 178 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 19 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 179 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 179 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 20 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 180 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 180 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 21 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 181 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 181 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 22 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 182 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 182 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 23 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 183 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 183 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 24 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 184 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 184 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 25 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 185 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 185 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 26 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 186 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 186 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 27 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 187 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 187 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 28 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 188 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 188 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 29 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 189 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 189 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 30 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 190 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 190 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 31 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 191 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 191 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 32 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 192 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 192 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 33 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 193 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 193 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 34 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 194 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 194 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 35 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 195 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 195 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 36 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 196 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 196 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 37 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 197 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 197 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 38 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 198 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 198 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 39 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 199 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 199 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 40 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 200 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 200 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 41 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 201 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 201 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 42 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 202 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 202 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 43 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 203 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 203 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 44 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 204 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 204 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 45 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 205 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 205 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 46 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 206 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 206 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 47 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 207 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 207 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 48 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 208 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 208 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 49 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 209 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 209 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 50 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 210 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 210 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 51 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 211 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 211 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 52 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 212 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 212 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 53 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 213 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 213 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 54 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 214 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 214 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 55 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 215 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 215 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 56 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 216 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 216 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 57 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 217 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 217 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 58 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 218 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 218 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 59 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 219 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 219 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 60 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 220 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 220 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 61 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 221 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 221 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 62 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 222 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 222 | |||
| AM6_DEV_MAIN2MCU_LVL_INTRTR0 | 97 | 63 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 223 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 223 |
MAIN2MCU_PLS_INTRTR0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 0 | Not Connected | ||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 1 | Not Connected | ||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 2 | AM6_DEV_EHRPWM0 | epwm_etint | 0 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 3 | AM6_DEV_EHRPWM1 | epwm_etint | 0 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 4 | AM6_DEV_EHRPWM2 | epwm_etint | 0 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 5 | AM6_DEV_EHRPWM3 | epwm_etint | 0 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 6 | AM6_DEV_EHRPWM4 | epwm_etint | 0 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 7 | AM6_DEV_EHRPWM5 | epwm_etint | 0 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 8 | AM6_DEV_EHRPWM0 | epwm_tripzint | 0 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 9 | AM6_DEV_EHRPWM1 | epwm_tripzint | 0 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 10 | AM6_DEV_EHRPWM2 | epwm_tripzint | 0 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 11 | AM6_DEV_EHRPWM3 | epwm_tripzint | 0 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 12 | AM6_DEV_EHRPWM4 | epwm_tripzint | 0 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 13 | AM6_DEV_EHRPWM5 | epwm_tripzint | 0 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 14 | AM6_DEV_EQEP0 | eqep_int | 0 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 15 | AM6_DEV_EQEP1 | eqep_int | 0 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 16 | AM6_DEV_EQEP2 | eqep_int | 0 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 17 | AM6_DEV_ECAP0 | ecap_int | 0 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 18 | Not Connected | ||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 19 | Not Connected | ||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 20 | AM6_DEV_PRU_ICSSG0 | pr1_rx_sof_intr_req | 0 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 21 | AM6_DEV_PRU_ICSSG0 | pr1_rx_sof_intr_req | 1 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 22 | AM6_DEV_PRU_ICSSG0 | pr1_tx_sof_intr_req | 0 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 23 | AM6_DEV_PRU_ICSSG0 | pr1_tx_sof_intr_req | 1 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 24 | AM6_DEV_PRU_ICSSG1 | pr1_rx_sof_intr_req | 0 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 25 | AM6_DEV_PRU_ICSSG1 | pr1_rx_sof_intr_req | 1 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 26 | AM6_DEV_PRU_ICSSG1 | pr1_tx_sof_intr_req | 0 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 27 | AM6_DEV_PRU_ICSSG1 | pr1_tx_sof_intr_req | 1 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 28 | AM6_DEV_PRU_ICSSG2 | pr1_rx_sof_intr_req | 0 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 29 | AM6_DEV_PRU_ICSSG2 | pr1_rx_sof_intr_req | 1 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 30 | AM6_DEV_PRU_ICSSG2 | pr1_tx_sof_intr_req | 0 |
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 31 | AM6_DEV_PRU_ICSSG2 | pr1_tx_sof_intr_req | 1 |
MAIN2MCU_PLS_INTRTR0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 0 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 224 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 224 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 1 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 225 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 225 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 2 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 226 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 226 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 3 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 227 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 227 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 4 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 228 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 228 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 5 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 229 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 229 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 6 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 230 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 230 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 7 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 231 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 231 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 8 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 232 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 232 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 9 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 233 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 233 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 10 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 234 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 234 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 11 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 235 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 235 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 12 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 236 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 236 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 13 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 237 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 237 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 14 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 238 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 238 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 15 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 239 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 239 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 16 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 240 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 240 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 17 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 241 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 241 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 18 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 242 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 242 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 19 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 243 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 243 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 20 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 244 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 244 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 21 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 245 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 245 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 22 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 246 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 246 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 23 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 247 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 247 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 24 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 248 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 248 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 25 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 249 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 249 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 26 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 250 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 250 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 27 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 251 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 251 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 28 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 252 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 252 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 29 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 253 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 253 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 30 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 254 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 254 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 31 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 255 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 255 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 32 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 256 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 256 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 33 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 257 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 257 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 34 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 258 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 258 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 35 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 259 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 259 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 36 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 260 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 260 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 37 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 261 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 261 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 38 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 262 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 262 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 39 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 263 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 263 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 40 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 264 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 264 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 41 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 265 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 265 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 42 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 266 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 266 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 43 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 267 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 267 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 44 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 268 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 268 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 45 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 269 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 269 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 46 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 270 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 270 | |||
| AM6_DEV_MAIN2MCU_PLS_INTRTR0 | 98 | 47 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 271 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 271 |
GPIOMUX_INTRTR0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 0 | AM6_DEV_GPIO0 | gpio | 0 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 1 | AM6_DEV_GPIO0 | gpio | 1 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 2 | AM6_DEV_GPIO0 | gpio | 2 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 3 | AM6_DEV_GPIO0 | gpio | 3 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 4 | AM6_DEV_GPIO0 | gpio | 4 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 5 | AM6_DEV_GPIO0 | gpio | 5 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 6 | AM6_DEV_GPIO0 | gpio | 6 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 7 | AM6_DEV_GPIO0 | gpio | 7 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 8 | AM6_DEV_GPIO0 | gpio | 8 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 9 | AM6_DEV_GPIO0 | gpio | 9 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 10 | AM6_DEV_GPIO0 | gpio | 10 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 11 | AM6_DEV_GPIO0 | gpio | 11 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 12 | AM6_DEV_GPIO0 | gpio | 12 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 13 | AM6_DEV_GPIO0 | gpio | 13 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 14 | AM6_DEV_GPIO0 | gpio | 14 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 15 | AM6_DEV_GPIO0 | gpio | 15 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 16 | AM6_DEV_GPIO0 | gpio | 16 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 17 | AM6_DEV_GPIO0 | gpio | 17 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 18 | AM6_DEV_GPIO0 | gpio | 18 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 19 | AM6_DEV_GPIO0 | gpio | 19 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 20 | AM6_DEV_GPIO0 | gpio | 20 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 21 | AM6_DEV_GPIO0 | gpio | 21 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 22 | AM6_DEV_GPIO0 | gpio | 22 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 23 | AM6_DEV_GPIO0 | gpio | 23 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 24 | AM6_DEV_GPIO0 | gpio | 24 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 25 | AM6_DEV_GPIO0 | gpio | 25 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 26 | AM6_DEV_GPIO0 | gpio | 26 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 27 | AM6_DEV_GPIO0 | gpio | 27 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 28 | AM6_DEV_GPIO0 | gpio | 28 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 29 | AM6_DEV_GPIO0 | gpio | 29 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 30 | AM6_DEV_GPIO0 | gpio | 30 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 31 | AM6_DEV_GPIO0 | gpio | 31 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 32 | AM6_DEV_GPIO0 | gpio | 32 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 33 | AM6_DEV_GPIO0 | gpio | 33 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 34 | AM6_DEV_GPIO0 | gpio | 34 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 35 | AM6_DEV_GPIO0 | gpio | 35 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 36 | AM6_DEV_GPIO0 | gpio | 36 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 37 | AM6_DEV_GPIO0 | gpio | 37 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 38 | AM6_DEV_GPIO0 | gpio | 38 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 39 | AM6_DEV_GPIO0 | gpio | 39 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 40 | AM6_DEV_GPIO0 | gpio | 40 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 41 | AM6_DEV_GPIO0 | gpio | 41 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 42 | AM6_DEV_GPIO0 | gpio | 42 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 43 | AM6_DEV_GPIO0 | gpio | 43 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 44 | AM6_DEV_GPIO0 | gpio | 44 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 45 | AM6_DEV_GPIO0 | gpio | 45 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 46 | AM6_DEV_GPIO0 | gpio | 46 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 47 | AM6_DEV_GPIO0 | gpio | 47 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 48 | AM6_DEV_GPIO0 | gpio | 48 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 49 | AM6_DEV_GPIO0 | gpio | 49 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 50 | AM6_DEV_GPIO0 | gpio | 50 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 51 | AM6_DEV_GPIO0 | gpio | 51 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 52 | AM6_DEV_GPIO0 | gpio | 52 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 53 | AM6_DEV_GPIO0 | gpio | 53 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 54 | AM6_DEV_GPIO0 | gpio | 54 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 55 | AM6_DEV_GPIO0 | gpio | 55 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 56 | AM6_DEV_GPIO0 | gpio | 56 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 57 | AM6_DEV_GPIO0 | gpio | 57 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 58 | AM6_DEV_GPIO0 | gpio | 58 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 59 | AM6_DEV_GPIO0 | gpio | 59 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 60 | AM6_DEV_GPIO0 | gpio | 60 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 61 | AM6_DEV_GPIO0 | gpio | 61 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 62 | AM6_DEV_GPIO0 | gpio | 62 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 63 | AM6_DEV_GPIO0 | gpio | 63 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 64 | AM6_DEV_GPIO0 | gpio | 64 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 65 | AM6_DEV_GPIO0 | gpio | 65 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 66 | AM6_DEV_GPIO0 | gpio | 66 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 67 | AM6_DEV_GPIO0 | gpio | 67 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 68 | AM6_DEV_GPIO0 | gpio | 68 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 69 | AM6_DEV_GPIO0 | gpio | 69 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 70 | AM6_DEV_GPIO0 | gpio | 70 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 71 | AM6_DEV_GPIO0 | gpio | 71 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 72 | AM6_DEV_GPIO0 | gpio | 72 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 73 | AM6_DEV_GPIO0 | gpio | 73 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 74 | AM6_DEV_GPIO0 | gpio | 74 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 75 | AM6_DEV_GPIO0 | gpio | 75 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 76 | AM6_DEV_GPIO0 | gpio | 76 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 77 | AM6_DEV_GPIO0 | gpio | 77 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 78 | AM6_DEV_GPIO0 | gpio | 78 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 79 | AM6_DEV_GPIO0 | gpio | 79 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 80 | AM6_DEV_GPIO0 | gpio | 80 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 81 | AM6_DEV_GPIO0 | gpio | 81 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 82 | AM6_DEV_GPIO0 | gpio | 82 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 83 | AM6_DEV_GPIO0 | gpio | 83 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 84 | AM6_DEV_GPIO0 | gpio | 84 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 85 | AM6_DEV_GPIO0 | gpio | 85 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 86 | AM6_DEV_GPIO0 | gpio | 86 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 87 | AM6_DEV_GPIO0 | gpio | 87 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 88 | AM6_DEV_GPIO0 | gpio | 88 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 89 | AM6_DEV_GPIO0 | gpio | 89 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 90 | AM6_DEV_GPIO0 | gpio | 90 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 91 | AM6_DEV_GPIO0 | gpio | 91 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 92 | AM6_DEV_GPIO0 | gpio | 92 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 93 | AM6_DEV_GPIO0 | gpio | 93 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 94 | AM6_DEV_GPIO0 | gpio | 94 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 95 | AM6_DEV_GPIO0 | gpio | 95 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 96 | AM6_DEV_GPIO1 | gpio | 0 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 97 | AM6_DEV_GPIO1 | gpio | 1 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 98 | AM6_DEV_GPIO1 | gpio | 2 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 99 | AM6_DEV_GPIO1 | gpio | 3 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 100 | AM6_DEV_GPIO1 | gpio | 4 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 101 | AM6_DEV_GPIO1 | gpio | 5 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 102 | AM6_DEV_GPIO1 | gpio | 6 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 103 | AM6_DEV_GPIO1 | gpio | 7 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 104 | AM6_DEV_GPIO1 | gpio | 8 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 105 | AM6_DEV_GPIO1 | gpio | 9 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 106 | AM6_DEV_GPIO1 | gpio | 10 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 107 | AM6_DEV_GPIO1 | gpio | 11 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 108 | AM6_DEV_GPIO1 | gpio | 12 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 109 | AM6_DEV_GPIO1 | gpio | 13 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 110 | AM6_DEV_GPIO1 | gpio | 14 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 111 | AM6_DEV_GPIO1 | gpio | 15 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 112 | AM6_DEV_GPIO1 | gpio | 16 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 113 | AM6_DEV_GPIO1 | gpio | 17 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 114 | AM6_DEV_GPIO1 | gpio | 18 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 115 | AM6_DEV_GPIO1 | gpio | 19 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 116 | AM6_DEV_GPIO1 | gpio | 20 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 117 | AM6_DEV_GPIO1 | gpio | 21 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 118 | AM6_DEV_GPIO1 | gpio | 22 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 119 | AM6_DEV_GPIO1 | gpio | 23 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 120 | AM6_DEV_GPIO1 | gpio | 24 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 121 | AM6_DEV_GPIO1 | gpio | 25 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 122 | AM6_DEV_GPIO1 | gpio | 26 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 123 | AM6_DEV_GPIO1 | gpio | 27 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 124 | AM6_DEV_GPIO1 | gpio | 28 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 125 | AM6_DEV_GPIO1 | gpio | 29 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 126 | AM6_DEV_GPIO1 | gpio | 30 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 127 | AM6_DEV_GPIO1 | gpio | 31 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 128 | AM6_DEV_GPIO1 | gpio | 32 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 129 | AM6_DEV_GPIO1 | gpio | 33 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 130 | AM6_DEV_GPIO1 | gpio | 34 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 131 | AM6_DEV_GPIO1 | gpio | 35 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 132 | AM6_DEV_GPIO1 | gpio | 36 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 133 | AM6_DEV_GPIO1 | gpio | 37 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 134 | AM6_DEV_GPIO1 | gpio | 38 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 135 | AM6_DEV_GPIO1 | gpio | 39 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 136 | AM6_DEV_GPIO1 | gpio | 40 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 137 | AM6_DEV_GPIO1 | gpio | 41 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 138 | AM6_DEV_GPIO1 | gpio | 42 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 139 | AM6_DEV_GPIO1 | gpio | 43 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 140 | AM6_DEV_GPIO1 | gpio | 44 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 141 | AM6_DEV_GPIO1 | gpio | 45 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 142 | AM6_DEV_GPIO1 | gpio | 46 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 143 | AM6_DEV_GPIO1 | gpio | 47 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 144 | AM6_DEV_GPIO1 | gpio | 48 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 145 | AM6_DEV_GPIO1 | gpio | 49 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 146 | AM6_DEV_GPIO1 | gpio | 50 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 147 | AM6_DEV_GPIO1 | gpio | 51 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 148 | AM6_DEV_GPIO1 | gpio | 52 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 149 | AM6_DEV_GPIO1 | gpio | 53 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 150 | AM6_DEV_GPIO1 | gpio | 54 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 151 | AM6_DEV_GPIO1 | gpio | 55 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 152 | AM6_DEV_GPIO1 | gpio | 56 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 153 | AM6_DEV_GPIO1 | gpio | 57 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 154 | AM6_DEV_GPIO1 | gpio | 58 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 155 | AM6_DEV_GPIO1 | gpio | 59 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 156 | AM6_DEV_GPIO1 | gpio | 60 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 157 | AM6_DEV_GPIO1 | gpio | 61 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 158 | AM6_DEV_GPIO1 | gpio | 62 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 159 | AM6_DEV_GPIO1 | gpio | 63 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 160 | AM6_DEV_GPIO1 | gpio | 64 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 161 | AM6_DEV_GPIO1 | gpio | 65 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 162 | AM6_DEV_GPIO1 | gpio | 66 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 163 | AM6_DEV_GPIO1 | gpio | 67 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 164 | AM6_DEV_GPIO1 | gpio | 68 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 165 | AM6_DEV_GPIO1 | gpio | 69 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 166 | AM6_DEV_GPIO1 | gpio | 70 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 167 | AM6_DEV_GPIO1 | gpio | 71 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 168 | AM6_DEV_GPIO1 | gpio | 72 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 169 | AM6_DEV_GPIO1 | gpio | 73 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 170 | AM6_DEV_GPIO1 | gpio | 74 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 171 | AM6_DEV_GPIO1 | gpio | 75 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 172 | AM6_DEV_GPIO1 | gpio | 76 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 173 | AM6_DEV_GPIO1 | gpio | 77 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 174 | AM6_DEV_GPIO1 | gpio | 78 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 175 | AM6_DEV_GPIO1 | gpio | 79 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 176 | AM6_DEV_GPIO1 | gpio | 80 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 177 | AM6_DEV_GPIO1 | gpio | 81 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 178 | AM6_DEV_GPIO1 | gpio | 82 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 179 | AM6_DEV_GPIO1 | gpio | 83 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 180 | AM6_DEV_GPIO1 | gpio | 84 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 181 | AM6_DEV_GPIO1 | gpio | 85 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 182 | AM6_DEV_GPIO1 | gpio | 86 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 183 | AM6_DEV_GPIO1 | gpio | 87 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 184 | AM6_DEV_GPIO1 | gpio | 88 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 185 | AM6_DEV_GPIO1 | gpio | 89 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 186 | Not Connected | ||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 187 | Not Connected | ||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 188 | Not Connected | ||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 189 | Not Connected | ||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 190 | Not Connected | ||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 191 | Not Connected | ||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 192 | AM6_DEV_GPIO0 | gpio_bank | 0 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 193 | AM6_DEV_GPIO0 | gpio_bank | 1 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 194 | AM6_DEV_GPIO0 | gpio_bank | 2 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 195 | AM6_DEV_GPIO0 | gpio_bank | 3 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 196 | AM6_DEV_GPIO0 | gpio_bank | 4 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 197 | AM6_DEV_GPIO0 | gpio_bank | 5 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 198 | Not Connected | ||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 199 | Not Connected | ||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 200 | AM6_DEV_GPIO1 | gpio_bank | 0 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 201 | AM6_DEV_GPIO1 | gpio_bank | 1 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 202 | AM6_DEV_GPIO1 | gpio_bank | 2 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 203 | AM6_DEV_GPIO1 | gpio_bank | 3 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 204 | AM6_DEV_GPIO1 | gpio_bank | 4 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 205 | AM6_DEV_GPIO1 | gpio_bank | 5 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 206 | Not Connected | ||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 207 | Not Connected |
GPIOMUX_INTRTR0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 0 | AM6_DEV_ESM0 | esm_pls_event0 | 248 |
| AM6_DEV_ESM0 | esm_pls_event1 | 248 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 0 | AM6_DEV_ESM0 | esm_pls_event2 | 248 |
| AM6_DEV_GIC0 | spi | 392 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 1 | AM6_DEV_ESM0 | esm_pls_event0 | 249 |
| AM6_DEV_ESM0 | esm_pls_event1 | 249 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 1 | AM6_DEV_ESM0 | esm_pls_event2 | 249 |
| AM6_DEV_GIC0 | spi | 393 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 2 | AM6_DEV_ESM0 | esm_pls_event0 | 250 |
| AM6_DEV_ESM0 | esm_pls_event1 | 250 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 2 | AM6_DEV_ESM0 | esm_pls_event2 | 250 |
| AM6_DEV_GIC0 | spi | 394 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 3 | AM6_DEV_ESM0 | esm_pls_event0 | 251 |
| AM6_DEV_ESM0 | esm_pls_event1 | 251 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 3 | AM6_DEV_ESM0 | esm_pls_event2 | 251 |
| AM6_DEV_GIC0 | spi | 395 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 4 | AM6_DEV_ESM0 | esm_pls_event0 | 252 |
| AM6_DEV_ESM0 | esm_pls_event1 | 252 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 4 | AM6_DEV_ESM0 | esm_pls_event2 | 252 |
| AM6_DEV_GIC0 | spi | 396 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 5 | AM6_DEV_ESM0 | esm_pls_event0 | 253 |
| AM6_DEV_ESM0 | esm_pls_event1 | 253 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 5 | AM6_DEV_ESM0 | esm_pls_event2 | 253 |
| AM6_DEV_GIC0 | spi | 397 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 6 | AM6_DEV_ESM0 | esm_pls_event0 | 254 |
| AM6_DEV_ESM0 | esm_pls_event1 | 254 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 6 | AM6_DEV_ESM0 | esm_pls_event2 | 254 |
| AM6_DEV_GIC0 | spi | 398 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 7 | AM6_DEV_ESM0 | esm_pls_event0 | 255 |
| AM6_DEV_ESM0 | esm_pls_event1 | 255 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 7 | AM6_DEV_ESM0 | esm_pls_event2 | 255 |
| AM6_DEV_GIC0 | spi | 399 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 8 | AM6_DEV_GIC0 | spi | 400 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 9 | AM6_DEV_GIC0 | spi | 401 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 10 | AM6_DEV_GIC0 | spi | 402 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 11 | AM6_DEV_GIC0 | spi | 403 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 12 | AM6_DEV_GIC0 | spi | 404 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 13 | AM6_DEV_GIC0 | spi | 405 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 14 | AM6_DEV_GIC0 | spi | 406 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 15 | AM6_DEV_GIC0 | spi | 407 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 16 | AM6_DEV_GIC0 | spi | 408 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 17 | AM6_DEV_GIC0 | spi | 409 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 18 | AM6_DEV_GIC0 | spi | 410 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 19 | AM6_DEV_GIC0 | spi | 411 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 20 | AM6_DEV_GIC0 | spi | 412 |
| AM6_DEV_PRU_ICSSG0 | pr1_iep0_cap_intr_req | 0 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 20 | AM6_DEV_PRU_ICSSG1 | pr1_iep0_cap_intr_req | 0 |
| AM6_DEV_PRU_ICSSG2 | pr1_iep0_cap_intr_req | 0 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 21 | AM6_DEV_GIC0 | spi | 413 |
| AM6_DEV_PRU_ICSSG0 | pr1_iep0_cap_intr_req | 1 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 21 | AM6_DEV_PRU_ICSSG1 | pr1_iep0_cap_intr_req | 1 |
| AM6_DEV_PRU_ICSSG2 | pr1_iep0_cap_intr_req | 1 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 22 | AM6_DEV_GIC0 | spi | 414 |
| AM6_DEV_PRU_ICSSG0 | pr1_iep0_cap_intr_req | 2 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 22 | AM6_DEV_PRU_ICSSG1 | pr1_iep0_cap_intr_req | 2 |
| AM6_DEV_PRU_ICSSG2 | pr1_iep0_cap_intr_req | 2 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 23 | AM6_DEV_GIC0 | spi | 415 |
| AM6_DEV_PRU_ICSSG0 | pr1_iep0_cap_intr_req | 3 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 23 | AM6_DEV_PRU_ICSSG1 | pr1_iep0_cap_intr_req | 3 |
| AM6_DEV_PRU_ICSSG2 | pr1_iep0_cap_intr_req | 3 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 24 | AM6_DEV_GIC0 | spi | 416 |
| AM6_DEV_PRU_ICSSG0 | pr1_iep0_cap_intr_req | 4 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 24 | AM6_DEV_PRU_ICSSG0 | pr1_slv_intr | 88 |
| AM6_DEV_PRU_ICSSG1 | pr1_iep0_cap_intr_req | 4 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 24 | AM6_DEV_PRU_ICSSG1 | pr1_slv_intr | 88 |
| AM6_DEV_PRU_ICSSG2 | pr1_iep0_cap_intr_req | 4 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 24 | AM6_DEV_PRU_ICSSG2 | pr1_slv_intr | 88 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 25 | AM6_DEV_GIC0 | spi | 417 |
| AM6_DEV_PRU_ICSSG0 | pr1_iep0_cap_intr_req | 5 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 25 | AM6_DEV_PRU_ICSSG0 | pr1_slv_intr | 89 |
| AM6_DEV_PRU_ICSSG1 | pr1_iep0_cap_intr_req | 5 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 25 | AM6_DEV_PRU_ICSSG1 | pr1_slv_intr | 89 |
| AM6_DEV_PRU_ICSSG2 | pr1_iep0_cap_intr_req | 5 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 25 | AM6_DEV_PRU_ICSSG2 | pr1_slv_intr | 89 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 26 | AM6_DEV_GIC0 | spi | 418 |
| AM6_DEV_PRU_ICSSG0 | pr1_iep1_cap_intr_req | 0 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 26 | AM6_DEV_PRU_ICSSG0 | pr1_slv_intr | 90 |
| AM6_DEV_PRU_ICSSG1 | pr1_iep1_cap_intr_req | 0 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 26 | AM6_DEV_PRU_ICSSG1 | pr1_slv_intr | 90 |
| AM6_DEV_PRU_ICSSG2 | pr1_iep1_cap_intr_req | 0 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 26 | AM6_DEV_PRU_ICSSG2 | pr1_slv_intr | 90 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 27 | AM6_DEV_GIC0 | spi | 419 |
| AM6_DEV_PRU_ICSSG0 | pr1_iep1_cap_intr_req | 1 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 27 | AM6_DEV_PRU_ICSSG0 | pr1_slv_intr | 91 |
| AM6_DEV_PRU_ICSSG1 | pr1_iep1_cap_intr_req | 1 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 27 | AM6_DEV_PRU_ICSSG1 | pr1_slv_intr | 91 |
| AM6_DEV_PRU_ICSSG2 | pr1_iep1_cap_intr_req | 1 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 27 | AM6_DEV_PRU_ICSSG2 | pr1_slv_intr | 91 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 28 | AM6_DEV_GIC0 | spi | 420 |
| AM6_DEV_PRU_ICSSG0 | pr1_iep1_cap_intr_req | 2 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 28 | AM6_DEV_PRU_ICSSG0 | pr1_slv_intr | 92 |
| AM6_DEV_PRU_ICSSG1 | pr1_iep1_cap_intr_req | 2 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 28 | AM6_DEV_PRU_ICSSG1 | pr1_slv_intr | 92 |
| AM6_DEV_PRU_ICSSG2 | pr1_iep1_cap_intr_req | 2 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 28 | AM6_DEV_PRU_ICSSG2 | pr1_slv_intr | 92 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 29 | AM6_DEV_GIC0 | spi | 421 |
| AM6_DEV_PRU_ICSSG0 | pr1_iep1_cap_intr_req | 3 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 29 | AM6_DEV_PRU_ICSSG0 | pr1_slv_intr | 93 |
| AM6_DEV_PRU_ICSSG1 | pr1_iep1_cap_intr_req | 3 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 29 | AM6_DEV_PRU_ICSSG1 | pr1_slv_intr | 93 |
| AM6_DEV_PRU_ICSSG2 | pr1_iep1_cap_intr_req | 3 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 29 | AM6_DEV_PRU_ICSSG2 | pr1_slv_intr | 93 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 30 | AM6_DEV_GIC0 | spi | 422 |
| AM6_DEV_PRU_ICSSG0 | pr1_iep1_cap_intr_req | 4 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 30 | AM6_DEV_PRU_ICSSG0 | pr1_slv_intr | 94 |
| AM6_DEV_PRU_ICSSG1 | pr1_iep1_cap_intr_req | 4 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 30 | AM6_DEV_PRU_ICSSG1 | pr1_slv_intr | 94 |
| AM6_DEV_PRU_ICSSG2 | pr1_iep1_cap_intr_req | 4 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 30 | AM6_DEV_PRU_ICSSG2 | pr1_slv_intr | 94 |
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 31 | AM6_DEV_GIC0 | spi | 423 |
| AM6_DEV_PRU_ICSSG0 | pr1_iep1_cap_intr_req | 5 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 31 | AM6_DEV_PRU_ICSSG0 | pr1_slv_intr | 95 |
| AM6_DEV_PRU_ICSSG1 | pr1_iep1_cap_intr_req | 5 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 31 | AM6_DEV_PRU_ICSSG1 | pr1_slv_intr | 95 |
| AM6_DEV_PRU_ICSSG2 | pr1_iep1_cap_intr_req | 5 | |||
| AM6_DEV_GPIOMUX_INTRTR0 | 100 | 31 | AM6_DEV_PRU_ICSSG2 | pr1_slv_intr | 95 |
TIMESYNC_INTRTR0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 0 | Not Connected | ||
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 1 | AM6_DEV_GTC0 | gtc_push_event | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 2 | Not Connected | ||
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 3 | Not Connected | ||
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 4 | AM6_DEV_NAVSS0 | cpts0_genf0 | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 5 | AM6_DEV_NAVSS0 | cpts0_genf1 | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 6 | AM6_DEV_NAVSS0 | cpts0_genf2 | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 7 | AM6_DEV_NAVSS0 | cpts0_genf3 | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 8 | AM6_DEV_NAVSS0 | cpts0_genf4 | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 9 | AM6_DEV_NAVSS0 | cpts0_genf5 | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 10 | AM6_DEV_PCIE0 | pcie_cpts_genf0 | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 11 | AM6_DEV_PCIE1 | pcie_cpts_genf0 | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 12 | AM6_DEV_MCU_CPSW0 | cpts_genf0 | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 13 | AM6_DEV_MCU_CPSW0 | cpts_genf1 | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 14 | AM6_DEV_PCIE0 | pcie_cpts_hw1_push | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 15 | AM6_DEV_PCIE1 | pcie_cpts_hw1_push | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 16 | AM6_DEV_PRU_ICSSG0 | pr1_edc0_sync0_out | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 17 | AM6_DEV_PRU_ICSSG0 | pr1_edc0_sync1_out | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 18 | AM6_DEV_PRU_ICSSG0 | pr1_edc1_sync0_out | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 19 | AM6_DEV_PRU_ICSSG0 | pr1_edc1_sync1_out | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 20 | AM6_DEV_PRU_ICSSG1 | pr1_edc0_sync0_out | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 21 | AM6_DEV_PRU_ICSSG1 | pr1_edc0_sync1_out | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 22 | AM6_DEV_PRU_ICSSG1 | pr1_edc1_sync0_out | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 23 | AM6_DEV_PRU_ICSSG1 | pr1_edc1_sync1_out | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 24 | AM6_DEV_PRU_ICSSG2 | pr1_edc0_sync0_out | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 25 | AM6_DEV_PRU_ICSSG2 | pr1_edc0_sync1_out | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 26 | AM6_DEV_PRU_ICSSG2 | pr1_edc1_sync0_out | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 27 | AM6_DEV_PRU_ICSSG2 | pr1_edc1_sync1_out | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 28 | AM6_DEV_PCIE0 | pcie_cpts_sync | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 29 | AM6_DEV_PCIE1 | pcie_cpts_sync | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 30 | AM6_DEV_NAVSS0 | cpts0_sync | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 31 | AM6_DEV_MCU_CPSW0 | cpts_sync | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 32 | Not Connected | ||
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 33 | Not Connected | ||
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 34 | Not Connected | ||
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 35 | Not Connected | ||
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 36 | Not Connected | ||
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 37 | Not Connected | ||
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 38 | Not Connected | ||
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 39 | Not Connected | ||
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 40 | Not Connected | ||
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 41 | Not Connected | ||
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 42 | Not Connected | ||
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 43 | Not Connected | ||
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 44 | Not Connected | ||
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 45 | Not Connected | ||
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 46 | Not Connected | ||
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 47 | Not Connected |
TIMESYNC_INTRTR0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 0 | AM6_DEV_NAVSS0 | cpts0_hw1_push | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 1 | AM6_DEV_NAVSS0 | cpts0_hw2_push | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 2 | AM6_DEV_NAVSS0 | cpts0_hw3_push | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 3 | AM6_DEV_NAVSS0 | cpts0_hw4_push | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 4 | AM6_DEV_NAVSS0 | cpts0_hw5_push | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 5 | AM6_DEV_NAVSS0 | cpts0_hw6_push | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 6 | AM6_DEV_NAVSS0 | cpts0_hw7_push | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 7 | AM6_DEV_NAVSS0 | cpts0_hw8_push | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 8 | AM6_DEV_PRU_ICSSG0 | pr1_edc0_latch0_in | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 9 | AM6_DEV_PRU_ICSSG0 | pr1_edc0_latch1_in | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 10 | AM6_DEV_PRU_ICSSG0 | pr1_edc1_latch0_in | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 11 | AM6_DEV_PRU_ICSSG0 | pr1_edc1_latch1_in | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 12 | AM6_DEV_PRU_ICSSG1 | pr1_edc0_latch0_in | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 13 | AM6_DEV_PRU_ICSSG1 | pr1_edc0_latch1_in | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 14 | AM6_DEV_PRU_ICSSG1 | pr1_edc1_latch0_in | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 15 | AM6_DEV_PRU_ICSSG1 | pr1_edc1_latch1_in | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 16 | AM6_DEV_PRU_ICSSG2 | pr1_edc0_latch0_in | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 17 | AM6_DEV_PRU_ICSSG2 | pr1_edc0_latch1_in | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 18 | AM6_DEV_PRU_ICSSG2 | pr1_edc1_latch0_in | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 19 | AM6_DEV_PRU_ICSSG2 | pr1_edc1_latch1_in | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 20 | AM6_DEV_PCIE0 | pcie_cpts_hw2_push | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 21 | AM6_DEV_PCIE1 | pcie_cpts_hw2_push | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 22 | Not Connected | ||
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 23 | Not Connected | ||
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 24 | AM6_DEV_MCU_CPSW0 | cpts_hw3_push | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 25 | AM6_DEV_MCU_CPSW0 | cpts_hw4_push | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 26 | Not Connected | ||
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 27 | Not Connected | ||
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 28 | Not Connected | ||
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 29 | Not Connected | ||
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 30 | Not Connected | ||
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 31 | Not Connected | ||
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 32 | AM6_DEV_PDMA1 | levent_in | 0 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 33 | AM6_DEV_PDMA1 | levent_in | 1 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 34 | AM6_DEV_PDMA1 | levent_in | 2 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 35 | AM6_DEV_PDMA1 | levent_in | 3 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 36 | AM6_DEV_PDMA1 | levent_in | 4 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 37 | AM6_DEV_PDMA1 | levent_in | 5 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 38 | AM6_DEV_PDMA1 | levent_in | 6 |
| AM6_DEV_TIMESYNC_INTRTR0 | 145 | 39 | AM6_DEV_PDMA1 | levent_in | 7 |
WKUP_GPIOMUX_INTRTR0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 0 | AM6_DEV_WKUP_GPIO0 | gpio | 0 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 1 | AM6_DEV_WKUP_GPIO0 | gpio | 1 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 2 | AM6_DEV_WKUP_GPIO0 | gpio | 2 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 3 | AM6_DEV_WKUP_GPIO0 | gpio | 3 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 4 | AM6_DEV_WKUP_GPIO0 | gpio | 4 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 5 | AM6_DEV_WKUP_GPIO0 | gpio | 5 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 6 | AM6_DEV_WKUP_GPIO0 | gpio | 6 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 7 | AM6_DEV_WKUP_GPIO0 | gpio | 7 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 8 | AM6_DEV_WKUP_GPIO0 | gpio | 8 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 9 | AM6_DEV_WKUP_GPIO0 | gpio | 9 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 10 | AM6_DEV_WKUP_GPIO0 | gpio | 10 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 11 | AM6_DEV_WKUP_GPIO0 | gpio | 11 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 12 | AM6_DEV_WKUP_GPIO0 | gpio | 12 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 13 | AM6_DEV_WKUP_GPIO0 | gpio | 13 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 14 | AM6_DEV_WKUP_GPIO0 | gpio | 14 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 15 | AM6_DEV_WKUP_GPIO0 | gpio | 15 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 16 | AM6_DEV_WKUP_GPIO0 | gpio | 16 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 17 | AM6_DEV_WKUP_GPIO0 | gpio | 17 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 18 | AM6_DEV_WKUP_GPIO0 | gpio | 18 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 19 | AM6_DEV_WKUP_GPIO0 | gpio | 19 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 20 | AM6_DEV_WKUP_GPIO0 | gpio | 20 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 21 | AM6_DEV_WKUP_GPIO0 | gpio | 21 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 22 | AM6_DEV_WKUP_GPIO0 | gpio | 22 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 23 | AM6_DEV_WKUP_GPIO0 | gpio | 23 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 24 | AM6_DEV_WKUP_GPIO0 | gpio | 24 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 25 | AM6_DEV_WKUP_GPIO0 | gpio | 25 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 26 | AM6_DEV_WKUP_GPIO0 | gpio | 26 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 27 | AM6_DEV_WKUP_GPIO0 | gpio | 27 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 28 | AM6_DEV_WKUP_GPIO0 | gpio | 28 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 29 | AM6_DEV_WKUP_GPIO0 | gpio | 29 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 30 | AM6_DEV_WKUP_GPIO0 | gpio | 30 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 31 | AM6_DEV_WKUP_GPIO0 | gpio | 31 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 32 | AM6_DEV_WKUP_GPIO0 | gpio | 32 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 33 | AM6_DEV_WKUP_GPIO0 | gpio | 33 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 34 | AM6_DEV_WKUP_GPIO0 | gpio | 34 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 35 | AM6_DEV_WKUP_GPIO0 | gpio | 35 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 36 | AM6_DEV_WKUP_GPIO0 | gpio | 36 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 37 | AM6_DEV_WKUP_GPIO0 | gpio | 37 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 38 | AM6_DEV_WKUP_GPIO0 | gpio | 38 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 39 | AM6_DEV_WKUP_GPIO0 | gpio | 39 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 40 | AM6_DEV_WKUP_GPIO0 | gpio | 40 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 41 | AM6_DEV_WKUP_GPIO0 | gpio | 41 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 42 | AM6_DEV_WKUP_GPIO0 | gpio | 42 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 43 | AM6_DEV_WKUP_GPIO0 | gpio | 43 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 44 | AM6_DEV_WKUP_GPIO0 | gpio | 44 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 45 | AM6_DEV_WKUP_GPIO0 | gpio | 45 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 46 | AM6_DEV_WKUP_GPIO0 | gpio | 46 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 47 | AM6_DEV_WKUP_GPIO0 | gpio | 47 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 48 | AM6_DEV_WKUP_GPIO0 | gpio | 48 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 49 | AM6_DEV_WKUP_GPIO0 | gpio | 49 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 50 | AM6_DEV_WKUP_GPIO0 | gpio | 50 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 51 | AM6_DEV_WKUP_GPIO0 | gpio | 51 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 52 | AM6_DEV_WKUP_GPIO0 | gpio | 52 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 53 | AM6_DEV_WKUP_GPIO0 | gpio | 53 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 54 | AM6_DEV_WKUP_GPIO0 | gpio | 54 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 55 | AM6_DEV_WKUP_GPIO0 | gpio | 55 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 56 | Not Connected | ||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 57 | Not Connected | ||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 58 | Not Connected | ||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 59 | Not Connected | ||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 60 | AM6_DEV_WKUP_GPIO0 | gpio_bank | 0 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 61 | AM6_DEV_WKUP_GPIO0 | gpio_bank | 1 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 62 | AM6_DEV_WKUP_GPIO0 | gpio_bank | 2 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 63 | AM6_DEV_WKUP_GPIO0 | gpio_bank | 3 |
WKUP_GPIOMUX_INTRTR0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 0 | AM6_DEV_WKUP_DMSC0_CORTEX_M3_0 | nvic | 184 |
| AM6_DEV_GIC0 | spi | 712 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 0 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 124 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 124 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 1 | AM6_DEV_WKUP_DMSC0_CORTEX_M3_0 | nvic | 185 |
| AM6_DEV_GIC0 | spi | 713 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 1 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 125 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 125 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 2 | AM6_DEV_WKUP_DMSC0_CORTEX_M3_0 | nvic | 186 |
| AM6_DEV_GIC0 | spi | 714 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 2 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 126 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 126 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 3 | AM6_DEV_WKUP_DMSC0_CORTEX_M3_0 | nvic | 187 |
| AM6_DEV_GIC0 | spi | 715 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 3 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 127 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 127 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 4 | AM6_DEV_WKUP_DMSC0_CORTEX_M3_0 | nvic | 188 |
| AM6_DEV_GIC0 | spi | 716 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 4 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 128 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 128 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 5 | AM6_DEV_WKUP_DMSC0_CORTEX_M3_0 | nvic | 189 |
| AM6_DEV_GIC0 | spi | 717 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 5 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 129 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 129 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 6 | AM6_DEV_WKUP_DMSC0_CORTEX_M3_0 | nvic | 190 |
| AM6_DEV_GIC0 | spi | 718 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 6 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 130 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 130 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 7 | AM6_DEV_WKUP_DMSC0_CORTEX_M3_0 | nvic | 191 |
| AM6_DEV_GIC0 | spi | 719 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 7 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 131 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 131 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 8 | AM6_DEV_WKUP_DMSC0_CORTEX_M3_0 | nvic | 192 |
| AM6_DEV_WKUP_ESM0 | esm_pls_event0 | 88 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 8 | AM6_DEV_WKUP_ESM0 | esm_pls_event1 | 88 |
| AM6_DEV_WKUP_ESM0 | esm_pls_event2 | 88 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 8 | AM6_DEV_GIC0 | spi | 720 |
| AM6_DEV_MCU_ARMSS0_CPU0 | intr | 132 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 8 | AM6_DEV_MCU_ARMSS0_CPU1 | intr | 132 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 9 | AM6_DEV_WKUP_DMSC0_CORTEX_M3_0 | nvic | 193 |
| AM6_DEV_WKUP_ESM0 | esm_pls_event0 | 89 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 9 | AM6_DEV_WKUP_ESM0 | esm_pls_event1 | 89 |
| AM6_DEV_WKUP_ESM0 | esm_pls_event2 | 89 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 9 | AM6_DEV_GIC0 | spi | 721 |
| AM6_DEV_MCU_ARMSS0_CPU0 | intr | 133 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 9 | AM6_DEV_MCU_ARMSS0_CPU1 | intr | 133 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 10 | AM6_DEV_WKUP_DMSC0_CORTEX_M3_0 | nvic | 194 |
| AM6_DEV_WKUP_ESM0 | esm_pls_event0 | 90 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 10 | AM6_DEV_WKUP_ESM0 | esm_pls_event1 | 90 |
| AM6_DEV_WKUP_ESM0 | esm_pls_event2 | 90 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 10 | AM6_DEV_GIC0 | spi | 722 |
| AM6_DEV_MCU_ARMSS0_CPU0 | intr | 134 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 10 | AM6_DEV_MCU_ARMSS0_CPU1 | intr | 134 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 11 | AM6_DEV_WKUP_DMSC0_CORTEX_M3_0 | nvic | 195 |
| AM6_DEV_WKUP_ESM0 | esm_pls_event0 | 91 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 11 | AM6_DEV_WKUP_ESM0 | esm_pls_event1 | 91 |
| AM6_DEV_WKUP_ESM0 | esm_pls_event2 | 91 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 11 | AM6_DEV_GIC0 | spi | 723 |
| AM6_DEV_MCU_ARMSS0_CPU0 | intr | 135 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 11 | AM6_DEV_MCU_ARMSS0_CPU1 | intr | 135 |
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 12 | AM6_DEV_WKUP_ESM0 | esm_pls_event0 | 92 |
| AM6_DEV_WKUP_ESM0 | esm_pls_event1 | 92 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 12 | AM6_DEV_WKUP_ESM0 | esm_pls_event2 | 92 |
| AM6_DEV_GIC0 | spi | 724 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 12 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 136 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 136 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 13 | AM6_DEV_WKUP_ESM0 | esm_pls_event0 | 93 |
| AM6_DEV_WKUP_ESM0 | esm_pls_event1 | 93 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 13 | AM6_DEV_WKUP_ESM0 | esm_pls_event2 | 93 |
| AM6_DEV_GIC0 | spi | 725 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 13 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 137 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 137 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 14 | AM6_DEV_WKUP_ESM0 | esm_pls_event0 | 94 |
| AM6_DEV_WKUP_ESM0 | esm_pls_event1 | 94 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 14 | AM6_DEV_WKUP_ESM0 | esm_pls_event2 | 94 |
| AM6_DEV_GIC0 | spi | 726 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 14 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 138 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 138 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 15 | AM6_DEV_WKUP_ESM0 | esm_pls_event0 | 95 |
| AM6_DEV_WKUP_ESM0 | esm_pls_event1 | 95 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 15 | AM6_DEV_WKUP_ESM0 | esm_pls_event2 | 95 |
| AM6_DEV_GIC0 | spi | 727 | |||
| AM6_DEV_WKUP_GPIOMUX_INTRTR0 | 156 | 15 | AM6_DEV_MCU_ARMSS0_CPU0 | intr | 139 |
| AM6_DEV_MCU_ARMSS0_CPU1 | intr | 139 |
Interrupt Aggregator Device IDs¶
Some System Firmware TISCI message APIs require the Interrupt Aggregator device ID be provided as part of the request. Based on AM6 Device IDs these are the valid Interrupt Aggregator device IDs.
| Interrupt Aggregator Device Name | Interrupt Aggregator Device ID |
|---|---|
| AM6_DEV_NAVSS0_MODSS_INTA0 | 180 |
| AM6_DEV_NAVSS0_MODSS_INTA1 | 181 |
| AM6_DEV_NAVSS0_UDMASS_INTA0 | 179 |
| AM6_DEV_MCU_NAVSS0_INTR_AGGR_0 | 189 |
Interrupt Aggregator Virtual Interrupts¶
This section describes Interrupt Aggregator virtual interrupts. The virtual interrupts are used in interrupt management based TISCI messages.
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| Interrupt Aggregator Name | Virtual Interrupt Range |
|---|---|
| AM6_DEV_NAVSS0_MODSS_INTA0 | 0 to 63 |
| AM6_DEV_NAVSS0_MODSS_INTA1 | 0 to 63 |
| AM6_DEV_NAVSS0_UDMASS_INTA0 (RESERVED BY SYSTEM FIRMWARE) | 0 to 15 |
| AM6_DEV_NAVSS0_UDMASS_INTA0 | 16 to 255 |
| AM6_DEV_MCU_NAVSS0_INTR_AGGR_0 (RESERVED BY SYSTEM FIRMWARE) | 0 to 7 |
| AM6_DEV_MCU_NAVSS0_INTR_AGGR_0 | 8 to 255 |
Global Events¶
This section describes AM6 global events. The global events are used in interrupt management based TISCI messages.
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| Global Event Name | Global Event Range |
|---|---|
| NAVSS0_UDMASS_INTA0 SEVT (RESERVED BY SYSTEM FIRMWARE) | 0 to 15 |
| NAVSS0_UDMASS_INTA0 SEVT | 16 to 4607 |
| MCU_NAVSS0_INTR_AGGR_0 SEVT (RESERVED BY SYSTEM FIRMWARE) | 16384 to 16391 |
| MCU_NAVSS0_INTR_AGGR_0 SEVT | 16392 to 17919 |
| NAVSS0_MODSS_INTA0 SEVT | 20480 to 21503 |
| NAVSS0_MODSS_INTA1 SEVT | 22528 to 23551 |
| NAVSS0_UDMASS_INTA0 MEVT | 32768 to 33279 |
| MCU_NAVSS0_INTR_AGGR_0 MEVT | 34816 to 34943 |
| NAVSS0_UDMASS_INTA0 GEVT | 36864 to 37375 |
| MCU_NAVSS0_INTR_AGGR_0 GEVT | 39936 to 40191 |
| NAVSS0_UDMAP0 TRIGGER | 49152 to 50175 |
| MCU_NAVSS0_UDMAP0 TRIGGER | 56320 to 56575 |
Event-Based Interrupt Source IDs¶
| Device Name | Device ID | Interrupt Source Name | Interrupt Source Index |
|---|---|---|---|
| AM6_DEV_NAVSS0_RINGACC0 | 187 | Ring events | 0 to 767 |
| AM6_DEV_MCU_NAVSS0_RINGACC0 | 195 | Ring events | 0 to 255 |
| AM6_DEV_NAVSS0_RINGACC0 | 187 | Ring monitor events | 1024 to 1055 |
| AM6_DEV_MCU_NAVSS0_RINGACC0 | 195 | Ring monitor events | 1024 to 1055 |
| AM6_DEV_NAVSS0_RINGACC0 | 187 | Ring global error event | 2048 |
| AM6_DEV_MCU_NAVSS0_RINGACC0 | 195 | Ring global error event | 2048 |
| AM6_DEV_NAVSS0_UDMAP0 | 188 | UDMA transmit channel OES events | 0 to 151 |
| AM6_DEV_NAVSS0_UDMAP0 | 188 | UDMA transmit channel EOES events | 256 to 407 |
| AM6_DEV_NAVSS0_UDMAP0 | 188 | UDMA receive channel OES events | 512 to 661 |
| AM6_DEV_NAVSS0_UDMAP0 | 188 | UDMA receive channel EOES events | 768 to 917 |
| AM6_DEV_NAVSS0_UDMAP0 | 188 | UDMA global configuration invalid flow event | 1024 |
| AM6_DEV_MCU_NAVSS0_UDMAP0 | 194 | UDMA transmit channel OES events | 0 to 47 |
| AM6_DEV_MCU_NAVSS0_UDMAP0 | 194 | UDMA transmit channel EOES events | 256 to 303 |
| AM6_DEV_MCU_NAVSS0_UDMAP0 | 194 | UDMA receive channel OES events | 512 to 559 |
| AM6_DEV_MCU_NAVSS0_UDMAP0 | 194 | UDMA receive channel EOES events | 768 to 815 |
| AM6_DEV_MCU_NAVSS0_UDMAP0 | 194 | UDMA global configuration invalid flow event | 1024 |