ADCBufMSP432E4.h

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/*
 * Copyright (c) 2018, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
#ifndef ti_drivers_adcbuf_ADCBufMSP432E4__include
#define ti_drivers_adcbuf_ADCBufMSP432E4__include

#ifdef __cplusplus
extern "C" {
#endif

#include <stdint.h>
#include <stdbool.h>

#include <ti/drivers/ADCBuf.h>
#include <ti/drivers/dpl/HwiP.h>
#include <ti/drivers/dpl/SemaphoreP.h>
#include <ti/drivers/dma/UDMAMSP432E4.h>
#include <ti/devices/msp432e4/driverlib/adc.h>

/*
 *  ADCBuf port/pin defines for pin configuration.  Ports B, D, E, and K are
 *  configurable through the port mapping controller.  None of the port
 *  mappings support ADC.
 *  Channel specifies the ADC channel and ranges from 0 to 19.
 *  pin range: 0 - 7, port range: 0 - 15
 *
 *
 *    15 - 10    19 - 16  15 - 8  7 - 0
 *  ---------------------------------
 *  |  CHANNEL | X | X | PORT | PIN |
 *  ---------------------------------
 *
 *  channel = (((config) >> 10) & 0x1F)
 *  port = (((config) << 4) & 0x40000000)
 *  pin = ((config) & 0xFF)
 *
 *
 */
/* Port B */
#define ADCBufMSP432E4_PB_4_A10 ((10 << 16) | 0x5910) /* ch 10, port B, pin 4 */
#define ADCBufMSP432E4_PB_5_A11 ((11 << 16) | 0x5920) /* ch 11, port B, pin 5 */

/* Port D */
#define ADCBufMSP432E4_PD_0_A15 ((15 << 16) | 0x5B01) /* ch 15, port D, pin 0 */
#define ADCBufMSP432E4_PD_1_A14 ((14 << 16) | 0x5B02) /* ch 14, port D, pin 1 */
#define ADCBufMSP432E4_PD_2_A13 ((13 << 16) | 0x5B04) /* ch 13, port D, pin 2 */
#define ADCBufMSP432E4_PD_3_A12 ((12 << 16) | 0x5B08) /* ch 12, port D, pin 3 */
#define ADCBufMSP432E4_PD_4_A7  ((7 << 16) | 0x5B10)  /* ch 7, port D, pin 4 */
#define ADCBufMSP432E4_PD_5_A6  ((6 << 16) | 0x5B20)  /* ch 6, port D, pin 5 */
#define ADCBufMSP432E4_PD_6_A5  ((5 << 16) | 0x5B40)  /* ch 5, port D, pin 6 */
#define ADCBufMSP432E4_PD_7_A4  ((4 << 16) | 0x5B80)  /* ch 4, port D, pin 7 */

/* Port E */
#define ADCBufMSP432E4_PE_0_A3  ((3 << 16) | 0x5C01) /* ch 3, port E, pin 0 */
#define ADCBufMSP432E4_PE_1_A2  ((2 << 16) | 0x5C02) /* ch 2, port E, pin 1 */
#define ADCBufMSP432E4_PE_2_A1  ((1 << 16) | 0x5C04) /* ch 1, port E, pin 2 */
#define ADCBufMSP432E4_PE_3_A0  ((0 << 16) | 0x5C08) /* ch 0, port E, pin 3 */
#define ADCBufMSP432E4_PE_4_A9  ((9 << 16) | 0x5C10) /* ch 9, port E, pin 4 */
#define ADCBufMSP432E4_PE_5_A8  ((8 << 16) | 0x5C20) /* ch 8, port E, pin 5 */
#define ADCBufMSP432E4_PE_6_A20  ((20 << 16) | 0x5C40) /* ch 20, port E, pin 6 */
#define ADCBufMSP432E4_PE_7_A21  ((21 << 16) | 0x5C80) /* ch 21, port E, pin 7 */

/* Port K */
#define ADCBufMSP432E4_PK_0_A16 ((16 << 16) | 0x6101) /* ch 16, port K, pin 0 */
#define ADCBufMSP432E4_PK_1_A17 ((17 << 16) | 0x6102) /* ch 17, port K, pin 1 */
#define ADCBufMSP432E4_PK_2_A18 ((18 << 16) | 0x6104) /* ch 18, port K, pin 2 */
#define ADCBufMSP432E4_PK_3_A19 ((19 << 16) | 0x6108) /* ch 19, port K, pin 3 */

/* Port P */
#define ADCBufMSP432E4_PP_6_A22  ((22 << 16) | 0x6540) /* ch 22, port P, pin 6 */
#define ADCBufMSP432E4_PP_7_A23  ((23 << 16) | 0x6580) /* ch 23, port P, pin 7 */

 /*
 * =============================================================================
 * Constants
 * =============================================================================
 */
#define ADCBufMSP432E4_PIN_NONE 0

/* Number of available ADC channels on device */
#define MSP432E4_NUM_ADC_CHANNELS (24)

/* Number of ADC Sequencers per Module */
#define ADCBufMSP432E4_SEQUENCER_COUNT 4

/* ADC function table pointer */
extern const ADCBuf_FxnTable ADCBufMSP432E4_fxnTable;

typedef enum ADCBufMSP432E4_SequencePriorities {
    ADCBufMSP432E4_Priority_0 = 0,
    ADCBufMSP432E4_Priority_1 = 1,
    ADCBufMSP432E4_Priority_2 = 2,
    ADCBufMSP432E4_Priority_3 = 3,
    ADCBufMSP432E4_Seq_Disable = 4
} ADCBufMSP432E4_SequencePriorities;

typedef enum ADCBufMSP432E4_Sequencer {
    ADCBufMSP432E4_Seq_0 = 0,
    ADCBufMSP432E4_Seq_1 = 1,
    ADCBufMSP432E4_Seq_2 = 2,
    ADCBufMSP432E4_Seq_3 = 3
} ADCBufMSP432E4_Sequencer;

typedef enum ADCBufMSP432E4_InternalSourceMode {
    ADCBufMSP432E4_INTERNAL_SOURCE_MODE_OFF = 0,
    ADCBufMSP432E4_TEMPERATURE_MODE = ADC_CTL_TS,
} ADCBufMSP432E4_InternalSourceMode;

typedef enum ADCBufMSP432E4_DifferentialMode {
    ADCBufMSP432E4_SINGLE_ENDED = 0,
    ADCBufMSP432E4_DIFFERENTIAL = ADC_CTL_D
} ADCBufMSP432E4_DifferentialMode;

typedef enum ADCBufMSP432E4_TriggerSource {
    ADCBufMSP432E4_SOFTWARE_AUTOMATIC_TRIGGER = ADC_TRIGGER_ALWAYS,
    ADCBufMSP432E4_TIMER_TRIGGER = ADC_TRIGGER_TIMER,
}ADCBufMSP432E4_TriggerSource;

typedef enum ADCBufMSP432E4_Phase {
    ADCBufMSP432E4_Phase_Delay_0 = ADC_PHASE_0,
    ADCBufMSP432E4_Phase_Delay_22_5 = ADC_PHASE_22_5,
    ADCBufMSP432E4_Phase_Delay_45 = ADC_PHASE_45,
    ADCBufMSP432E4_Phase_Delay_67_5 = ADC_PHASE_67_5,
    ADCBufMSP432E4_Phase_Delay_90 = ADC_PHASE_90,
    ADCBufMSP432E4_Phase_Delay_112_5 = ADC_PHASE_112_5,
    ADCBufMSP432E4_Phase_Delay_135 = ADC_PHASE_135,
    ADCBufMSP432E4_Phase_Delay_157_5 = ADC_PHASE_157_5,
    ADCBufMSP432E4_Phase_Delay_180 = ADC_PHASE_180,
    ADCBufMSP432E4_Phase_Delay_202_5 = ADC_PHASE_202_5,
    ADCBufMSP432E4_Phase_Delay_225 = ADC_PHASE_225,
    ADCBufMSP432E4_Phase_Delay_247_5 = ADC_PHASE_247_5,
    ADCBufMSP432E4_Phase_Delay_270 = ADC_PHASE_270,
    ADCBufMSP432E4_Phase_Delay_292_5 = ADC_PHASE_292_5,
    ADCBufMSP432E4_Phase_Delay_315 = ADC_PHASE_315,
    ADCBufMSP432E4_Phase_Delay_337_5 = ADC_PHASE_337_5,
} ADCBufMSP432E4_Phase;

typedef enum ADCBufMSP432E4_SamplingDuration {
    ADCBufMSP432E4_SamplingDuration_PULSE_WIDTH_4 = ADC_CTL_SHOLD_4,
    ADCBufMSP432E4_SamplingDuration_PULSE_WIDTH_8 = ADC_CTL_SHOLD_8,
    ADCBufMSP432E4_SamplingDuration_PULSE_WIDTH_16 = ADC_CTL_SHOLD_16,
    ADCBufMSP432E4_SamplingDuration_PULSE_WIDTH_32 = ADC_CTL_SHOLD_32,
    ADCBufMSP432E4_SamplingDuration_PULSE_WIDTH_64 = ADC_CTL_SHOLD_64,
    ADCBufMSP432E4_SamplingDuration_PULSE_WIDTH_128 = ADC_CTL_SHOLD_128,
    ADCBufMSP432E4_SamplingDuration_PULSE_WIDTH_256 = ADC_CTL_SHOLD_256
} ADCBufMSP432E4_SamplingDuration;

typedef enum ADCBufMSP432E4_ReferenceSource {
    ADCBufMSP432E4_VREF_INTERNAL = ADC_REF_INT,
    ADCBufMSP432E4_VREF_EXTERNAL_3V = ADC_REF_EXT_3V
}ADCBufMSP432E4_ReferenceSource;

typedef struct ADCBufMSP432E4_ParamsExtension{
    ADCBufMSP432E4_SamplingDuration samplingDuration;   
} ADCBufMSP432E4_ParamsExtension;

typedef struct ADCBufMSP432E4_Channels {
    uint32_t refVoltage;                                   
    uint_fast16_t adcPin;                                  
    ADCBufMSP432E4_Sequencer adcSequence;                  
    ADCBufMSP432E4_DifferentialMode adcInputMode;          
    ADCBufMSP432E4_InternalSourceMode adcInternalSource;   
    uint_fast16_t adcDifferentialPin;                      
} ADCBufMSP432E4_Channels;

typedef struct ADCBufMSP432E4_HWAttrsV1 {
    uint32_t intPriority; 
    uint32_t adcBase; 
    uint32_t adcTimerSource;
    ADCBufMSP432E4_Channels *channelSetting; 
    ADCBufMSP432E4_TriggerSource *adcTriggerSource; 
    ADCBufMSP432E4_Phase modulePhase; 
    ADCBufMSP432E4_ReferenceSource refSource; 
    ADCBufMSP432E4_SequencePriorities *sequencePriority; 
    uint8_t useDMA; 
} ADCBufMSP432E4_HWAttrsV1;

typedef struct ADCBufMSP432E4_Object {
    SemaphoreP_Handle mutex;                /* Grants exclusive access to ADC */
    SemaphoreP_Handle convertComplete;      /* Notify finished ADC convert */
    HwiP_Handle       sequencerHwiHandles[4]; /* Hardware interrupt handles, one per sequencer */

    uint_fast8_t        pingpongFlag[4];          /* PingPong flag indicates which sample buffer is active in the conversion */
    uint_fast8_t        channelCount[4];          /* Count of sampling channels */
    ADCBuf_Conversion   *conversions[4];

    ADCBuf_Callback     callBackFxn;           /* Callback function pointer */

    uint16_t            *sampleBuffer[4];
    uint_fast16_t        sampleIndex[4];        /* Internal dec. conversion buffer counter */
    uint_fast16_t        sampleCount[4];      /* Total sampling count per channel */

    ADCBufMSP432E4_SamplingDuration  samplingDuration;           
    uint32_t                        semaphoreTimeout;           
    uint32_t                        samplingFrequency;          
    ADCBuf_Recurrence_Mode          recurrenceMode;             
    ADCBuf_Return_Mode              returnMode;                 
    UDMAMSP432E4_Handle  dmaHandle;
    bool                 isOpen;               /* To determine if the ADC is open */

} ADCBufMSP432E4_Object;

typedef struct ADCBufMSP432E4_TimerSettings {
    uint32_t timerSource;
    uint32_t timerInstances;
    uint32_t timerFrequency;
    bool     isInitialized;
} ADCBufMSP432E4_TimerSettings;

#ifdef __cplusplus
}
#endif

#endif /* ti_drivers_adcbuf_ADCBufMSP432E4__include */