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Macros | |
#define | SSI_O_CR0 0x00000000 |
#define | SSI_O_CR1 0x00000004 |
#define | SSI_O_DR 0x00000008 |
#define | SSI_O_SR 0x0000000C |
#define | SSI_O_CPSR 0x00000010 |
#define | SSI_O_IM 0x00000014 |
#define | SSI_O_RIS 0x00000018 |
#define | SSI_O_MIS 0x0000001C |
#define | SSI_O_ICR 0x00000020 |
#define | SSI_O_DMACTL 0x00000024 |
#define | SSI_O_PP 0x00000FC0 |
#define | SSI_O_CC 0x00000FC8 |
#define | SSI_CR0_SCR_M 0x0000FF00 |
#define | SSI_CR0_SPH 0x00000080 |
#define | SSI_CR0_SPO 0x00000040 |
#define | SSI_CR0_FRF_M 0x00000030 |
#define | SSI_CR0_FRF_MOTO 0x00000000 |
#define | SSI_CR0_FRF_TI 0x00000010 |
#define | SSI_CR0_DSS_M 0x0000000F |
#define | SSI_CR0_DSS_4 0x00000003 |
#define | SSI_CR0_DSS_5 0x00000004 |
#define | SSI_CR0_DSS_6 0x00000005 |
#define | SSI_CR0_DSS_7 0x00000006 |
#define | SSI_CR0_DSS_8 0x00000007 |
#define | SSI_CR0_DSS_9 0x00000008 |
#define | SSI_CR0_DSS_10 0x00000009 |
#define | SSI_CR0_DSS_11 0x0000000A |
#define | SSI_CR0_DSS_12 0x0000000B |
#define | SSI_CR0_DSS_13 0x0000000C |
#define | SSI_CR0_DSS_14 0x0000000D |
#define | SSI_CR0_DSS_15 0x0000000E |
#define | SSI_CR0_DSS_16 0x0000000F |
#define | SSI_CR0_SCR_S 8 |
#define | SSI_CR1_EOM 0x00000800 |
#define | SSI_CR1_FSSHLDFRM 0x00000400 |
#define | SSI_CR1_HSCLKEN 0x00000200 |
#define | SSI_CR1_DIR 0x00000100 |
#define | SSI_CR1_MODE_M 0x000000C0 |
#define | SSI_CR1_MODE_LEGACY 0x00000000 |
#define | SSI_CR1_MODE_BI 0x00000040 |
#define | SSI_CR1_MODE_QUAD 0x00000080 |
#define | SSI_CR1_MODE_ADVANCED 0x000000C0 |
#define | SSI_CR1_MS 0x00000004 |
#define | SSI_CR1_SSE 0x00000002 |
#define | SSI_CR1_LBM 0x00000001 |
#define | SSI_DR_DATA_M 0x0000FFFF |
#define | SSI_DR_DATA_S 0 |
#define | SSI_SR_BSY 0x00000010 |
#define | SSI_SR_RFF 0x00000008 |
#define | SSI_SR_RNE 0x00000004 |
#define | SSI_SR_TNF 0x00000002 |
#define | SSI_SR_TFE 0x00000001 |
#define | SSI_CPSR_CPSDVSR_M 0x000000FF |
#define | SSI_CPSR_CPSDVSR_S 0 |
#define | SSI_IM_EOTIM 0x00000040 |
#define | SSI_IM_DMATXIM 0x00000020 |
#define | SSI_IM_DMARXIM 0x00000010 |
#define | SSI_IM_TXIM 0x00000008 |
#define | SSI_IM_RXIM 0x00000004 |
#define | SSI_IM_RTIM 0x00000002 |
#define | SSI_IM_RORIM 0x00000001 |
#define | SSI_RIS_EOTRIS 0x00000040 |
#define | SSI_RIS_DMATXRIS 0x00000020 |
#define | SSI_RIS_DMARXRIS 0x00000010 |
#define | SSI_RIS_TXRIS 0x00000008 |
#define | SSI_RIS_RXRIS 0x00000004 |
#define | SSI_RIS_RTRIS 0x00000002 |
#define | SSI_RIS_RORRIS 0x00000001 |
#define | SSI_MIS_EOTMIS 0x00000040 |
#define | SSI_MIS_DMATXMIS 0x00000020 |
#define | SSI_MIS_DMARXMIS 0x00000010 |
#define | SSI_MIS_TXMIS 0x00000008 |
#define | SSI_MIS_RXMIS 0x00000004 |
#define | SSI_MIS_RTMIS 0x00000002 |
#define | SSI_MIS_RORMIS 0x00000001 |
#define | SSI_ICR_EOTIC 0x00000040 |
#define | SSI_ICR_DMATXIC 0x00000020 |
#define | SSI_ICR_DMARXIC 0x00000010 |
#define | SSI_ICR_RTIC 0x00000002 |
#define | SSI_ICR_RORIC 0x00000001 |
#define | SSI_DMACTL_TXDMAE 0x00000002 |
#define | SSI_DMACTL_RXDMAE 0x00000001 |
#define | SSI_PP_FSSHLDFRM 0x00000008 |
#define | SSI_PP_MODE_M 0x00000006 |
#define | SSI_PP_MODE_LEGACY 0x00000000 |
#define | SSI_PP_MODE_ADVBI 0x00000002 |
#define | SSI_PP_MODE_ADVBIQUAD 0x00000004 |
#define | SSI_PP_HSCLK 0x00000001 |
#define | SSI_CC_CS_M 0x0000000F |
#define | SSI_CC_CS_SYSPLL 0x00000000 |
#define | SSI_CC_CS_ALTCLK 0x00000005 |
#define SSI_O_CR0 0x00000000 |
Referenced by SSIConfigSetExpClk(), SSIDataPut(), and SSIDataPutNonBlocking().
#define SSI_O_CR1 0x00000004 |
#define SSI_O_DR 0x00000008 |
#define SSI_O_SR 0x0000000C |
#define SSI_O_CPSR 0x00000010 |
Referenced by SSIConfigSetExpClk().
#define SSI_O_IM 0x00000014 |
Referenced by SSIIntDisable(), and SSIIntEnable().
#define SSI_O_RIS 0x00000018 |
Referenced by SSIIntStatus().
#define SSI_O_MIS 0x0000001C |
Referenced by SSIIntStatus().
#define SSI_O_ICR 0x00000020 |
Referenced by SSIIntClear().
#define SSI_O_DMACTL 0x00000024 |
Referenced by SSIDMADisable(), and SSIDMAEnable().
#define SSI_O_PP 0x00000FC0 |
#define SSI_O_CC 0x00000FC8 |
Referenced by SSIClockSourceGet(), and SSIClockSourceSet().
#define SSI_CR0_SCR_M 0x0000FF00 |
#define SSI_CR0_SPH 0x00000080 |
#define SSI_CR0_SPO 0x00000040 |
#define SSI_CR0_FRF_M 0x00000030 |
Referenced by SSIConfigSetExpClk().
#define SSI_CR0_FRF_MOTO 0x00000000 |
#define SSI_CR0_FRF_TI 0x00000010 |
#define SSI_CR0_DSS_M 0x0000000F |
Referenced by SSIDataPut(), and SSIDataPutNonBlocking().
#define SSI_CR0_DSS_4 0x00000003 |
#define SSI_CR0_DSS_5 0x00000004 |
#define SSI_CR0_DSS_6 0x00000005 |
#define SSI_CR0_DSS_7 0x00000006 |
#define SSI_CR0_DSS_8 0x00000007 |
#define SSI_CR0_DSS_9 0x00000008 |
#define SSI_CR0_DSS_10 0x00000009 |
#define SSI_CR0_DSS_11 0x0000000A |
#define SSI_CR0_DSS_12 0x0000000B |
#define SSI_CR0_DSS_13 0x0000000C |
#define SSI_CR0_DSS_14 0x0000000D |
#define SSI_CR0_DSS_15 0x0000000E |
#define SSI_CR0_DSS_16 0x0000000F |
#define SSI_CR0_SCR_S 8 |
#define SSI_CR1_EOM 0x00000800 |
Referenced by SSIAdvDataPutFrameEnd(), and SSIAdvDataPutFrameEndNonBlocking().
#define SSI_CR1_FSSHLDFRM 0x00000400 |
Referenced by SSIAdvFrameHoldDisable(), and SSIAdvFrameHoldEnable().
#define SSI_CR1_HSCLKEN 0x00000200 |
#define SSI_CR1_DIR 0x00000100 |
Referenced by SSIAdvModeSet().
#define SSI_CR1_MODE_M 0x000000C0 |
Referenced by SSIAdvModeSet().
#define SSI_CR1_MODE_LEGACY 0x00000000 |
#define SSI_CR1_MODE_BI 0x00000040 |
#define SSI_CR1_MODE_QUAD 0x00000080 |
#define SSI_CR1_MODE_ADVANCED 0x000000C0 |
#define SSI_CR1_MS 0x00000004 |
Referenced by SSIConfigSetExpClk().
#define SSI_CR1_SSE 0x00000002 |
Referenced by SSIDisable(), and SSIEnable().
#define SSI_CR1_LBM 0x00000001 |
#define SSI_DR_DATA_M 0x0000FFFF |
#define SSI_DR_DATA_S 0 |
#define SSI_SR_BSY 0x00000010 |
Referenced by SSIBusy().
#define SSI_SR_RFF 0x00000008 |
#define SSI_SR_RNE 0x00000004 |
Referenced by SSIDataGet(), and SSIDataGetNonBlocking().
#define SSI_SR_TNF 0x00000002 |
Referenced by SSIAdvDataPutFrameEnd(), SSIAdvDataPutFrameEndNonBlocking(), SSIDataPut(), and SSIDataPutNonBlocking().
#define SSI_SR_TFE 0x00000001 |
#define SSI_CPSR_CPSDVSR_M 0x000000FF |
#define SSI_CPSR_CPSDVSR_S 0 |
#define SSI_IM_EOTIM 0x00000040 |
#define SSI_IM_DMATXIM 0x00000020 |
#define SSI_IM_DMARXIM 0x00000010 |
#define SSI_IM_TXIM 0x00000008 |
#define SSI_IM_RXIM 0x00000004 |
#define SSI_IM_RTIM 0x00000002 |
#define SSI_IM_RORIM 0x00000001 |
#define SSI_RIS_EOTRIS 0x00000040 |
#define SSI_RIS_DMATXRIS 0x00000020 |
#define SSI_RIS_DMARXRIS 0x00000010 |
#define SSI_RIS_TXRIS 0x00000008 |
#define SSI_RIS_RXRIS 0x00000004 |
#define SSI_RIS_RTRIS 0x00000002 |
#define SSI_RIS_RORRIS 0x00000001 |
#define SSI_MIS_EOTMIS 0x00000040 |
#define SSI_MIS_DMATXMIS 0x00000020 |
#define SSI_MIS_DMARXMIS 0x00000010 |
#define SSI_MIS_TXMIS 0x00000008 |
#define SSI_MIS_RXMIS 0x00000004 |
#define SSI_MIS_RTMIS 0x00000002 |
#define SSI_MIS_RORMIS 0x00000001 |
#define SSI_ICR_EOTIC 0x00000040 |
#define SSI_ICR_DMATXIC 0x00000020 |
#define SSI_ICR_DMARXIC 0x00000010 |
#define SSI_ICR_RTIC 0x00000002 |
#define SSI_ICR_RORIC 0x00000001 |
#define SSI_DMACTL_TXDMAE 0x00000002 |
#define SSI_DMACTL_RXDMAE 0x00000001 |
#define SSI_PP_FSSHLDFRM 0x00000008 |
#define SSI_PP_MODE_M 0x00000006 |
#define SSI_PP_MODE_LEGACY 0x00000000 |
#define SSI_PP_MODE_ADVBI 0x00000002 |
#define SSI_PP_MODE_ADVBIQUAD 0x00000004 |
#define SSI_PP_HSCLK 0x00000001 |
#define SSI_CC_CS_M 0x0000000F |
#define SSI_CC_CS_SYSPLL 0x00000000 |
#define SSI_CC_CS_ALTCLK 0x00000005 |