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Macros | |
#define | PWM_O_CTL 0x00000000 |
#define | PWM_O_SYNC 0x00000004 |
#define | PWM_O_ENABLE 0x00000008 |
#define | PWM_O_INVERT 0x0000000C |
#define | PWM_O_FAULT 0x00000010 |
#define | PWM_O_INTEN 0x00000014 |
#define | PWM_O_RIS 0x00000018 |
#define | PWM_O_ISC 0x0000001C |
#define | PWM_O_STATUS 0x00000020 |
#define | PWM_O_FAULTVAL 0x00000024 |
#define | PWM_O_ENUPD 0x00000028 |
#define | PWM_O_0_CTL 0x00000040 |
#define | PWM_O_0_INTEN 0x00000044 |
#define | PWM_O_0_RIS 0x00000048 |
#define | PWM_O_0_ISC 0x0000004C |
#define | PWM_O_0_LOAD 0x00000050 |
#define | PWM_O_0_COUNT 0x00000054 |
#define | PWM_O_0_CMPA 0x00000058 |
#define | PWM_O_0_CMPB 0x0000005C |
#define | PWM_O_0_GENA 0x00000060 |
#define | PWM_O_0_GENB 0x00000064 |
#define | PWM_O_0_DBCTL 0x00000068 |
#define | PWM_O_0_DBRISE 0x0000006C |
#define | PWM_O_0_DBFALL 0x00000070 |
#define | PWM_O_0_FLTSRC0 0x00000074 |
#define | PWM_O_0_FLTSRC1 0x00000078 |
#define | PWM_O_0_MINFLTPER 0x0000007C |
#define | PWM_O_1_CTL 0x00000080 |
#define | PWM_O_1_INTEN 0x00000084 |
#define | PWM_O_1_RIS 0x00000088 |
#define | PWM_O_1_ISC 0x0000008C |
#define | PWM_O_1_LOAD 0x00000090 |
#define | PWM_O_1_COUNT 0x00000094 |
#define | PWM_O_1_CMPA 0x00000098 |
#define | PWM_O_1_CMPB 0x0000009C |
#define | PWM_O_1_GENA 0x000000A0 |
#define | PWM_O_1_GENB 0x000000A4 |
#define | PWM_O_1_DBCTL 0x000000A8 |
#define | PWM_O_1_DBRISE 0x000000AC |
#define | PWM_O_1_DBFALL 0x000000B0 |
#define | PWM_O_1_FLTSRC0 0x000000B4 |
#define | PWM_O_1_FLTSRC1 0x000000B8 |
#define | PWM_O_1_MINFLTPER 0x000000BC |
#define | PWM_O_2_CTL 0x000000C0 |
#define | PWM_O_2_INTEN 0x000000C4 |
#define | PWM_O_2_RIS 0x000000C8 |
#define | PWM_O_2_ISC 0x000000CC |
#define | PWM_O_2_LOAD 0x000000D0 |
#define | PWM_O_2_COUNT 0x000000D4 |
#define | PWM_O_2_CMPA 0x000000D8 |
#define | PWM_O_2_CMPB 0x000000DC |
#define | PWM_O_2_GENA 0x000000E0 |
#define | PWM_O_2_GENB 0x000000E4 |
#define | PWM_O_2_DBCTL 0x000000E8 |
#define | PWM_O_2_DBRISE 0x000000EC |
#define | PWM_O_2_DBFALL 0x000000F0 |
#define | PWM_O_2_FLTSRC0 0x000000F4 |
#define | PWM_O_2_FLTSRC1 0x000000F8 |
#define | PWM_O_2_MINFLTPER 0x000000FC |
#define | PWM_O_3_CTL 0x00000100 |
#define | PWM_O_3_INTEN 0x00000104 |
#define | PWM_O_3_RIS 0x00000108 |
#define | PWM_O_3_ISC 0x0000010C |
#define | PWM_O_3_LOAD 0x00000110 |
#define | PWM_O_3_COUNT 0x00000114 |
#define | PWM_O_3_CMPA 0x00000118 |
#define | PWM_O_3_CMPB 0x0000011C |
#define | PWM_O_3_GENA 0x00000120 |
#define | PWM_O_3_GENB 0x00000124 |
#define | PWM_O_3_DBCTL 0x00000128 |
#define | PWM_O_3_DBRISE 0x0000012C |
#define | PWM_O_3_DBFALL 0x00000130 |
#define | PWM_O_3_FLTSRC0 0x00000134 |
#define | PWM_O_3_FLTSRC1 0x00000138 |
#define | PWM_O_3_MINFLTPER 0x0000013C |
#define | PWM_O_0_FLTSEN 0x00000800 |
#define | PWM_O_0_FLTSTAT0 0x00000804 |
#define | PWM_O_0_FLTSTAT1 0x00000808 |
#define | PWM_O_1_FLTSEN 0x00000880 |
#define | PWM_O_1_FLTSTAT0 0x00000884 |
#define | PWM_O_1_FLTSTAT1 0x00000888 |
#define | PWM_O_2_FLTSEN 0x00000900 |
#define | PWM_O_2_FLTSTAT0 0x00000904 |
#define | PWM_O_2_FLTSTAT1 0x00000908 |
#define | PWM_O_3_FLTSEN 0x00000980 |
#define | PWM_O_3_FLTSTAT0 0x00000984 |
#define | PWM_O_3_FLTSTAT1 0x00000988 |
#define | PWM_O_PP 0x00000FC0 |
#define | PWM_O_CC 0x00000FC8 |
#define | PWM_CTL_GLOBALSYNC3 0x00000008 |
#define | PWM_CTL_GLOBALSYNC2 0x00000004 |
#define | PWM_CTL_GLOBALSYNC1 0x00000002 |
#define | PWM_CTL_GLOBALSYNC0 0x00000001 |
#define | PWM_SYNC_SYNC3 0x00000008 |
#define | PWM_SYNC_SYNC2 0x00000004 |
#define | PWM_SYNC_SYNC1 0x00000002 |
#define | PWM_SYNC_SYNC0 0x00000001 |
#define | PWM_ENABLE_PWM7EN 0x00000080 |
#define | PWM_ENABLE_PWM6EN 0x00000040 |
#define | PWM_ENABLE_PWM5EN 0x00000020 |
#define | PWM_ENABLE_PWM4EN 0x00000010 |
#define | PWM_ENABLE_PWM3EN 0x00000008 |
#define | PWM_ENABLE_PWM2EN 0x00000004 |
#define | PWM_ENABLE_PWM1EN 0x00000002 |
#define | PWM_ENABLE_PWM0EN 0x00000001 |
#define | PWM_INVERT_PWM7INV 0x00000080 |
#define | PWM_INVERT_PWM6INV 0x00000040 |
#define | PWM_INVERT_PWM5INV 0x00000020 |
#define | PWM_INVERT_PWM4INV 0x00000010 |
#define | PWM_INVERT_PWM3INV 0x00000008 |
#define | PWM_INVERT_PWM2INV 0x00000004 |
#define | PWM_INVERT_PWM1INV 0x00000002 |
#define | PWM_INVERT_PWM0INV 0x00000001 |
#define | PWM_FAULT_FAULT7 0x00000080 |
#define | PWM_FAULT_FAULT6 0x00000040 |
#define | PWM_FAULT_FAULT5 0x00000020 |
#define | PWM_FAULT_FAULT4 0x00000010 |
#define | PWM_FAULT_FAULT3 0x00000008 |
#define | PWM_FAULT_FAULT2 0x00000004 |
#define | PWM_FAULT_FAULT1 0x00000002 |
#define | PWM_FAULT_FAULT0 0x00000001 |
#define | PWM_INTEN_INTFAULT3 0x00080000 |
#define | PWM_INTEN_INTFAULT2 0x00040000 |
#define | PWM_INTEN_INTFAULT1 0x00020000 |
#define | PWM_INTEN_INTFAULT0 0x00010000 |
#define | PWM_INTEN_INTPWM3 0x00000008 |
#define | PWM_INTEN_INTPWM2 0x00000004 |
#define | PWM_INTEN_INTPWM1 0x00000002 |
#define | PWM_INTEN_INTPWM0 0x00000001 |
#define | PWM_RIS_INTFAULT3 0x00080000 |
#define | PWM_RIS_INTFAULT2 0x00040000 |
#define | PWM_RIS_INTFAULT1 0x00020000 |
#define | PWM_RIS_INTFAULT0 0x00010000 |
#define | PWM_RIS_INTPWM3 0x00000008 |
#define | PWM_RIS_INTPWM2 0x00000004 |
#define | PWM_RIS_INTPWM1 0x00000002 |
#define | PWM_RIS_INTPWM0 0x00000001 |
#define | PWM_ISC_INTFAULT3 0x00080000 |
#define | PWM_ISC_INTFAULT2 0x00040000 |
#define | PWM_ISC_INTFAULT1 0x00020000 |
#define | PWM_ISC_INTFAULT0 0x00010000 |
#define | PWM_ISC_INTPWM3 0x00000008 |
#define | PWM_ISC_INTPWM2 0x00000004 |
#define | PWM_ISC_INTPWM1 0x00000002 |
#define | PWM_ISC_INTPWM0 0x00000001 |
#define | PWM_STATUS_FAULT3 0x00000008 |
#define | PWM_STATUS_FAULT2 0x00000004 |
#define | PWM_STATUS_FAULT1 0x00000002 |
#define | PWM_STATUS_FAULT0 0x00000001 |
#define | PWM_FAULTVAL_PWM7 0x00000080 |
#define | PWM_FAULTVAL_PWM6 0x00000040 |
#define | PWM_FAULTVAL_PWM5 0x00000020 |
#define | PWM_FAULTVAL_PWM4 0x00000010 |
#define | PWM_FAULTVAL_PWM3 0x00000008 |
#define | PWM_FAULTVAL_PWM2 0x00000004 |
#define | PWM_FAULTVAL_PWM1 0x00000002 |
#define | PWM_FAULTVAL_PWM0 0x00000001 |
#define | PWM_ENUPD_ENUPD7_M 0x0000C000 |
#define | PWM_ENUPD_ENUPD7_IMM 0x00000000 |
#define | PWM_ENUPD_ENUPD7_LSYNC 0x00008000 |
#define | PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 |
#define | PWM_ENUPD_ENUPD6_M 0x00003000 |
#define | PWM_ENUPD_ENUPD6_IMM 0x00000000 |
#define | PWM_ENUPD_ENUPD6_LSYNC 0x00002000 |
#define | PWM_ENUPD_ENUPD6_GSYNC 0x00003000 |
#define | PWM_ENUPD_ENUPD5_M 0x00000C00 |
#define | PWM_ENUPD_ENUPD5_IMM 0x00000000 |
#define | PWM_ENUPD_ENUPD5_LSYNC 0x00000800 |
#define | PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 |
#define | PWM_ENUPD_ENUPD4_M 0x00000300 |
#define | PWM_ENUPD_ENUPD4_IMM 0x00000000 |
#define | PWM_ENUPD_ENUPD4_LSYNC 0x00000200 |
#define | PWM_ENUPD_ENUPD4_GSYNC 0x00000300 |
#define | PWM_ENUPD_ENUPD3_M 0x000000C0 |
#define | PWM_ENUPD_ENUPD3_IMM 0x00000000 |
#define | PWM_ENUPD_ENUPD3_LSYNC 0x00000080 |
#define | PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 |
#define | PWM_ENUPD_ENUPD2_M 0x00000030 |
#define | PWM_ENUPD_ENUPD2_IMM 0x00000000 |
#define | PWM_ENUPD_ENUPD2_LSYNC 0x00000020 |
#define | PWM_ENUPD_ENUPD2_GSYNC 0x00000030 |
#define | PWM_ENUPD_ENUPD1_M 0x0000000C |
#define | PWM_ENUPD_ENUPD1_IMM 0x00000000 |
#define | PWM_ENUPD_ENUPD1_LSYNC 0x00000008 |
#define | PWM_ENUPD_ENUPD1_GSYNC 0x0000000C |
#define | PWM_ENUPD_ENUPD0_M 0x00000003 |
#define | PWM_ENUPD_ENUPD0_IMM 0x00000000 |
#define | PWM_ENUPD_ENUPD0_LSYNC 0x00000002 |
#define | PWM_ENUPD_ENUPD0_GSYNC 0x00000003 |
#define | PWM_0_CTL_LATCH 0x00040000 |
#define | PWM_0_CTL_MINFLTPER 0x00020000 |
#define | PWM_0_CTL_FLTSRC 0x00010000 |
#define | PWM_0_CTL_DBFALLUPD_M 0x0000C000 |
#define | PWM_0_CTL_DBFALLUPD_I 0x00000000 |
#define | PWM_0_CTL_DBFALLUPD_LS 0x00008000 |
#define | PWM_0_CTL_DBFALLUPD_GS 0x0000C000 |
#define | PWM_0_CTL_DBRISEUPD_M 0x00003000 |
#define | PWM_0_CTL_DBRISEUPD_I 0x00000000 |
#define | PWM_0_CTL_DBRISEUPD_LS 0x00002000 |
#define | PWM_0_CTL_DBRISEUPD_GS 0x00003000 |
#define | PWM_0_CTL_DBCTLUPD_M 0x00000C00 |
#define | PWM_0_CTL_DBCTLUPD_I 0x00000000 |
#define | PWM_0_CTL_DBCTLUPD_LS 0x00000800 |
#define | PWM_0_CTL_DBCTLUPD_GS 0x00000C00 |
#define | PWM_0_CTL_GENBUPD_M 0x00000300 |
#define | PWM_0_CTL_GENBUPD_I 0x00000000 |
#define | PWM_0_CTL_GENBUPD_LS 0x00000200 |
#define | PWM_0_CTL_GENBUPD_GS 0x00000300 |
#define | PWM_0_CTL_GENAUPD_M 0x000000C0 |
#define | PWM_0_CTL_GENAUPD_I 0x00000000 |
#define | PWM_0_CTL_GENAUPD_LS 0x00000080 |
#define | PWM_0_CTL_GENAUPD_GS 0x000000C0 |
#define | PWM_0_CTL_CMPBUPD 0x00000020 |
#define | PWM_0_CTL_CMPAUPD 0x00000010 |
#define | PWM_0_CTL_LOADUPD 0x00000008 |
#define | PWM_0_CTL_DEBUG 0x00000004 |
#define | PWM_0_CTL_MODE 0x00000002 |
#define | PWM_0_CTL_ENABLE 0x00000001 |
#define | PWM_0_INTEN_TRCMPBD 0x00002000 |
#define | PWM_0_INTEN_TRCMPBU 0x00001000 |
#define | PWM_0_INTEN_TRCMPAD 0x00000800 |
#define | PWM_0_INTEN_TRCMPAU 0x00000400 |
#define | PWM_0_INTEN_TRCNTLOAD 0x00000200 |
#define | PWM_0_INTEN_TRCNTZERO 0x00000100 |
#define | PWM_0_INTEN_INTCMPBD 0x00000020 |
#define | PWM_0_INTEN_INTCMPBU 0x00000010 |
#define | PWM_0_INTEN_INTCMPAD 0x00000008 |
#define | PWM_0_INTEN_INTCMPAU 0x00000004 |
#define | PWM_0_INTEN_INTCNTLOAD 0x00000002 |
#define | PWM_0_INTEN_INTCNTZERO 0x00000001 |
#define | PWM_0_RIS_INTCMPBD 0x00000020 |
#define | PWM_0_RIS_INTCMPBU 0x00000010 |
#define | PWM_0_RIS_INTCMPAD 0x00000008 |
#define | PWM_0_RIS_INTCMPAU 0x00000004 |
#define | PWM_0_RIS_INTCNTLOAD 0x00000002 |
#define | PWM_0_RIS_INTCNTZERO 0x00000001 |
#define | PWM_0_ISC_INTCMPBD 0x00000020 |
#define | PWM_0_ISC_INTCMPBU 0x00000010 |
#define | PWM_0_ISC_INTCMPAD 0x00000008 |
#define | PWM_0_ISC_INTCMPAU 0x00000004 |
#define | PWM_0_ISC_INTCNTLOAD 0x00000002 |
#define | PWM_0_ISC_INTCNTZERO 0x00000001 |
#define | PWM_0_LOAD_M 0x0000FFFF |
#define | PWM_0_LOAD_S 0 |
#define | PWM_0_COUNT_M 0x0000FFFF |
#define | PWM_0_COUNT_S 0 |
#define | PWM_0_CMPA_M 0x0000FFFF |
#define | PWM_0_CMPA_S 0 |
#define | PWM_0_CMPB_M 0x0000FFFF |
#define | PWM_0_CMPB_S 0 |
#define | PWM_0_GENA_ACTCMPBD_M 0x00000C00 |
#define | PWM_0_GENA_ACTCMPBD_NONE 0x00000000 |
#define | PWM_0_GENA_ACTCMPBD_INV 0x00000400 |
#define | PWM_0_GENA_ACTCMPBD_ZERO 0x00000800 |
#define | PWM_0_GENA_ACTCMPBD_ONE 0x00000C00 |
#define | PWM_0_GENA_ACTCMPBU_M 0x00000300 |
#define | PWM_0_GENA_ACTCMPBU_NONE 0x00000000 |
#define | PWM_0_GENA_ACTCMPBU_INV 0x00000100 |
#define | PWM_0_GENA_ACTCMPBU_ZERO 0x00000200 |
#define | PWM_0_GENA_ACTCMPBU_ONE 0x00000300 |
#define | PWM_0_GENA_ACTCMPAD_M 0x000000C0 |
#define | PWM_0_GENA_ACTCMPAD_NONE 0x00000000 |
#define | PWM_0_GENA_ACTCMPAD_INV 0x00000040 |
#define | PWM_0_GENA_ACTCMPAD_ZERO 0x00000080 |
#define | PWM_0_GENA_ACTCMPAD_ONE 0x000000C0 |
#define | PWM_0_GENA_ACTCMPAU_M 0x00000030 |
#define | PWM_0_GENA_ACTCMPAU_NONE 0x00000000 |
#define | PWM_0_GENA_ACTCMPAU_INV 0x00000010 |
#define | PWM_0_GENA_ACTCMPAU_ZERO 0x00000020 |
#define | PWM_0_GENA_ACTCMPAU_ONE 0x00000030 |
#define | PWM_0_GENA_ACTLOAD_M 0x0000000C |
#define | PWM_0_GENA_ACTLOAD_NONE 0x00000000 |
#define | PWM_0_GENA_ACTLOAD_INV 0x00000004 |
#define | PWM_0_GENA_ACTLOAD_ZERO 0x00000008 |
#define | PWM_0_GENA_ACTLOAD_ONE 0x0000000C |
#define | PWM_0_GENA_ACTZERO_M 0x00000003 |
#define | PWM_0_GENA_ACTZERO_NONE 0x00000000 |
#define | PWM_0_GENA_ACTZERO_INV 0x00000001 |
#define | PWM_0_GENA_ACTZERO_ZERO 0x00000002 |
#define | PWM_0_GENA_ACTZERO_ONE 0x00000003 |
#define | PWM_0_GENB_ACTCMPBD_M 0x00000C00 |
#define | PWM_0_GENB_ACTCMPBD_NONE 0x00000000 |
#define | PWM_0_GENB_ACTCMPBD_INV 0x00000400 |
#define | PWM_0_GENB_ACTCMPBD_ZERO 0x00000800 |
#define | PWM_0_GENB_ACTCMPBD_ONE 0x00000C00 |
#define | PWM_0_GENB_ACTCMPBU_M 0x00000300 |
#define | PWM_0_GENB_ACTCMPBU_NONE 0x00000000 |
#define | PWM_0_GENB_ACTCMPBU_INV 0x00000100 |
#define | PWM_0_GENB_ACTCMPBU_ZERO 0x00000200 |
#define | PWM_0_GENB_ACTCMPBU_ONE 0x00000300 |
#define | PWM_0_GENB_ACTCMPAD_M 0x000000C0 |
#define | PWM_0_GENB_ACTCMPAD_NONE 0x00000000 |
#define | PWM_0_GENB_ACTCMPAD_INV 0x00000040 |
#define | PWM_0_GENB_ACTCMPAD_ZERO 0x00000080 |
#define | PWM_0_GENB_ACTCMPAD_ONE 0x000000C0 |
#define | PWM_0_GENB_ACTCMPAU_M 0x00000030 |
#define | PWM_0_GENB_ACTCMPAU_NONE 0x00000000 |
#define | PWM_0_GENB_ACTCMPAU_INV 0x00000010 |
#define | PWM_0_GENB_ACTCMPAU_ZERO 0x00000020 |
#define | PWM_0_GENB_ACTCMPAU_ONE 0x00000030 |
#define | PWM_0_GENB_ACTLOAD_M 0x0000000C |
#define | PWM_0_GENB_ACTLOAD_NONE 0x00000000 |
#define | PWM_0_GENB_ACTLOAD_INV 0x00000004 |
#define | PWM_0_GENB_ACTLOAD_ZERO 0x00000008 |
#define | PWM_0_GENB_ACTLOAD_ONE 0x0000000C |
#define | PWM_0_GENB_ACTZERO_M 0x00000003 |
#define | PWM_0_GENB_ACTZERO_NONE 0x00000000 |
#define | PWM_0_GENB_ACTZERO_INV 0x00000001 |
#define | PWM_0_GENB_ACTZERO_ZERO 0x00000002 |
#define | PWM_0_GENB_ACTZERO_ONE 0x00000003 |
#define | PWM_0_DBCTL_ENABLE 0x00000001 |
#define | PWM_0_DBRISE_DELAY_M 0x00000FFF |
#define | PWM_0_DBRISE_DELAY_S 0 |
#define | PWM_0_DBFALL_DELAY_M 0x00000FFF |
#define | PWM_0_DBFALL_DELAY_S 0 |
#define | PWM_0_FLTSRC0_FAULT3 0x00000008 |
#define | PWM_0_FLTSRC0_FAULT2 0x00000004 |
#define | PWM_0_FLTSRC0_FAULT1 0x00000002 |
#define | PWM_0_FLTSRC0_FAULT0 0x00000001 |
#define | PWM_0_FLTSRC1_DCMP7 0x00000080 |
#define | PWM_0_FLTSRC1_DCMP6 0x00000040 |
#define | PWM_0_FLTSRC1_DCMP5 0x00000020 |
#define | PWM_0_FLTSRC1_DCMP4 0x00000010 |
#define | PWM_0_FLTSRC1_DCMP3 0x00000008 |
#define | PWM_0_FLTSRC1_DCMP2 0x00000004 |
#define | PWM_0_FLTSRC1_DCMP1 0x00000002 |
#define | PWM_0_FLTSRC1_DCMP0 0x00000001 |
#define | PWM_0_MINFLTPER_M 0x0000FFFF |
#define | PWM_0_MINFLTPER_S 0 |
#define | PWM_1_CTL_LATCH 0x00040000 |
#define | PWM_1_CTL_MINFLTPER 0x00020000 |
#define | PWM_1_CTL_FLTSRC 0x00010000 |
#define | PWM_1_CTL_DBFALLUPD_M 0x0000C000 |
#define | PWM_1_CTL_DBFALLUPD_I 0x00000000 |
#define | PWM_1_CTL_DBFALLUPD_LS 0x00008000 |
#define | PWM_1_CTL_DBFALLUPD_GS 0x0000C000 |
#define | PWM_1_CTL_DBRISEUPD_M 0x00003000 |
#define | PWM_1_CTL_DBRISEUPD_I 0x00000000 |
#define | PWM_1_CTL_DBRISEUPD_LS 0x00002000 |
#define | PWM_1_CTL_DBRISEUPD_GS 0x00003000 |
#define | PWM_1_CTL_DBCTLUPD_M 0x00000C00 |
#define | PWM_1_CTL_DBCTLUPD_I 0x00000000 |
#define | PWM_1_CTL_DBCTLUPD_LS 0x00000800 |
#define | PWM_1_CTL_DBCTLUPD_GS 0x00000C00 |
#define | PWM_1_CTL_GENBUPD_M 0x00000300 |
#define | PWM_1_CTL_GENBUPD_I 0x00000000 |
#define | PWM_1_CTL_GENBUPD_LS 0x00000200 |
#define | PWM_1_CTL_GENBUPD_GS 0x00000300 |
#define | PWM_1_CTL_GENAUPD_M 0x000000C0 |
#define | PWM_1_CTL_GENAUPD_I 0x00000000 |
#define | PWM_1_CTL_GENAUPD_LS 0x00000080 |
#define | PWM_1_CTL_GENAUPD_GS 0x000000C0 |
#define | PWM_1_CTL_CMPBUPD 0x00000020 |
#define | PWM_1_CTL_CMPAUPD 0x00000010 |
#define | PWM_1_CTL_LOADUPD 0x00000008 |
#define | PWM_1_CTL_DEBUG 0x00000004 |
#define | PWM_1_CTL_MODE 0x00000002 |
#define | PWM_1_CTL_ENABLE 0x00000001 |
#define | PWM_1_INTEN_TRCMPBD 0x00002000 |
#define | PWM_1_INTEN_TRCMPBU 0x00001000 |
#define | PWM_1_INTEN_TRCMPAD 0x00000800 |
#define | PWM_1_INTEN_TRCMPAU 0x00000400 |
#define | PWM_1_INTEN_TRCNTLOAD 0x00000200 |
#define | PWM_1_INTEN_TRCNTZERO 0x00000100 |
#define | PWM_1_INTEN_INTCMPBD 0x00000020 |
#define | PWM_1_INTEN_INTCMPBU 0x00000010 |
#define | PWM_1_INTEN_INTCMPAD 0x00000008 |
#define | PWM_1_INTEN_INTCMPAU 0x00000004 |
#define | PWM_1_INTEN_INTCNTLOAD 0x00000002 |
#define | PWM_1_INTEN_INTCNTZERO 0x00000001 |
#define | PWM_1_RIS_INTCMPBD 0x00000020 |
#define | PWM_1_RIS_INTCMPBU 0x00000010 |
#define | PWM_1_RIS_INTCMPAD 0x00000008 |
#define | PWM_1_RIS_INTCMPAU 0x00000004 |
#define | PWM_1_RIS_INTCNTLOAD 0x00000002 |
#define | PWM_1_RIS_INTCNTZERO 0x00000001 |
#define | PWM_1_ISC_INTCMPBD 0x00000020 |
#define | PWM_1_ISC_INTCMPBU 0x00000010 |
#define | PWM_1_ISC_INTCMPAD 0x00000008 |
#define | PWM_1_ISC_INTCMPAU 0x00000004 |
#define | PWM_1_ISC_INTCNTLOAD 0x00000002 |
#define | PWM_1_ISC_INTCNTZERO 0x00000001 |
#define | PWM_1_LOAD_LOAD_M 0x0000FFFF |
#define | PWM_1_LOAD_LOAD_S 0 |
#define | PWM_1_COUNT_COUNT_M 0x0000FFFF |
#define | PWM_1_COUNT_COUNT_S 0 |
#define | PWM_1_CMPA_COMPA_M 0x0000FFFF |
#define | PWM_1_CMPA_COMPA_S 0 |
#define | PWM_1_CMPB_COMPB_M 0x0000FFFF |
#define | PWM_1_CMPB_COMPB_S 0 |
#define | PWM_1_GENA_ACTCMPBD_M 0x00000C00 |
#define | PWM_1_GENA_ACTCMPBD_NONE 0x00000000 |
#define | PWM_1_GENA_ACTCMPBD_INV 0x00000400 |
#define | PWM_1_GENA_ACTCMPBD_ZERO 0x00000800 |
#define | PWM_1_GENA_ACTCMPBD_ONE 0x00000C00 |
#define | PWM_1_GENA_ACTCMPBU_M 0x00000300 |
#define | PWM_1_GENA_ACTCMPBU_NONE 0x00000000 |
#define | PWM_1_GENA_ACTCMPBU_INV 0x00000100 |
#define | PWM_1_GENA_ACTCMPBU_ZERO 0x00000200 |
#define | PWM_1_GENA_ACTCMPBU_ONE 0x00000300 |
#define | PWM_1_GENA_ACTCMPAD_M 0x000000C0 |
#define | PWM_1_GENA_ACTCMPAD_NONE 0x00000000 |
#define | PWM_1_GENA_ACTCMPAD_INV 0x00000040 |
#define | PWM_1_GENA_ACTCMPAD_ZERO 0x00000080 |
#define | PWM_1_GENA_ACTCMPAD_ONE 0x000000C0 |
#define | PWM_1_GENA_ACTCMPAU_M 0x00000030 |
#define | PWM_1_GENA_ACTCMPAU_NONE 0x00000000 |
#define | PWM_1_GENA_ACTCMPAU_INV 0x00000010 |
#define | PWM_1_GENA_ACTCMPAU_ZERO 0x00000020 |
#define | PWM_1_GENA_ACTCMPAU_ONE 0x00000030 |
#define | PWM_1_GENA_ACTLOAD_M 0x0000000C |
#define | PWM_1_GENA_ACTLOAD_NONE 0x00000000 |
#define | PWM_1_GENA_ACTLOAD_INV 0x00000004 |
#define | PWM_1_GENA_ACTLOAD_ZERO 0x00000008 |
#define | PWM_1_GENA_ACTLOAD_ONE 0x0000000C |
#define | PWM_1_GENA_ACTZERO_M 0x00000003 |
#define | PWM_1_GENA_ACTZERO_NONE 0x00000000 |
#define | PWM_1_GENA_ACTZERO_INV 0x00000001 |
#define | PWM_1_GENA_ACTZERO_ZERO 0x00000002 |
#define | PWM_1_GENA_ACTZERO_ONE 0x00000003 |
#define | PWM_1_GENB_ACTCMPBD_M 0x00000C00 |
#define | PWM_1_GENB_ACTCMPBD_NONE 0x00000000 |
#define | PWM_1_GENB_ACTCMPBD_INV 0x00000400 |
#define | PWM_1_GENB_ACTCMPBD_ZERO 0x00000800 |
#define | PWM_1_GENB_ACTCMPBD_ONE 0x00000C00 |
#define | PWM_1_GENB_ACTCMPBU_M 0x00000300 |
#define | PWM_1_GENB_ACTCMPBU_NONE 0x00000000 |
#define | PWM_1_GENB_ACTCMPBU_INV 0x00000100 |
#define | PWM_1_GENB_ACTCMPBU_ZERO 0x00000200 |
#define | PWM_1_GENB_ACTCMPBU_ONE 0x00000300 |
#define | PWM_1_GENB_ACTCMPAD_M 0x000000C0 |
#define | PWM_1_GENB_ACTCMPAD_NONE 0x00000000 |
#define | PWM_1_GENB_ACTCMPAD_INV 0x00000040 |
#define | PWM_1_GENB_ACTCMPAD_ZERO 0x00000080 |
#define | PWM_1_GENB_ACTCMPAD_ONE 0x000000C0 |
#define | PWM_1_GENB_ACTCMPAU_M 0x00000030 |
#define | PWM_1_GENB_ACTCMPAU_NONE 0x00000000 |
#define | PWM_1_GENB_ACTCMPAU_INV 0x00000010 |
#define | PWM_1_GENB_ACTCMPAU_ZERO 0x00000020 |
#define | PWM_1_GENB_ACTCMPAU_ONE 0x00000030 |
#define | PWM_1_GENB_ACTLOAD_M 0x0000000C |
#define | PWM_1_GENB_ACTLOAD_NONE 0x00000000 |
#define | PWM_1_GENB_ACTLOAD_INV 0x00000004 |
#define | PWM_1_GENB_ACTLOAD_ZERO 0x00000008 |
#define | PWM_1_GENB_ACTLOAD_ONE 0x0000000C |
#define | PWM_1_GENB_ACTZERO_M 0x00000003 |
#define | PWM_1_GENB_ACTZERO_NONE 0x00000000 |
#define | PWM_1_GENB_ACTZERO_INV 0x00000001 |
#define | PWM_1_GENB_ACTZERO_ZERO 0x00000002 |
#define | PWM_1_GENB_ACTZERO_ONE 0x00000003 |
#define | PWM_1_DBCTL_ENABLE 0x00000001 |
#define | PWM_1_DBRISE_RISEDELAY_M 0x00000FFF |
#define | PWM_1_DBRISE_RISEDELAY_S 0 |
#define | PWM_1_DBFALL_FALLDELAY_M 0x00000FFF |
#define | PWM_1_DBFALL_FALLDELAY_S 0 |
#define | PWM_1_FLTSRC0_FAULT3 0x00000008 |
#define | PWM_1_FLTSRC0_FAULT2 0x00000004 |
#define | PWM_1_FLTSRC0_FAULT1 0x00000002 |
#define | PWM_1_FLTSRC0_FAULT0 0x00000001 |
#define | PWM_1_FLTSRC1_DCMP7 0x00000080 |
#define | PWM_1_FLTSRC1_DCMP6 0x00000040 |
#define | PWM_1_FLTSRC1_DCMP5 0x00000020 |
#define | PWM_1_FLTSRC1_DCMP4 0x00000010 |
#define | PWM_1_FLTSRC1_DCMP3 0x00000008 |
#define | PWM_1_FLTSRC1_DCMP2 0x00000004 |
#define | PWM_1_FLTSRC1_DCMP1 0x00000002 |
#define | PWM_1_FLTSRC1_DCMP0 0x00000001 |
#define | PWM_1_MINFLTPER_MFP_M 0x0000FFFF |
#define | PWM_1_MINFLTPER_MFP_S 0 |
#define | PWM_2_CTL_LATCH 0x00040000 |
#define | PWM_2_CTL_MINFLTPER 0x00020000 |
#define | PWM_2_CTL_FLTSRC 0x00010000 |
#define | PWM_2_CTL_DBFALLUPD_M 0x0000C000 |
#define | PWM_2_CTL_DBFALLUPD_I 0x00000000 |
#define | PWM_2_CTL_DBFALLUPD_LS 0x00008000 |
#define | PWM_2_CTL_DBFALLUPD_GS 0x0000C000 |
#define | PWM_2_CTL_DBRISEUPD_M 0x00003000 |
#define | PWM_2_CTL_DBRISEUPD_I 0x00000000 |
#define | PWM_2_CTL_DBRISEUPD_LS 0x00002000 |
#define | PWM_2_CTL_DBRISEUPD_GS 0x00003000 |
#define | PWM_2_CTL_DBCTLUPD_M 0x00000C00 |
#define | PWM_2_CTL_DBCTLUPD_I 0x00000000 |
#define | PWM_2_CTL_DBCTLUPD_LS 0x00000800 |
#define | PWM_2_CTL_DBCTLUPD_GS 0x00000C00 |
#define | PWM_2_CTL_GENBUPD_M 0x00000300 |
#define | PWM_2_CTL_GENBUPD_I 0x00000000 |
#define | PWM_2_CTL_GENBUPD_LS 0x00000200 |
#define | PWM_2_CTL_GENBUPD_GS 0x00000300 |
#define | PWM_2_CTL_GENAUPD_M 0x000000C0 |
#define | PWM_2_CTL_GENAUPD_I 0x00000000 |
#define | PWM_2_CTL_GENAUPD_LS 0x00000080 |
#define | PWM_2_CTL_GENAUPD_GS 0x000000C0 |
#define | PWM_2_CTL_CMPBUPD 0x00000020 |
#define | PWM_2_CTL_CMPAUPD 0x00000010 |
#define | PWM_2_CTL_LOADUPD 0x00000008 |
#define | PWM_2_CTL_DEBUG 0x00000004 |
#define | PWM_2_CTL_MODE 0x00000002 |
#define | PWM_2_CTL_ENABLE 0x00000001 |
#define | PWM_2_INTEN_TRCMPBD 0x00002000 |
#define | PWM_2_INTEN_TRCMPBU 0x00001000 |
#define | PWM_2_INTEN_TRCMPAD 0x00000800 |
#define | PWM_2_INTEN_TRCMPAU 0x00000400 |
#define | PWM_2_INTEN_TRCNTLOAD 0x00000200 |
#define | PWM_2_INTEN_TRCNTZERO 0x00000100 |
#define | PWM_2_INTEN_INTCMPBD 0x00000020 |
#define | PWM_2_INTEN_INTCMPBU 0x00000010 |
#define | PWM_2_INTEN_INTCMPAD 0x00000008 |
#define | PWM_2_INTEN_INTCMPAU 0x00000004 |
#define | PWM_2_INTEN_INTCNTLOAD 0x00000002 |
#define | PWM_2_INTEN_INTCNTZERO 0x00000001 |
#define | PWM_2_RIS_INTCMPBD 0x00000020 |
#define | PWM_2_RIS_INTCMPBU 0x00000010 |
#define | PWM_2_RIS_INTCMPAD 0x00000008 |
#define | PWM_2_RIS_INTCMPAU 0x00000004 |
#define | PWM_2_RIS_INTCNTLOAD 0x00000002 |
#define | PWM_2_RIS_INTCNTZERO 0x00000001 |
#define | PWM_2_ISC_INTCMPBD 0x00000020 |
#define | PWM_2_ISC_INTCMPBU 0x00000010 |
#define | PWM_2_ISC_INTCMPAD 0x00000008 |
#define | PWM_2_ISC_INTCMPAU 0x00000004 |
#define | PWM_2_ISC_INTCNTLOAD 0x00000002 |
#define | PWM_2_ISC_INTCNTZERO 0x00000001 |
#define | PWM_2_LOAD_LOAD_M 0x0000FFFF |
#define | PWM_2_LOAD_LOAD_S 0 |
#define | PWM_2_COUNT_COUNT_M 0x0000FFFF |
#define | PWM_2_COUNT_COUNT_S 0 |
#define | PWM_2_CMPA_COMPA_M 0x0000FFFF |
#define | PWM_2_CMPA_COMPA_S 0 |
#define | PWM_2_CMPB_COMPB_M 0x0000FFFF |
#define | PWM_2_CMPB_COMPB_S 0 |
#define | PWM_2_GENA_ACTCMPBD_M 0x00000C00 |
#define | PWM_2_GENA_ACTCMPBD_NONE 0x00000000 |
#define | PWM_2_GENA_ACTCMPBD_INV 0x00000400 |
#define | PWM_2_GENA_ACTCMPBD_ZERO 0x00000800 |
#define | PWM_2_GENA_ACTCMPBD_ONE 0x00000C00 |
#define | PWM_2_GENA_ACTCMPBU_M 0x00000300 |
#define | PWM_2_GENA_ACTCMPBU_NONE 0x00000000 |
#define | PWM_2_GENA_ACTCMPBU_INV 0x00000100 |
#define | PWM_2_GENA_ACTCMPBU_ZERO 0x00000200 |
#define | PWM_2_GENA_ACTCMPBU_ONE 0x00000300 |
#define | PWM_2_GENA_ACTCMPAD_M 0x000000C0 |
#define | PWM_2_GENA_ACTCMPAD_NONE 0x00000000 |
#define | PWM_2_GENA_ACTCMPAD_INV 0x00000040 |
#define | PWM_2_GENA_ACTCMPAD_ZERO 0x00000080 |
#define | PWM_2_GENA_ACTCMPAD_ONE 0x000000C0 |
#define | PWM_2_GENA_ACTCMPAU_M 0x00000030 |
#define | PWM_2_GENA_ACTCMPAU_NONE 0x00000000 |
#define | PWM_2_GENA_ACTCMPAU_INV 0x00000010 |
#define | PWM_2_GENA_ACTCMPAU_ZERO 0x00000020 |
#define | PWM_2_GENA_ACTCMPAU_ONE 0x00000030 |
#define | PWM_2_GENA_ACTLOAD_M 0x0000000C |
#define | PWM_2_GENA_ACTLOAD_NONE 0x00000000 |
#define | PWM_2_GENA_ACTLOAD_INV 0x00000004 |
#define | PWM_2_GENA_ACTLOAD_ZERO 0x00000008 |
#define | PWM_2_GENA_ACTLOAD_ONE 0x0000000C |
#define | PWM_2_GENA_ACTZERO_M 0x00000003 |
#define | PWM_2_GENA_ACTZERO_NONE 0x00000000 |
#define | PWM_2_GENA_ACTZERO_INV 0x00000001 |
#define | PWM_2_GENA_ACTZERO_ZERO 0x00000002 |
#define | PWM_2_GENA_ACTZERO_ONE 0x00000003 |
#define | PWM_2_GENB_ACTCMPBD_M 0x00000C00 |
#define | PWM_2_GENB_ACTCMPBD_NONE 0x00000000 |
#define | PWM_2_GENB_ACTCMPBD_INV 0x00000400 |
#define | PWM_2_GENB_ACTCMPBD_ZERO 0x00000800 |
#define | PWM_2_GENB_ACTCMPBD_ONE 0x00000C00 |
#define | PWM_2_GENB_ACTCMPBU_M 0x00000300 |
#define | PWM_2_GENB_ACTCMPBU_NONE 0x00000000 |
#define | PWM_2_GENB_ACTCMPBU_INV 0x00000100 |
#define | PWM_2_GENB_ACTCMPBU_ZERO 0x00000200 |
#define | PWM_2_GENB_ACTCMPBU_ONE 0x00000300 |
#define | PWM_2_GENB_ACTCMPAD_M 0x000000C0 |
#define | PWM_2_GENB_ACTCMPAD_NONE 0x00000000 |
#define | PWM_2_GENB_ACTCMPAD_INV 0x00000040 |
#define | PWM_2_GENB_ACTCMPAD_ZERO 0x00000080 |
#define | PWM_2_GENB_ACTCMPAD_ONE 0x000000C0 |
#define | PWM_2_GENB_ACTCMPAU_M 0x00000030 |
#define | PWM_2_GENB_ACTCMPAU_NONE 0x00000000 |
#define | PWM_2_GENB_ACTCMPAU_INV 0x00000010 |
#define | PWM_2_GENB_ACTCMPAU_ZERO 0x00000020 |
#define | PWM_2_GENB_ACTCMPAU_ONE 0x00000030 |
#define | PWM_2_GENB_ACTLOAD_M 0x0000000C |
#define | PWM_2_GENB_ACTLOAD_NONE 0x00000000 |
#define | PWM_2_GENB_ACTLOAD_INV 0x00000004 |
#define | PWM_2_GENB_ACTLOAD_ZERO 0x00000008 |
#define | PWM_2_GENB_ACTLOAD_ONE 0x0000000C |
#define | PWM_2_GENB_ACTZERO_M 0x00000003 |
#define | PWM_2_GENB_ACTZERO_NONE 0x00000000 |
#define | PWM_2_GENB_ACTZERO_INV 0x00000001 |
#define | PWM_2_GENB_ACTZERO_ZERO 0x00000002 |
#define | PWM_2_GENB_ACTZERO_ONE 0x00000003 |
#define | PWM_2_DBCTL_ENABLE 0x00000001 |
#define | PWM_2_DBRISE_RISEDELAY_M 0x00000FFF |
#define | PWM_2_DBRISE_RISEDELAY_S 0 |
#define | PWM_2_DBFALL_FALLDELAY_M 0x00000FFF |
#define | PWM_2_DBFALL_FALLDELAY_S 0 |
#define | PWM_2_FLTSRC0_FAULT3 0x00000008 |
#define | PWM_2_FLTSRC0_FAULT2 0x00000004 |
#define | PWM_2_FLTSRC0_FAULT1 0x00000002 |
#define | PWM_2_FLTSRC0_FAULT0 0x00000001 |
#define | PWM_2_FLTSRC1_DCMP7 0x00000080 |
#define | PWM_2_FLTSRC1_DCMP6 0x00000040 |
#define | PWM_2_FLTSRC1_DCMP5 0x00000020 |
#define | PWM_2_FLTSRC1_DCMP4 0x00000010 |
#define | PWM_2_FLTSRC1_DCMP3 0x00000008 |
#define | PWM_2_FLTSRC1_DCMP2 0x00000004 |
#define | PWM_2_FLTSRC1_DCMP1 0x00000002 |
#define | PWM_2_FLTSRC1_DCMP0 0x00000001 |
#define | PWM_2_MINFLTPER_MFP_M 0x0000FFFF |
#define | PWM_2_MINFLTPER_MFP_S 0 |
#define | PWM_3_CTL_LATCH 0x00040000 |
#define | PWM_3_CTL_MINFLTPER 0x00020000 |
#define | PWM_3_CTL_FLTSRC 0x00010000 |
#define | PWM_3_CTL_DBFALLUPD_M 0x0000C000 |
#define | PWM_3_CTL_DBFALLUPD_I 0x00000000 |
#define | PWM_3_CTL_DBFALLUPD_LS 0x00008000 |
#define | PWM_3_CTL_DBFALLUPD_GS 0x0000C000 |
#define | PWM_3_CTL_DBRISEUPD_M 0x00003000 |
#define | PWM_3_CTL_DBRISEUPD_I 0x00000000 |
#define | PWM_3_CTL_DBRISEUPD_LS 0x00002000 |
#define | PWM_3_CTL_DBRISEUPD_GS 0x00003000 |
#define | PWM_3_CTL_DBCTLUPD_M 0x00000C00 |
#define | PWM_3_CTL_DBCTLUPD_I 0x00000000 |
#define | PWM_3_CTL_DBCTLUPD_LS 0x00000800 |
#define | PWM_3_CTL_DBCTLUPD_GS 0x00000C00 |
#define | PWM_3_CTL_GENBUPD_M 0x00000300 |
#define | PWM_3_CTL_GENBUPD_I 0x00000000 |
#define | PWM_3_CTL_GENBUPD_LS 0x00000200 |
#define | PWM_3_CTL_GENBUPD_GS 0x00000300 |
#define | PWM_3_CTL_GENAUPD_M 0x000000C0 |
#define | PWM_3_CTL_GENAUPD_I 0x00000000 |
#define | PWM_3_CTL_GENAUPD_LS 0x00000080 |
#define | PWM_3_CTL_GENAUPD_GS 0x000000C0 |
#define | PWM_3_CTL_CMPBUPD 0x00000020 |
#define | PWM_3_CTL_CMPAUPD 0x00000010 |
#define | PWM_3_CTL_LOADUPD 0x00000008 |
#define | PWM_3_CTL_DEBUG 0x00000004 |
#define | PWM_3_CTL_MODE 0x00000002 |
#define | PWM_3_CTL_ENABLE 0x00000001 |
#define | PWM_3_INTEN_TRCMPBD 0x00002000 |
#define | PWM_3_INTEN_TRCMPBU 0x00001000 |
#define | PWM_3_INTEN_TRCMPAD 0x00000800 |
#define | PWM_3_INTEN_TRCMPAU 0x00000400 |
#define | PWM_3_INTEN_TRCNTLOAD 0x00000200 |
#define | PWM_3_INTEN_TRCNTZERO 0x00000100 |
#define | PWM_3_INTEN_INTCMPBD 0x00000020 |
#define | PWM_3_INTEN_INTCMPBU 0x00000010 |
#define | PWM_3_INTEN_INTCMPAD 0x00000008 |
#define | PWM_3_INTEN_INTCMPAU 0x00000004 |
#define | PWM_3_INTEN_INTCNTLOAD 0x00000002 |
#define | PWM_3_INTEN_INTCNTZERO 0x00000001 |
#define | PWM_3_RIS_INTCMPBD 0x00000020 |
#define | PWM_3_RIS_INTCMPBU 0x00000010 |
#define | PWM_3_RIS_INTCMPAD 0x00000008 |
#define | PWM_3_RIS_INTCMPAU 0x00000004 |
#define | PWM_3_RIS_INTCNTLOAD 0x00000002 |
#define | PWM_3_RIS_INTCNTZERO 0x00000001 |
#define | PWM_3_ISC_INTCMPBD 0x00000020 |
#define | PWM_3_ISC_INTCMPBU 0x00000010 |
#define | PWM_3_ISC_INTCMPAD 0x00000008 |
#define | PWM_3_ISC_INTCMPAU 0x00000004 |
#define | PWM_3_ISC_INTCNTLOAD 0x00000002 |
#define | PWM_3_ISC_INTCNTZERO 0x00000001 |
#define | PWM_3_LOAD_LOAD_M 0x0000FFFF |
#define | PWM_3_LOAD_LOAD_S 0 |
#define | PWM_3_COUNT_COUNT_M 0x0000FFFF |
#define | PWM_3_COUNT_COUNT_S 0 |
#define | PWM_3_CMPA_COMPA_M 0x0000FFFF |
#define | PWM_3_CMPA_COMPA_S 0 |
#define | PWM_3_CMPB_COMPB_M 0x0000FFFF |
#define | PWM_3_CMPB_COMPB_S 0 |
#define | PWM_3_GENA_ACTCMPBD_M 0x00000C00 |
#define | PWM_3_GENA_ACTCMPBD_NONE 0x00000000 |
#define | PWM_3_GENA_ACTCMPBD_INV 0x00000400 |
#define | PWM_3_GENA_ACTCMPBD_ZERO 0x00000800 |
#define | PWM_3_GENA_ACTCMPBD_ONE 0x00000C00 |
#define | PWM_3_GENA_ACTCMPBU_M 0x00000300 |
#define | PWM_3_GENA_ACTCMPBU_NONE 0x00000000 |
#define | PWM_3_GENA_ACTCMPBU_INV 0x00000100 |
#define | PWM_3_GENA_ACTCMPBU_ZERO 0x00000200 |
#define | PWM_3_GENA_ACTCMPBU_ONE 0x00000300 |
#define | PWM_3_GENA_ACTCMPAD_M 0x000000C0 |
#define | PWM_3_GENA_ACTCMPAD_NONE 0x00000000 |
#define | PWM_3_GENA_ACTCMPAD_INV 0x00000040 |
#define | PWM_3_GENA_ACTCMPAD_ZERO 0x00000080 |
#define | PWM_3_GENA_ACTCMPAD_ONE 0x000000C0 |
#define | PWM_3_GENA_ACTCMPAU_M 0x00000030 |
#define | PWM_3_GENA_ACTCMPAU_NONE 0x00000000 |
#define | PWM_3_GENA_ACTCMPAU_INV 0x00000010 |
#define | PWM_3_GENA_ACTCMPAU_ZERO 0x00000020 |
#define | PWM_3_GENA_ACTCMPAU_ONE 0x00000030 |
#define | PWM_3_GENA_ACTLOAD_M 0x0000000C |
#define | PWM_3_GENA_ACTLOAD_NONE 0x00000000 |
#define | PWM_3_GENA_ACTLOAD_INV 0x00000004 |
#define | PWM_3_GENA_ACTLOAD_ZERO 0x00000008 |
#define | PWM_3_GENA_ACTLOAD_ONE 0x0000000C |
#define | PWM_3_GENA_ACTZERO_M 0x00000003 |
#define | PWM_3_GENA_ACTZERO_NONE 0x00000000 |
#define | PWM_3_GENA_ACTZERO_INV 0x00000001 |
#define | PWM_3_GENA_ACTZERO_ZERO 0x00000002 |
#define | PWM_3_GENA_ACTZERO_ONE 0x00000003 |
#define | PWM_3_GENB_ACTCMPBD_M 0x00000C00 |
#define | PWM_3_GENB_ACTCMPBD_NONE 0x00000000 |
#define | PWM_3_GENB_ACTCMPBD_INV 0x00000400 |
#define | PWM_3_GENB_ACTCMPBD_ZERO 0x00000800 |
#define | PWM_3_GENB_ACTCMPBD_ONE 0x00000C00 |
#define | PWM_3_GENB_ACTCMPBU_M 0x00000300 |
#define | PWM_3_GENB_ACTCMPBU_NONE 0x00000000 |
#define | PWM_3_GENB_ACTCMPBU_INV 0x00000100 |
#define | PWM_3_GENB_ACTCMPBU_ZERO 0x00000200 |
#define | PWM_3_GENB_ACTCMPBU_ONE 0x00000300 |
#define | PWM_3_GENB_ACTCMPAD_M 0x000000C0 |
#define | PWM_3_GENB_ACTCMPAD_NONE 0x00000000 |
#define | PWM_3_GENB_ACTCMPAD_INV 0x00000040 |
#define | PWM_3_GENB_ACTCMPAD_ZERO 0x00000080 |
#define | PWM_3_GENB_ACTCMPAD_ONE 0x000000C0 |
#define | PWM_3_GENB_ACTCMPAU_M 0x00000030 |
#define | PWM_3_GENB_ACTCMPAU_NONE 0x00000000 |
#define | PWM_3_GENB_ACTCMPAU_INV 0x00000010 |
#define | PWM_3_GENB_ACTCMPAU_ZERO 0x00000020 |
#define | PWM_3_GENB_ACTCMPAU_ONE 0x00000030 |
#define | PWM_3_GENB_ACTLOAD_M 0x0000000C |
#define | PWM_3_GENB_ACTLOAD_NONE 0x00000000 |
#define | PWM_3_GENB_ACTLOAD_INV 0x00000004 |
#define | PWM_3_GENB_ACTLOAD_ZERO 0x00000008 |
#define | PWM_3_GENB_ACTLOAD_ONE 0x0000000C |
#define | PWM_3_GENB_ACTZERO_M 0x00000003 |
#define | PWM_3_GENB_ACTZERO_NONE 0x00000000 |
#define | PWM_3_GENB_ACTZERO_INV 0x00000001 |
#define | PWM_3_GENB_ACTZERO_ZERO 0x00000002 |
#define | PWM_3_GENB_ACTZERO_ONE 0x00000003 |
#define | PWM_3_DBCTL_ENABLE 0x00000001 |
#define | PWM_3_DBRISE_RISEDELAY_M 0x00000FFF |
#define | PWM_3_DBRISE_RISEDELAY_S 0 |
#define | PWM_3_DBFALL_FALLDELAY_M 0x00000FFF |
#define | PWM_3_DBFALL_FALLDELAY_S 0 |
#define | PWM_3_FLTSRC0_FAULT3 0x00000008 |
#define | PWM_3_FLTSRC0_FAULT2 0x00000004 |
#define | PWM_3_FLTSRC0_FAULT1 0x00000002 |
#define | PWM_3_FLTSRC0_FAULT0 0x00000001 |
#define | PWM_3_FLTSRC1_DCMP7 0x00000080 |
#define | PWM_3_FLTSRC1_DCMP6 0x00000040 |
#define | PWM_3_FLTSRC1_DCMP5 0x00000020 |
#define | PWM_3_FLTSRC1_DCMP4 0x00000010 |
#define | PWM_3_FLTSRC1_DCMP3 0x00000008 |
#define | PWM_3_FLTSRC1_DCMP2 0x00000004 |
#define | PWM_3_FLTSRC1_DCMP1 0x00000002 |
#define | PWM_3_FLTSRC1_DCMP0 0x00000001 |
#define | PWM_3_MINFLTPER_MFP_M 0x0000FFFF |
#define | PWM_3_MINFLTPER_MFP_S 0 |
#define | PWM_0_FLTSEN_FAULT3 0x00000008 |
#define | PWM_0_FLTSEN_FAULT2 0x00000004 |
#define | PWM_0_FLTSEN_FAULT1 0x00000002 |
#define | PWM_0_FLTSEN_FAULT0 0x00000001 |
#define | PWM_0_FLTSTAT0_FAULT3 0x00000008 |
#define | PWM_0_FLTSTAT0_FAULT2 0x00000004 |
#define | PWM_0_FLTSTAT0_FAULT1 0x00000002 |
#define | PWM_0_FLTSTAT0_FAULT0 0x00000001 |
#define | PWM_0_FLTSTAT1_DCMP7 0x00000080 |
#define | PWM_0_FLTSTAT1_DCMP6 0x00000040 |
#define | PWM_0_FLTSTAT1_DCMP5 0x00000020 |
#define | PWM_0_FLTSTAT1_DCMP4 0x00000010 |
#define | PWM_0_FLTSTAT1_DCMP3 0x00000008 |
#define | PWM_0_FLTSTAT1_DCMP2 0x00000004 |
#define | PWM_0_FLTSTAT1_DCMP1 0x00000002 |
#define | PWM_0_FLTSTAT1_DCMP0 0x00000001 |
#define | PWM_1_FLTSEN_FAULT3 0x00000008 |
#define | PWM_1_FLTSEN_FAULT2 0x00000004 |
#define | PWM_1_FLTSEN_FAULT1 0x00000002 |
#define | PWM_1_FLTSEN_FAULT0 0x00000001 |
#define | PWM_1_FLTSTAT0_FAULT3 0x00000008 |
#define | PWM_1_FLTSTAT0_FAULT2 0x00000004 |
#define | PWM_1_FLTSTAT0_FAULT1 0x00000002 |
#define | PWM_1_FLTSTAT0_FAULT0 0x00000001 |
#define | PWM_1_FLTSTAT1_DCMP7 0x00000080 |
#define | PWM_1_FLTSTAT1_DCMP6 0x00000040 |
#define | PWM_1_FLTSTAT1_DCMP5 0x00000020 |
#define | PWM_1_FLTSTAT1_DCMP4 0x00000010 |
#define | PWM_1_FLTSTAT1_DCMP3 0x00000008 |
#define | PWM_1_FLTSTAT1_DCMP2 0x00000004 |
#define | PWM_1_FLTSTAT1_DCMP1 0x00000002 |
#define | PWM_1_FLTSTAT1_DCMP0 0x00000001 |
#define | PWM_2_FLTSEN_FAULT3 0x00000008 |
#define | PWM_2_FLTSEN_FAULT2 0x00000004 |
#define | PWM_2_FLTSEN_FAULT1 0x00000002 |
#define | PWM_2_FLTSEN_FAULT0 0x00000001 |
#define | PWM_2_FLTSTAT0_FAULT3 0x00000008 |
#define | PWM_2_FLTSTAT0_FAULT2 0x00000004 |
#define | PWM_2_FLTSTAT0_FAULT1 0x00000002 |
#define | PWM_2_FLTSTAT0_FAULT0 0x00000001 |
#define | PWM_2_FLTSTAT1_DCMP7 0x00000080 |
#define | PWM_2_FLTSTAT1_DCMP6 0x00000040 |
#define | PWM_2_FLTSTAT1_DCMP5 0x00000020 |
#define | PWM_2_FLTSTAT1_DCMP4 0x00000010 |
#define | PWM_2_FLTSTAT1_DCMP3 0x00000008 |
#define | PWM_2_FLTSTAT1_DCMP2 0x00000004 |
#define | PWM_2_FLTSTAT1_DCMP1 0x00000002 |
#define | PWM_2_FLTSTAT1_DCMP0 0x00000001 |
#define | PWM_3_FLTSEN_FAULT3 0x00000008 |
#define | PWM_3_FLTSEN_FAULT2 0x00000004 |
#define | PWM_3_FLTSEN_FAULT1 0x00000002 |
#define | PWM_3_FLTSEN_FAULT0 0x00000001 |
#define | PWM_3_FLTSTAT0_FAULT3 0x00000008 |
#define | PWM_3_FLTSTAT0_FAULT2 0x00000004 |
#define | PWM_3_FLTSTAT0_FAULT1 0x00000002 |
#define | PWM_3_FLTSTAT0_FAULT0 0x00000001 |
#define | PWM_3_FLTSTAT1_DCMP7 0x00000080 |
#define | PWM_3_FLTSTAT1_DCMP6 0x00000040 |
#define | PWM_3_FLTSTAT1_DCMP5 0x00000020 |
#define | PWM_3_FLTSTAT1_DCMP4 0x00000010 |
#define | PWM_3_FLTSTAT1_DCMP3 0x00000008 |
#define | PWM_3_FLTSTAT1_DCMP2 0x00000004 |
#define | PWM_3_FLTSTAT1_DCMP1 0x00000002 |
#define | PWM_3_FLTSTAT1_DCMP0 0x00000001 |
#define | PWM_PP_GCNT_M 0x0000000F |
#define | PWM_PP_FCNT_M 0x000000F0 |
#define | PWM_PP_ESYNC 0x00000100 |
#define | PWM_PP_EFAULT 0x00000200 |
#define | PWM_PP_ONE 0x00000400 |
#define | PWM_PP_GCNT_S 0 |
#define | PWM_PP_FCNT_S 4 |
#define | PWM_CC_USEPWM 0x00000100 |
#define | PWM_CC_PWMDIV_M 0x00000007 |
#define | PWM_CC_PWMDIV_2 0x00000000 |
#define | PWM_CC_PWMDIV_4 0x00000001 |
#define | PWM_CC_PWMDIV_8 0x00000002 |
#define | PWM_CC_PWMDIV_16 0x00000003 |
#define | PWM_CC_PWMDIV_32 0x00000004 |
#define | PWM_CC_PWMDIV_64 0x00000005 |
#define | PWM_O_X_CTL 0x00000000 |
#define | PWM_O_X_INTEN 0x00000004 |
#define | PWM_O_X_RIS 0x00000008 |
#define | PWM_O_X_ISC 0x0000000C |
#define | PWM_O_X_LOAD 0x00000010 |
#define | PWM_O_X_COUNT 0x00000014 |
#define | PWM_O_X_CMPA 0x00000018 |
#define | PWM_O_X_CMPB 0x0000001C |
#define | PWM_O_X_GENA 0x00000020 |
#define | PWM_O_X_GENB 0x00000024 |
#define | PWM_O_X_DBCTL 0x00000028 |
#define | PWM_O_X_DBRISE 0x0000002C |
#define | PWM_O_X_DBFALL 0x00000030 |
#define | PWM_O_X_FLTSRC0 0x00000034 |
#define | PWM_O_X_FLTSRC1 0x00000038 |
#define | PWM_O_X_MINFLTPER 0x0000003C |
#define | PWM_GEN_0_OFFSET 0x00000040 |
#define | PWM_GEN_1_OFFSET 0x00000080 |
#define | PWM_GEN_2_OFFSET 0x000000C0 |
#define | PWM_GEN_3_OFFSET 0x00000100 |
#define | PWM_X_CTL_LATCH 0x00040000 |
#define | PWM_X_CTL_MINFLTPER 0x00020000 |
#define | PWM_X_CTL_FLTSRC 0x00010000 |
#define | PWM_X_CTL_DBFALLUPD_M 0x0000C000 |
#define | PWM_X_CTL_DBFALLUPD_I 0x00000000 |
#define | PWM_X_CTL_DBFALLUPD_LS 0x00008000 |
#define | PWM_X_CTL_DBFALLUPD_GS 0x0000C000 |
#define | PWM_X_CTL_DBRISEUPD_M 0x00003000 |
#define | PWM_X_CTL_DBRISEUPD_I 0x00000000 |
#define | PWM_X_CTL_DBRISEUPD_LS 0x00002000 |
#define | PWM_X_CTL_DBRISEUPD_GS 0x00003000 |
#define | PWM_X_CTL_DBCTLUPD_M 0x00000C00 |
#define | PWM_X_CTL_DBCTLUPD_I 0x00000000 |
#define | PWM_X_CTL_DBCTLUPD_LS 0x00000800 |
#define | PWM_X_CTL_DBCTLUPD_GS 0x00000C00 |
#define | PWM_X_CTL_GENBUPD_M 0x00000300 |
#define | PWM_X_CTL_GENBUPD_I 0x00000000 |
#define | PWM_X_CTL_GENBUPD_LS 0x00000200 |
#define | PWM_X_CTL_GENBUPD_GS 0x00000300 |
#define | PWM_X_CTL_GENAUPD_M 0x000000C0 |
#define | PWM_X_CTL_GENAUPD_I 0x00000000 |
#define | PWM_X_CTL_GENAUPD_LS 0x00000080 |
#define | PWM_X_CTL_GENAUPD_GS 0x000000C0 |
#define | PWM_X_CTL_CMPBUPD 0x00000020 |
#define | PWM_X_CTL_CMPAUPD 0x00000010 |
#define | PWM_X_CTL_LOADUPD 0x00000008 |
#define | PWM_X_CTL_DEBUG 0x00000004 |
#define | PWM_X_CTL_MODE 0x00000002 |
#define | PWM_X_CTL_ENABLE 0x00000001 |
#define | PWM_X_INTEN_TRCMPBD 0x00002000 |
#define | PWM_X_INTEN_TRCMPBU 0x00001000 |
#define | PWM_X_INTEN_TRCMPAD 0x00000800 |
#define | PWM_X_INTEN_TRCMPAU 0x00000400 |
#define | PWM_X_INTEN_TRCNTLOAD 0x00000200 |
#define | PWM_X_INTEN_TRCNTZERO 0x00000100 |
#define | PWM_X_INTEN_INTCMPBD 0x00000020 |
#define | PWM_X_INTEN_INTCMPBU 0x00000010 |
#define | PWM_X_INTEN_INTCMPAD 0x00000008 |
#define | PWM_X_INTEN_INTCMPAU 0x00000004 |
#define | PWM_X_INTEN_INTCNTLOAD 0x00000002 |
#define | PWM_X_INTEN_INTCNTZERO 0x00000001 |
#define | PWM_X_RIS_INTCMPBD 0x00000020 |
#define | PWM_X_RIS_INTCMPBU 0x00000010 |
#define | PWM_X_RIS_INTCMPAD 0x00000008 |
#define | PWM_X_RIS_INTCMPAU 0x00000004 |
#define | PWM_X_RIS_INTCNTLOAD 0x00000002 |
#define | PWM_X_RIS_INTCNTZERO 0x00000001 |
#define | PWM_X_ISC_INTCMPBD 0x00000020 |
#define | PWM_X_ISC_INTCMPBU 0x00000010 |
#define | PWM_X_ISC_INTCMPAD 0x00000008 |
#define | PWM_X_ISC_INTCMPAU 0x00000004 |
#define | PWM_X_ISC_INTCNTLOAD 0x00000002 |
#define | PWM_X_ISC_INTCNTZERO 0x00000001 |
#define | PWM_X_LOAD_M 0x0000FFFF |
#define | PWM_X_LOAD_S 0 |
#define | PWM_X_COUNT_M 0x0000FFFF |
#define | PWM_X_COUNT_S 0 |
#define | PWM_X_CMPA_M 0x0000FFFF |
#define | PWM_X_CMPA_S 0 |
#define | PWM_X_CMPB_M 0x0000FFFF |
#define | PWM_X_CMPB_S 0 |
#define | PWM_X_GENA_ACTCMPBD_M 0x00000C00 |
#define | PWM_X_GENA_ACTCMPBD_NONE 0x00000000 |
#define | PWM_X_GENA_ACTCMPBD_INV 0x00000400 |
#define | PWM_X_GENA_ACTCMPBD_ZERO 0x00000800 |
#define | PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 |
#define | PWM_X_GENA_ACTCMPBU_M 0x00000300 |
#define | PWM_X_GENA_ACTCMPBU_NONE 0x00000000 |
#define | PWM_X_GENA_ACTCMPBU_INV 0x00000100 |
#define | PWM_X_GENA_ACTCMPBU_ZERO 0x00000200 |
#define | PWM_X_GENA_ACTCMPBU_ONE 0x00000300 |
#define | PWM_X_GENA_ACTCMPAD_M 0x000000C0 |
#define | PWM_X_GENA_ACTCMPAD_NONE 0x00000000 |
#define | PWM_X_GENA_ACTCMPAD_INV 0x00000040 |
#define | PWM_X_GENA_ACTCMPAD_ZERO 0x00000080 |
#define | PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 |
#define | PWM_X_GENA_ACTCMPAU_M 0x00000030 |
#define | PWM_X_GENA_ACTCMPAU_NONE 0x00000000 |
#define | PWM_X_GENA_ACTCMPAU_INV 0x00000010 |
#define | PWM_X_GENA_ACTCMPAU_ZERO 0x00000020 |
#define | PWM_X_GENA_ACTCMPAU_ONE 0x00000030 |
#define | PWM_X_GENA_ACTLOAD_M 0x0000000C |
#define | PWM_X_GENA_ACTLOAD_NONE 0x00000000 |
#define | PWM_X_GENA_ACTLOAD_INV 0x00000004 |
#define | PWM_X_GENA_ACTLOAD_ZERO 0x00000008 |
#define | PWM_X_GENA_ACTLOAD_ONE 0x0000000C |
#define | PWM_X_GENA_ACTZERO_M 0x00000003 |
#define | PWM_X_GENA_ACTZERO_NONE 0x00000000 |
#define | PWM_X_GENA_ACTZERO_INV 0x00000001 |
#define | PWM_X_GENA_ACTZERO_ZERO 0x00000002 |
#define | PWM_X_GENA_ACTZERO_ONE 0x00000003 |
#define | PWM_X_GENB_ACTCMPBD_M 0x00000C00 |
#define | PWM_X_GENB_ACTCMPBD_NONE 0x00000000 |
#define | PWM_X_GENB_ACTCMPBD_INV 0x00000400 |
#define | PWM_X_GENB_ACTCMPBD_ZERO 0x00000800 |
#define | PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 |
#define | PWM_X_GENB_ACTCMPBU_M 0x00000300 |
#define | PWM_X_GENB_ACTCMPBU_NONE 0x00000000 |
#define | PWM_X_GENB_ACTCMPBU_INV 0x00000100 |
#define | PWM_X_GENB_ACTCMPBU_ZERO 0x00000200 |
#define | PWM_X_GENB_ACTCMPBU_ONE 0x00000300 |
#define | PWM_X_GENB_ACTCMPAD_M 0x000000C0 |
#define | PWM_X_GENB_ACTCMPAD_NONE 0x00000000 |
#define | PWM_X_GENB_ACTCMPAD_INV 0x00000040 |
#define | PWM_X_GENB_ACTCMPAD_ZERO 0x00000080 |
#define | PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 |
#define | PWM_X_GENB_ACTCMPAU_M 0x00000030 |
#define | PWM_X_GENB_ACTCMPAU_NONE 0x00000000 |
#define | PWM_X_GENB_ACTCMPAU_INV 0x00000010 |
#define | PWM_X_GENB_ACTCMPAU_ZERO 0x00000020 |
#define | PWM_X_GENB_ACTCMPAU_ONE 0x00000030 |
#define | PWM_X_GENB_ACTLOAD_M 0x0000000C |
#define | PWM_X_GENB_ACTLOAD_NONE 0x00000000 |
#define | PWM_X_GENB_ACTLOAD_INV 0x00000004 |
#define | PWM_X_GENB_ACTLOAD_ZERO 0x00000008 |
#define | PWM_X_GENB_ACTLOAD_ONE 0x0000000C |
#define | PWM_X_GENB_ACTZERO_M 0x00000003 |
#define | PWM_X_GENB_ACTZERO_NONE 0x00000000 |
#define | PWM_X_GENB_ACTZERO_INV 0x00000001 |
#define | PWM_X_GENB_ACTZERO_ZERO 0x00000002 |
#define | PWM_X_GENB_ACTZERO_ONE 0x00000003 |
#define | PWM_X_DBCTL_ENABLE 0x00000001 |
#define | PWM_X_DBRISE_DELAY_M 0x00000FFF |
#define | PWM_X_DBRISE_DELAY_S 0 |
#define | PWM_X_DBFALL_DELAY_M 0x00000FFF |
#define | PWM_X_DBFALL_DELAY_S 0 |
#define | PWM_X_FLTSRC0_FAULT3 0x00000008 |
#define | PWM_X_FLTSRC0_FAULT2 0x00000004 |
#define | PWM_X_FLTSRC0_FAULT1 0x00000002 |
#define | PWM_X_FLTSRC0_FAULT0 0x00000001 |
#define | PWM_X_FLTSRC1_DCMP7 0x00000080 |
#define | PWM_X_FLTSRC1_DCMP6 0x00000040 |
#define | PWM_X_FLTSRC1_DCMP5 0x00000020 |
#define | PWM_X_FLTSRC1_DCMP4 0x00000010 |
#define | PWM_X_FLTSRC1_DCMP3 0x00000008 |
#define | PWM_X_FLTSRC1_DCMP2 0x00000004 |
#define | PWM_X_FLTSRC1_DCMP1 0x00000002 |
#define | PWM_X_FLTSRC1_DCMP0 0x00000001 |
#define | PWM_X_MINFLTPER_M 0x0000FFFF |
#define | PWM_X_MINFLTPER_S 0 |
#define | PWM_O_X_FLTSEN 0x00000000 |
#define | PWM_O_X_FLTSTAT0 0x00000004 |
#define | PWM_O_X_FLTSTAT1 0x00000008 |
#define | PWM_EXT_0_OFFSET 0x00000800 |
#define | PWM_EXT_1_OFFSET 0x00000880 |
#define | PWM_EXT_2_OFFSET 0x00000900 |
#define | PWM_EXT_3_OFFSET 0x00000980 |
#define | PWM_X_FLTSEN_FAULT3 0x00000008 |
#define | PWM_X_FLTSEN_FAULT2 0x00000004 |
#define | PWM_X_FLTSEN_FAULT1 0x00000002 |
#define | PWM_X_FLTSEN_FAULT0 0x00000001 |
#define | PWM_X_FLTSTAT0_FAULT3 0x00000008 |
#define | PWM_X_FLTSTAT0_FAULT2 0x00000004 |
#define | PWM_X_FLTSTAT0_FAULT1 0x00000002 |
#define | PWM_X_FLTSTAT0_FAULT0 0x00000001 |
#define | PWM_X_FLTSTAT1_DCMP7 0x00000080 |
#define | PWM_X_FLTSTAT1_DCMP6 0x00000040 |
#define | PWM_X_FLTSTAT1_DCMP5 0x00000020 |
#define | PWM_X_FLTSTAT1_DCMP4 0x00000010 |
#define | PWM_X_FLTSTAT1_DCMP3 0x00000008 |
#define | PWM_X_FLTSTAT1_DCMP2 0x00000004 |
#define | PWM_X_FLTSTAT1_DCMP1 0x00000002 |
#define | PWM_X_FLTSTAT1_DCMP0 0x00000001 |
#define PWM_O_CTL 0x00000000 |
Referenced by PWMSyncUpdate().
#define PWM_O_SYNC 0x00000004 |
Referenced by PWMSyncTimeBase().
#define PWM_O_ENABLE 0x00000008 |
Referenced by PWMOutputState().
#define PWM_O_INVERT 0x0000000C |
Referenced by PWMOutputInvert().
#define PWM_O_FAULT 0x00000010 |
Referenced by PWMOutputFault().
#define PWM_O_INTEN 0x00000014 |
Referenced by PWMIntDisable(), and PWMIntEnable().
#define PWM_O_RIS 0x00000018 |
Referenced by PWMIntStatus().
#define PWM_O_ISC 0x0000001C |
Referenced by PWMFaultIntClearExt(), and PWMIntStatus().
#define PWM_O_STATUS 0x00000020 |
#define PWM_O_FAULTVAL 0x00000024 |
Referenced by PWMOutputFaultLevel().
#define PWM_O_ENUPD 0x00000028 |
Referenced by PWMOutputUpdateMode().
#define PWM_O_0_CTL 0x00000040 |
#define PWM_O_0_INTEN 0x00000044 |
#define PWM_O_0_RIS 0x00000048 |
#define PWM_O_0_ISC 0x0000004C |
#define PWM_O_0_LOAD 0x00000050 |
#define PWM_O_0_COUNT 0x00000054 |
#define PWM_O_0_CMPA 0x00000058 |
#define PWM_O_0_CMPB 0x0000005C |
#define PWM_O_0_GENA 0x00000060 |
#define PWM_O_0_GENB 0x00000064 |
#define PWM_O_0_DBCTL 0x00000068 |
#define PWM_O_0_DBRISE 0x0000006C |
#define PWM_O_0_DBFALL 0x00000070 |
#define PWM_O_0_FLTSRC0 0x00000074 |
#define PWM_O_0_FLTSRC1 0x00000078 |
#define PWM_O_0_MINFLTPER 0x0000007C |
#define PWM_O_1_CTL 0x00000080 |
#define PWM_O_1_INTEN 0x00000084 |
#define PWM_O_1_RIS 0x00000088 |
#define PWM_O_1_ISC 0x0000008C |
#define PWM_O_1_LOAD 0x00000090 |
#define PWM_O_1_COUNT 0x00000094 |
#define PWM_O_1_CMPA 0x00000098 |
#define PWM_O_1_CMPB 0x0000009C |
#define PWM_O_1_GENA 0x000000A0 |
#define PWM_O_1_GENB 0x000000A4 |
#define PWM_O_1_DBCTL 0x000000A8 |
#define PWM_O_1_DBRISE 0x000000AC |
#define PWM_O_1_DBFALL 0x000000B0 |
#define PWM_O_1_FLTSRC0 0x000000B4 |
#define PWM_O_1_FLTSRC1 0x000000B8 |
#define PWM_O_1_MINFLTPER 0x000000BC |
#define PWM_O_2_CTL 0x000000C0 |
#define PWM_O_2_INTEN 0x000000C4 |
#define PWM_O_2_RIS 0x000000C8 |
#define PWM_O_2_ISC 0x000000CC |
#define PWM_O_2_LOAD 0x000000D0 |
#define PWM_O_2_COUNT 0x000000D4 |
#define PWM_O_2_CMPA 0x000000D8 |
#define PWM_O_2_CMPB 0x000000DC |
#define PWM_O_2_GENA 0x000000E0 |
#define PWM_O_2_GENB 0x000000E4 |
#define PWM_O_2_DBCTL 0x000000E8 |
#define PWM_O_2_DBRISE 0x000000EC |
#define PWM_O_2_DBFALL 0x000000F0 |
#define PWM_O_2_FLTSRC0 0x000000F4 |
#define PWM_O_2_FLTSRC1 0x000000F8 |
#define PWM_O_2_MINFLTPER 0x000000FC |
#define PWM_O_3_CTL 0x00000100 |
#define PWM_O_3_INTEN 0x00000104 |
#define PWM_O_3_RIS 0x00000108 |
#define PWM_O_3_ISC 0x0000010C |
#define PWM_O_3_LOAD 0x00000110 |
#define PWM_O_3_COUNT 0x00000114 |
#define PWM_O_3_CMPA 0x00000118 |
#define PWM_O_3_CMPB 0x0000011C |
#define PWM_O_3_GENA 0x00000120 |
#define PWM_O_3_GENB 0x00000124 |
#define PWM_O_3_DBCTL 0x00000128 |
#define PWM_O_3_DBRISE 0x0000012C |
#define PWM_O_3_DBFALL 0x00000130 |
#define PWM_O_3_FLTSRC0 0x00000134 |
#define PWM_O_3_FLTSRC1 0x00000138 |
#define PWM_O_3_MINFLTPER 0x0000013C |
#define PWM_O_0_FLTSEN 0x00000800 |
#define PWM_O_0_FLTSTAT0 0x00000804 |
#define PWM_O_0_FLTSTAT1 0x00000808 |
#define PWM_O_1_FLTSEN 0x00000880 |
#define PWM_O_1_FLTSTAT0 0x00000884 |
#define PWM_O_1_FLTSTAT1 0x00000888 |
#define PWM_O_2_FLTSEN 0x00000900 |
#define PWM_O_2_FLTSTAT0 0x00000904 |
#define PWM_O_2_FLTSTAT1 0x00000908 |
#define PWM_O_3_FLTSEN 0x00000980 |
#define PWM_O_3_FLTSTAT0 0x00000984 |
#define PWM_O_3_FLTSTAT1 0x00000988 |
#define PWM_O_PP 0x00000FC0 |
#define PWM_O_CC 0x00000FC8 |
Referenced by PWMClockGet(), and PWMClockSet().
#define PWM_CTL_GLOBALSYNC3 0x00000008 |
#define PWM_CTL_GLOBALSYNC2 0x00000004 |
#define PWM_CTL_GLOBALSYNC1 0x00000002 |
#define PWM_CTL_GLOBALSYNC0 0x00000001 |
#define PWM_SYNC_SYNC3 0x00000008 |
#define PWM_SYNC_SYNC2 0x00000004 |
#define PWM_SYNC_SYNC1 0x00000002 |
#define PWM_SYNC_SYNC0 0x00000001 |
#define PWM_ENABLE_PWM7EN 0x00000080 |
#define PWM_ENABLE_PWM6EN 0x00000040 |
#define PWM_ENABLE_PWM5EN 0x00000020 |
#define PWM_ENABLE_PWM4EN 0x00000010 |
#define PWM_ENABLE_PWM3EN 0x00000008 |
#define PWM_ENABLE_PWM2EN 0x00000004 |
#define PWM_ENABLE_PWM1EN 0x00000002 |
#define PWM_ENABLE_PWM0EN 0x00000001 |
#define PWM_INVERT_PWM7INV 0x00000080 |
#define PWM_INVERT_PWM6INV 0x00000040 |
#define PWM_INVERT_PWM5INV 0x00000020 |
#define PWM_INVERT_PWM4INV 0x00000010 |
#define PWM_INVERT_PWM3INV 0x00000008 |
#define PWM_INVERT_PWM2INV 0x00000004 |
#define PWM_INVERT_PWM1INV 0x00000002 |
#define PWM_INVERT_PWM0INV 0x00000001 |
#define PWM_FAULT_FAULT7 0x00000080 |
#define PWM_FAULT_FAULT6 0x00000040 |
#define PWM_FAULT_FAULT5 0x00000020 |
#define PWM_FAULT_FAULT4 0x00000010 |
#define PWM_FAULT_FAULT3 0x00000008 |
Referenced by PWMGenFaultClear(), and PWMGenFaultTriggerSet().
#define PWM_FAULT_FAULT2 0x00000004 |
Referenced by PWMGenFaultClear(), and PWMGenFaultTriggerSet().
#define PWM_FAULT_FAULT1 0x00000002 |
Referenced by PWMGenFaultClear(), and PWMGenFaultTriggerSet().
#define PWM_FAULT_FAULT0 0x00000001 |
Referenced by PWMGenFaultClear(), and PWMGenFaultTriggerSet().
#define PWM_INTEN_INTFAULT3 0x00080000 |
#define PWM_INTEN_INTFAULT2 0x00040000 |
#define PWM_INTEN_INTFAULT1 0x00020000 |
#define PWM_INTEN_INTFAULT0 0x00010000 |
#define PWM_INTEN_INTPWM3 0x00000008 |
#define PWM_INTEN_INTPWM2 0x00000004 |
#define PWM_INTEN_INTPWM1 0x00000002 |
#define PWM_INTEN_INTPWM0 0x00000001 |
#define PWM_RIS_INTFAULT3 0x00080000 |
#define PWM_RIS_INTFAULT2 0x00040000 |
#define PWM_RIS_INTFAULT1 0x00020000 |
#define PWM_RIS_INTFAULT0 0x00010000 |
#define PWM_RIS_INTPWM3 0x00000008 |
#define PWM_RIS_INTPWM2 0x00000004 |
#define PWM_RIS_INTPWM1 0x00000002 |
#define PWM_RIS_INTPWM0 0x00000001 |
#define PWM_ISC_INTFAULT3 0x00080000 |
#define PWM_ISC_INTFAULT2 0x00040000 |
#define PWM_ISC_INTFAULT1 0x00020000 |
#define PWM_ISC_INTFAULT0 0x00010000 |
#define PWM_ISC_INTPWM3 0x00000008 |
#define PWM_ISC_INTPWM2 0x00000004 |
#define PWM_ISC_INTPWM1 0x00000002 |
#define PWM_ISC_INTPWM0 0x00000001 |
#define PWM_STATUS_FAULT3 0x00000008 |
#define PWM_STATUS_FAULT2 0x00000004 |
#define PWM_STATUS_FAULT1 0x00000002 |
#define PWM_STATUS_FAULT0 0x00000001 |
#define PWM_FAULTVAL_PWM7 0x00000080 |
#define PWM_FAULTVAL_PWM6 0x00000040 |
#define PWM_FAULTVAL_PWM5 0x00000020 |
#define PWM_FAULTVAL_PWM4 0x00000010 |
#define PWM_FAULTVAL_PWM3 0x00000008 |
#define PWM_FAULTVAL_PWM2 0x00000004 |
#define PWM_FAULTVAL_PWM1 0x00000002 |
#define PWM_FAULTVAL_PWM0 0x00000001 |
#define PWM_ENUPD_ENUPD7_M 0x0000C000 |
#define PWM_ENUPD_ENUPD7_IMM 0x00000000 |
#define PWM_ENUPD_ENUPD7_LSYNC 0x00008000 |
#define PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 |
#define PWM_ENUPD_ENUPD6_M 0x00003000 |
#define PWM_ENUPD_ENUPD6_IMM 0x00000000 |
#define PWM_ENUPD_ENUPD6_LSYNC 0x00002000 |
#define PWM_ENUPD_ENUPD6_GSYNC 0x00003000 |
#define PWM_ENUPD_ENUPD5_M 0x00000C00 |
#define PWM_ENUPD_ENUPD5_IMM 0x00000000 |
#define PWM_ENUPD_ENUPD5_LSYNC 0x00000800 |
#define PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 |
#define PWM_ENUPD_ENUPD4_M 0x00000300 |
#define PWM_ENUPD_ENUPD4_IMM 0x00000000 |
#define PWM_ENUPD_ENUPD4_LSYNC 0x00000200 |
#define PWM_ENUPD_ENUPD4_GSYNC 0x00000300 |
#define PWM_ENUPD_ENUPD3_M 0x000000C0 |
#define PWM_ENUPD_ENUPD3_IMM 0x00000000 |
#define PWM_ENUPD_ENUPD3_LSYNC 0x00000080 |
#define PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 |
#define PWM_ENUPD_ENUPD2_M 0x00000030 |
#define PWM_ENUPD_ENUPD2_IMM 0x00000000 |
#define PWM_ENUPD_ENUPD2_LSYNC 0x00000020 |
#define PWM_ENUPD_ENUPD2_GSYNC 0x00000030 |
#define PWM_ENUPD_ENUPD1_M 0x0000000C |
#define PWM_ENUPD_ENUPD1_IMM 0x00000000 |
#define PWM_ENUPD_ENUPD1_LSYNC 0x00000008 |
#define PWM_ENUPD_ENUPD1_GSYNC 0x0000000C |
#define PWM_ENUPD_ENUPD0_M 0x00000003 |
#define PWM_ENUPD_ENUPD0_IMM 0x00000000 |
#define PWM_ENUPD_ENUPD0_LSYNC 0x00000002 |
#define PWM_ENUPD_ENUPD0_GSYNC 0x00000003 |
#define PWM_0_CTL_LATCH 0x00040000 |
#define PWM_0_CTL_MINFLTPER 0x00020000 |
#define PWM_0_CTL_FLTSRC 0x00010000 |
#define PWM_0_CTL_DBFALLUPD_M 0x0000C000 |
#define PWM_0_CTL_DBFALLUPD_I 0x00000000 |
#define PWM_0_CTL_DBFALLUPD_LS 0x00008000 |
#define PWM_0_CTL_DBFALLUPD_GS 0x0000C000 |
#define PWM_0_CTL_DBRISEUPD_M 0x00003000 |
#define PWM_0_CTL_DBRISEUPD_I 0x00000000 |
#define PWM_0_CTL_DBRISEUPD_LS 0x00002000 |
#define PWM_0_CTL_DBRISEUPD_GS 0x00003000 |
#define PWM_0_CTL_DBCTLUPD_M 0x00000C00 |
#define PWM_0_CTL_DBCTLUPD_I 0x00000000 |
#define PWM_0_CTL_DBCTLUPD_LS 0x00000800 |
#define PWM_0_CTL_DBCTLUPD_GS 0x00000C00 |
#define PWM_0_CTL_GENBUPD_M 0x00000300 |
#define PWM_0_CTL_GENBUPD_I 0x00000000 |
#define PWM_0_CTL_GENBUPD_LS 0x00000200 |
#define PWM_0_CTL_GENBUPD_GS 0x00000300 |
#define PWM_0_CTL_GENAUPD_M 0x000000C0 |
#define PWM_0_CTL_GENAUPD_I 0x00000000 |
#define PWM_0_CTL_GENAUPD_LS 0x00000080 |
#define PWM_0_CTL_GENAUPD_GS 0x000000C0 |
#define PWM_0_CTL_CMPBUPD 0x00000020 |
#define PWM_0_CTL_CMPAUPD 0x00000010 |
#define PWM_0_CTL_LOADUPD 0x00000008 |
#define PWM_0_CTL_DEBUG 0x00000004 |
#define PWM_0_CTL_MODE 0x00000002 |
#define PWM_0_CTL_ENABLE 0x00000001 |
#define PWM_0_INTEN_TRCMPBD 0x00002000 |
#define PWM_0_INTEN_TRCMPBU 0x00001000 |
#define PWM_0_INTEN_TRCMPAD 0x00000800 |
#define PWM_0_INTEN_TRCMPAU 0x00000400 |
#define PWM_0_INTEN_TRCNTLOAD 0x00000200 |
#define PWM_0_INTEN_TRCNTZERO 0x00000100 |
#define PWM_0_INTEN_INTCMPBD 0x00000020 |
#define PWM_0_INTEN_INTCMPBU 0x00000010 |
#define PWM_0_INTEN_INTCMPAD 0x00000008 |
#define PWM_0_INTEN_INTCMPAU 0x00000004 |
#define PWM_0_INTEN_INTCNTLOAD 0x00000002 |
#define PWM_0_INTEN_INTCNTZERO 0x00000001 |
#define PWM_0_RIS_INTCMPBD 0x00000020 |
#define PWM_0_RIS_INTCMPBU 0x00000010 |
#define PWM_0_RIS_INTCMPAD 0x00000008 |
#define PWM_0_RIS_INTCMPAU 0x00000004 |
#define PWM_0_RIS_INTCNTLOAD 0x00000002 |
#define PWM_0_RIS_INTCNTZERO 0x00000001 |
#define PWM_0_ISC_INTCMPBD 0x00000020 |
#define PWM_0_ISC_INTCMPBU 0x00000010 |
#define PWM_0_ISC_INTCMPAD 0x00000008 |
#define PWM_0_ISC_INTCMPAU 0x00000004 |
#define PWM_0_ISC_INTCNTLOAD 0x00000002 |
#define PWM_0_ISC_INTCNTZERO 0x00000001 |
#define PWM_0_LOAD_M 0x0000FFFF |
#define PWM_0_LOAD_S 0 |
#define PWM_0_COUNT_M 0x0000FFFF |
#define PWM_0_COUNT_S 0 |
#define PWM_0_CMPA_M 0x0000FFFF |
#define PWM_0_CMPA_S 0 |
#define PWM_0_CMPB_M 0x0000FFFF |
#define PWM_0_CMPB_S 0 |
#define PWM_0_GENA_ACTCMPBD_M 0x00000C00 |
#define PWM_0_GENA_ACTCMPBD_NONE 0x00000000 |
#define PWM_0_GENA_ACTCMPBD_INV 0x00000400 |
#define PWM_0_GENA_ACTCMPBD_ZERO 0x00000800 |
#define PWM_0_GENA_ACTCMPBD_ONE 0x00000C00 |
#define PWM_0_GENA_ACTCMPBU_M 0x00000300 |
#define PWM_0_GENA_ACTCMPBU_NONE 0x00000000 |
#define PWM_0_GENA_ACTCMPBU_INV 0x00000100 |
#define PWM_0_GENA_ACTCMPBU_ZERO 0x00000200 |
#define PWM_0_GENA_ACTCMPBU_ONE 0x00000300 |
#define PWM_0_GENA_ACTCMPAD_M 0x000000C0 |
#define PWM_0_GENA_ACTCMPAD_NONE 0x00000000 |
#define PWM_0_GENA_ACTCMPAD_INV 0x00000040 |
#define PWM_0_GENA_ACTCMPAD_ZERO 0x00000080 |
#define PWM_0_GENA_ACTCMPAD_ONE 0x000000C0 |
#define PWM_0_GENA_ACTCMPAU_M 0x00000030 |
#define PWM_0_GENA_ACTCMPAU_NONE 0x00000000 |
#define PWM_0_GENA_ACTCMPAU_INV 0x00000010 |
#define PWM_0_GENA_ACTCMPAU_ZERO 0x00000020 |
#define PWM_0_GENA_ACTCMPAU_ONE 0x00000030 |
#define PWM_0_GENA_ACTLOAD_M 0x0000000C |
#define PWM_0_GENA_ACTLOAD_NONE 0x00000000 |
#define PWM_0_GENA_ACTLOAD_INV 0x00000004 |
#define PWM_0_GENA_ACTLOAD_ZERO 0x00000008 |
#define PWM_0_GENA_ACTLOAD_ONE 0x0000000C |
#define PWM_0_GENA_ACTZERO_M 0x00000003 |
#define PWM_0_GENA_ACTZERO_NONE 0x00000000 |
#define PWM_0_GENA_ACTZERO_INV 0x00000001 |
#define PWM_0_GENA_ACTZERO_ZERO 0x00000002 |
#define PWM_0_GENA_ACTZERO_ONE 0x00000003 |
#define PWM_0_GENB_ACTCMPBD_M 0x00000C00 |
#define PWM_0_GENB_ACTCMPBD_NONE 0x00000000 |
#define PWM_0_GENB_ACTCMPBD_INV 0x00000400 |
#define PWM_0_GENB_ACTCMPBD_ZERO 0x00000800 |
#define PWM_0_GENB_ACTCMPBD_ONE 0x00000C00 |
#define PWM_0_GENB_ACTCMPBU_M 0x00000300 |
#define PWM_0_GENB_ACTCMPBU_NONE 0x00000000 |
#define PWM_0_GENB_ACTCMPBU_INV 0x00000100 |
#define PWM_0_GENB_ACTCMPBU_ZERO 0x00000200 |
#define PWM_0_GENB_ACTCMPBU_ONE 0x00000300 |
#define PWM_0_GENB_ACTCMPAD_M 0x000000C0 |
#define PWM_0_GENB_ACTCMPAD_NONE 0x00000000 |
#define PWM_0_GENB_ACTCMPAD_INV 0x00000040 |
#define PWM_0_GENB_ACTCMPAD_ZERO 0x00000080 |
#define PWM_0_GENB_ACTCMPAD_ONE 0x000000C0 |
#define PWM_0_GENB_ACTCMPAU_M 0x00000030 |
#define PWM_0_GENB_ACTCMPAU_NONE 0x00000000 |
#define PWM_0_GENB_ACTCMPAU_INV 0x00000010 |
#define PWM_0_GENB_ACTCMPAU_ZERO 0x00000020 |
#define PWM_0_GENB_ACTCMPAU_ONE 0x00000030 |
#define PWM_0_GENB_ACTLOAD_M 0x0000000C |
#define PWM_0_GENB_ACTLOAD_NONE 0x00000000 |
#define PWM_0_GENB_ACTLOAD_INV 0x00000004 |
#define PWM_0_GENB_ACTLOAD_ZERO 0x00000008 |
#define PWM_0_GENB_ACTLOAD_ONE 0x0000000C |
#define PWM_0_GENB_ACTZERO_M 0x00000003 |
#define PWM_0_GENB_ACTZERO_NONE 0x00000000 |
#define PWM_0_GENB_ACTZERO_INV 0x00000001 |
#define PWM_0_GENB_ACTZERO_ZERO 0x00000002 |
#define PWM_0_GENB_ACTZERO_ONE 0x00000003 |
#define PWM_0_DBCTL_ENABLE 0x00000001 |
#define PWM_0_DBRISE_DELAY_M 0x00000FFF |
#define PWM_0_DBRISE_DELAY_S 0 |
#define PWM_0_DBFALL_DELAY_M 0x00000FFF |
#define PWM_0_DBFALL_DELAY_S 0 |
#define PWM_0_FLTSRC0_FAULT3 0x00000008 |
#define PWM_0_FLTSRC0_FAULT2 0x00000004 |
#define PWM_0_FLTSRC0_FAULT1 0x00000002 |
#define PWM_0_FLTSRC0_FAULT0 0x00000001 |
#define PWM_0_FLTSRC1_DCMP7 0x00000080 |
#define PWM_0_FLTSRC1_DCMP6 0x00000040 |
#define PWM_0_FLTSRC1_DCMP5 0x00000020 |
#define PWM_0_FLTSRC1_DCMP4 0x00000010 |
#define PWM_0_FLTSRC1_DCMP3 0x00000008 |
#define PWM_0_FLTSRC1_DCMP2 0x00000004 |
#define PWM_0_FLTSRC1_DCMP1 0x00000002 |
#define PWM_0_FLTSRC1_DCMP0 0x00000001 |
#define PWM_0_MINFLTPER_M 0x0000FFFF |
#define PWM_0_MINFLTPER_S 0 |
#define PWM_1_CTL_LATCH 0x00040000 |
#define PWM_1_CTL_MINFLTPER 0x00020000 |
#define PWM_1_CTL_FLTSRC 0x00010000 |
#define PWM_1_CTL_DBFALLUPD_M 0x0000C000 |
#define PWM_1_CTL_DBFALLUPD_I 0x00000000 |
#define PWM_1_CTL_DBFALLUPD_LS 0x00008000 |
#define PWM_1_CTL_DBFALLUPD_GS 0x0000C000 |
#define PWM_1_CTL_DBRISEUPD_M 0x00003000 |
#define PWM_1_CTL_DBRISEUPD_I 0x00000000 |
#define PWM_1_CTL_DBRISEUPD_LS 0x00002000 |
#define PWM_1_CTL_DBRISEUPD_GS 0x00003000 |
#define PWM_1_CTL_DBCTLUPD_M 0x00000C00 |
#define PWM_1_CTL_DBCTLUPD_I 0x00000000 |
#define PWM_1_CTL_DBCTLUPD_LS 0x00000800 |
#define PWM_1_CTL_DBCTLUPD_GS 0x00000C00 |
#define PWM_1_CTL_GENBUPD_M 0x00000300 |
#define PWM_1_CTL_GENBUPD_I 0x00000000 |
#define PWM_1_CTL_GENBUPD_LS 0x00000200 |
#define PWM_1_CTL_GENBUPD_GS 0x00000300 |
#define PWM_1_CTL_GENAUPD_M 0x000000C0 |
#define PWM_1_CTL_GENAUPD_I 0x00000000 |
#define PWM_1_CTL_GENAUPD_LS 0x00000080 |
#define PWM_1_CTL_GENAUPD_GS 0x000000C0 |
#define PWM_1_CTL_CMPBUPD 0x00000020 |
#define PWM_1_CTL_CMPAUPD 0x00000010 |
#define PWM_1_CTL_LOADUPD 0x00000008 |
#define PWM_1_CTL_DEBUG 0x00000004 |
#define PWM_1_CTL_MODE 0x00000002 |
#define PWM_1_CTL_ENABLE 0x00000001 |
#define PWM_1_INTEN_TRCMPBD 0x00002000 |
#define PWM_1_INTEN_TRCMPBU 0x00001000 |
#define PWM_1_INTEN_TRCMPAD 0x00000800 |
#define PWM_1_INTEN_TRCMPAU 0x00000400 |
#define PWM_1_INTEN_TRCNTLOAD 0x00000200 |
#define PWM_1_INTEN_TRCNTZERO 0x00000100 |
#define PWM_1_INTEN_INTCMPBD 0x00000020 |
#define PWM_1_INTEN_INTCMPBU 0x00000010 |
#define PWM_1_INTEN_INTCMPAD 0x00000008 |
#define PWM_1_INTEN_INTCMPAU 0x00000004 |
#define PWM_1_INTEN_INTCNTLOAD 0x00000002 |
#define PWM_1_INTEN_INTCNTZERO 0x00000001 |
#define PWM_1_RIS_INTCMPBD 0x00000020 |
#define PWM_1_RIS_INTCMPBU 0x00000010 |
#define PWM_1_RIS_INTCMPAD 0x00000008 |
#define PWM_1_RIS_INTCMPAU 0x00000004 |
#define PWM_1_RIS_INTCNTLOAD 0x00000002 |
#define PWM_1_RIS_INTCNTZERO 0x00000001 |
#define PWM_1_ISC_INTCMPBD 0x00000020 |
#define PWM_1_ISC_INTCMPBU 0x00000010 |
#define PWM_1_ISC_INTCMPAD 0x00000008 |
#define PWM_1_ISC_INTCMPAU 0x00000004 |
#define PWM_1_ISC_INTCNTLOAD 0x00000002 |
#define PWM_1_ISC_INTCNTZERO 0x00000001 |
#define PWM_1_LOAD_LOAD_M 0x0000FFFF |
#define PWM_1_LOAD_LOAD_S 0 |
#define PWM_1_COUNT_COUNT_M 0x0000FFFF |
#define PWM_1_COUNT_COUNT_S 0 |
#define PWM_1_CMPA_COMPA_M 0x0000FFFF |
#define PWM_1_CMPA_COMPA_S 0 |
#define PWM_1_CMPB_COMPB_M 0x0000FFFF |
#define PWM_1_CMPB_COMPB_S 0 |
#define PWM_1_GENA_ACTCMPBD_M 0x00000C00 |
#define PWM_1_GENA_ACTCMPBD_NONE 0x00000000 |
#define PWM_1_GENA_ACTCMPBD_INV 0x00000400 |
#define PWM_1_GENA_ACTCMPBD_ZERO 0x00000800 |
#define PWM_1_GENA_ACTCMPBD_ONE 0x00000C00 |
#define PWM_1_GENA_ACTCMPBU_M 0x00000300 |
#define PWM_1_GENA_ACTCMPBU_NONE 0x00000000 |
#define PWM_1_GENA_ACTCMPBU_INV 0x00000100 |
#define PWM_1_GENA_ACTCMPBU_ZERO 0x00000200 |
#define PWM_1_GENA_ACTCMPBU_ONE 0x00000300 |
#define PWM_1_GENA_ACTCMPAD_M 0x000000C0 |
#define PWM_1_GENA_ACTCMPAD_NONE 0x00000000 |
#define PWM_1_GENA_ACTCMPAD_INV 0x00000040 |
#define PWM_1_GENA_ACTCMPAD_ZERO 0x00000080 |
#define PWM_1_GENA_ACTCMPAD_ONE 0x000000C0 |
#define PWM_1_GENA_ACTCMPAU_M 0x00000030 |
#define PWM_1_GENA_ACTCMPAU_NONE 0x00000000 |
#define PWM_1_GENA_ACTCMPAU_INV 0x00000010 |
#define PWM_1_GENA_ACTCMPAU_ZERO 0x00000020 |
#define PWM_1_GENA_ACTCMPAU_ONE 0x00000030 |
#define PWM_1_GENA_ACTLOAD_M 0x0000000C |
#define PWM_1_GENA_ACTLOAD_NONE 0x00000000 |
#define PWM_1_GENA_ACTLOAD_INV 0x00000004 |
#define PWM_1_GENA_ACTLOAD_ZERO 0x00000008 |
#define PWM_1_GENA_ACTLOAD_ONE 0x0000000C |
#define PWM_1_GENA_ACTZERO_M 0x00000003 |
#define PWM_1_GENA_ACTZERO_NONE 0x00000000 |
#define PWM_1_GENA_ACTZERO_INV 0x00000001 |
#define PWM_1_GENA_ACTZERO_ZERO 0x00000002 |
#define PWM_1_GENA_ACTZERO_ONE 0x00000003 |
#define PWM_1_GENB_ACTCMPBD_M 0x00000C00 |
#define PWM_1_GENB_ACTCMPBD_NONE 0x00000000 |
#define PWM_1_GENB_ACTCMPBD_INV 0x00000400 |
#define PWM_1_GENB_ACTCMPBD_ZERO 0x00000800 |
#define PWM_1_GENB_ACTCMPBD_ONE 0x00000C00 |
#define PWM_1_GENB_ACTCMPBU_M 0x00000300 |
#define PWM_1_GENB_ACTCMPBU_NONE 0x00000000 |
#define PWM_1_GENB_ACTCMPBU_INV 0x00000100 |
#define PWM_1_GENB_ACTCMPBU_ZERO 0x00000200 |
#define PWM_1_GENB_ACTCMPBU_ONE 0x00000300 |
#define PWM_1_GENB_ACTCMPAD_M 0x000000C0 |
#define PWM_1_GENB_ACTCMPAD_NONE 0x00000000 |
#define PWM_1_GENB_ACTCMPAD_INV 0x00000040 |
#define PWM_1_GENB_ACTCMPAD_ZERO 0x00000080 |
#define PWM_1_GENB_ACTCMPAD_ONE 0x000000C0 |
#define PWM_1_GENB_ACTCMPAU_M 0x00000030 |
#define PWM_1_GENB_ACTCMPAU_NONE 0x00000000 |
#define PWM_1_GENB_ACTCMPAU_INV 0x00000010 |
#define PWM_1_GENB_ACTCMPAU_ZERO 0x00000020 |
#define PWM_1_GENB_ACTCMPAU_ONE 0x00000030 |
#define PWM_1_GENB_ACTLOAD_M 0x0000000C |
#define PWM_1_GENB_ACTLOAD_NONE 0x00000000 |
#define PWM_1_GENB_ACTLOAD_INV 0x00000004 |
#define PWM_1_GENB_ACTLOAD_ZERO 0x00000008 |
#define PWM_1_GENB_ACTLOAD_ONE 0x0000000C |
#define PWM_1_GENB_ACTZERO_M 0x00000003 |
#define PWM_1_GENB_ACTZERO_NONE 0x00000000 |
#define PWM_1_GENB_ACTZERO_INV 0x00000001 |
#define PWM_1_GENB_ACTZERO_ZERO 0x00000002 |
#define PWM_1_GENB_ACTZERO_ONE 0x00000003 |
#define PWM_1_DBCTL_ENABLE 0x00000001 |
#define PWM_1_DBRISE_RISEDELAY_M 0x00000FFF |
#define PWM_1_DBRISE_RISEDELAY_S 0 |
#define PWM_1_DBFALL_FALLDELAY_M 0x00000FFF |
#define PWM_1_DBFALL_FALLDELAY_S 0 |
#define PWM_1_FLTSRC0_FAULT3 0x00000008 |
#define PWM_1_FLTSRC0_FAULT2 0x00000004 |
#define PWM_1_FLTSRC0_FAULT1 0x00000002 |
#define PWM_1_FLTSRC0_FAULT0 0x00000001 |
#define PWM_1_FLTSRC1_DCMP7 0x00000080 |
#define PWM_1_FLTSRC1_DCMP6 0x00000040 |
#define PWM_1_FLTSRC1_DCMP5 0x00000020 |
#define PWM_1_FLTSRC1_DCMP4 0x00000010 |
#define PWM_1_FLTSRC1_DCMP3 0x00000008 |
#define PWM_1_FLTSRC1_DCMP2 0x00000004 |
#define PWM_1_FLTSRC1_DCMP1 0x00000002 |
#define PWM_1_FLTSRC1_DCMP0 0x00000001 |
#define PWM_1_MINFLTPER_MFP_M 0x0000FFFF |
#define PWM_1_MINFLTPER_MFP_S 0 |
#define PWM_2_CTL_LATCH 0x00040000 |
#define PWM_2_CTL_MINFLTPER 0x00020000 |
#define PWM_2_CTL_FLTSRC 0x00010000 |
#define PWM_2_CTL_DBFALLUPD_M 0x0000C000 |
#define PWM_2_CTL_DBFALLUPD_I 0x00000000 |
#define PWM_2_CTL_DBFALLUPD_LS 0x00008000 |
#define PWM_2_CTL_DBFALLUPD_GS 0x0000C000 |
#define PWM_2_CTL_DBRISEUPD_M 0x00003000 |
#define PWM_2_CTL_DBRISEUPD_I 0x00000000 |
#define PWM_2_CTL_DBRISEUPD_LS 0x00002000 |
#define PWM_2_CTL_DBRISEUPD_GS 0x00003000 |
#define PWM_2_CTL_DBCTLUPD_M 0x00000C00 |
#define PWM_2_CTL_DBCTLUPD_I 0x00000000 |
#define PWM_2_CTL_DBCTLUPD_LS 0x00000800 |
#define PWM_2_CTL_DBCTLUPD_GS 0x00000C00 |
#define PWM_2_CTL_GENBUPD_M 0x00000300 |
#define PWM_2_CTL_GENBUPD_I 0x00000000 |
#define PWM_2_CTL_GENBUPD_LS 0x00000200 |
#define PWM_2_CTL_GENBUPD_GS 0x00000300 |
#define PWM_2_CTL_GENAUPD_M 0x000000C0 |
#define PWM_2_CTL_GENAUPD_I 0x00000000 |
#define PWM_2_CTL_GENAUPD_LS 0x00000080 |
#define PWM_2_CTL_GENAUPD_GS 0x000000C0 |
#define PWM_2_CTL_CMPBUPD 0x00000020 |
#define PWM_2_CTL_CMPAUPD 0x00000010 |
#define PWM_2_CTL_LOADUPD 0x00000008 |
#define PWM_2_CTL_DEBUG 0x00000004 |
#define PWM_2_CTL_MODE 0x00000002 |
#define PWM_2_CTL_ENABLE 0x00000001 |
#define PWM_2_INTEN_TRCMPBD 0x00002000 |
#define PWM_2_INTEN_TRCMPBU 0x00001000 |
#define PWM_2_INTEN_TRCMPAD 0x00000800 |
#define PWM_2_INTEN_TRCMPAU 0x00000400 |
#define PWM_2_INTEN_TRCNTLOAD 0x00000200 |
#define PWM_2_INTEN_TRCNTZERO 0x00000100 |
#define PWM_2_INTEN_INTCMPBD 0x00000020 |
#define PWM_2_INTEN_INTCMPBU 0x00000010 |
#define PWM_2_INTEN_INTCMPAD 0x00000008 |
#define PWM_2_INTEN_INTCMPAU 0x00000004 |
#define PWM_2_INTEN_INTCNTLOAD 0x00000002 |
#define PWM_2_INTEN_INTCNTZERO 0x00000001 |
#define PWM_2_RIS_INTCMPBD 0x00000020 |
#define PWM_2_RIS_INTCMPBU 0x00000010 |
#define PWM_2_RIS_INTCMPAD 0x00000008 |
#define PWM_2_RIS_INTCMPAU 0x00000004 |
#define PWM_2_RIS_INTCNTLOAD 0x00000002 |
#define PWM_2_RIS_INTCNTZERO 0x00000001 |
#define PWM_2_ISC_INTCMPBD 0x00000020 |
#define PWM_2_ISC_INTCMPBU 0x00000010 |
#define PWM_2_ISC_INTCMPAD 0x00000008 |
#define PWM_2_ISC_INTCMPAU 0x00000004 |
#define PWM_2_ISC_INTCNTLOAD 0x00000002 |
#define PWM_2_ISC_INTCNTZERO 0x00000001 |
#define PWM_2_LOAD_LOAD_M 0x0000FFFF |
#define PWM_2_LOAD_LOAD_S 0 |
#define PWM_2_COUNT_COUNT_M 0x0000FFFF |
#define PWM_2_COUNT_COUNT_S 0 |
#define PWM_2_CMPA_COMPA_M 0x0000FFFF |
#define PWM_2_CMPA_COMPA_S 0 |
#define PWM_2_CMPB_COMPB_M 0x0000FFFF |
#define PWM_2_CMPB_COMPB_S 0 |
#define PWM_2_GENA_ACTCMPBD_M 0x00000C00 |
#define PWM_2_GENA_ACTCMPBD_NONE 0x00000000 |
#define PWM_2_GENA_ACTCMPBD_INV 0x00000400 |
#define PWM_2_GENA_ACTCMPBD_ZERO 0x00000800 |
#define PWM_2_GENA_ACTCMPBD_ONE 0x00000C00 |
#define PWM_2_GENA_ACTCMPBU_M 0x00000300 |
#define PWM_2_GENA_ACTCMPBU_NONE 0x00000000 |
#define PWM_2_GENA_ACTCMPBU_INV 0x00000100 |
#define PWM_2_GENA_ACTCMPBU_ZERO 0x00000200 |
#define PWM_2_GENA_ACTCMPBU_ONE 0x00000300 |
#define PWM_2_GENA_ACTCMPAD_M 0x000000C0 |
#define PWM_2_GENA_ACTCMPAD_NONE 0x00000000 |
#define PWM_2_GENA_ACTCMPAD_INV 0x00000040 |
#define PWM_2_GENA_ACTCMPAD_ZERO 0x00000080 |
#define PWM_2_GENA_ACTCMPAD_ONE 0x000000C0 |
#define PWM_2_GENA_ACTCMPAU_M 0x00000030 |
#define PWM_2_GENA_ACTCMPAU_NONE 0x00000000 |
#define PWM_2_GENA_ACTCMPAU_INV 0x00000010 |
#define PWM_2_GENA_ACTCMPAU_ZERO 0x00000020 |
#define PWM_2_GENA_ACTCMPAU_ONE 0x00000030 |
#define PWM_2_GENA_ACTLOAD_M 0x0000000C |
#define PWM_2_GENA_ACTLOAD_NONE 0x00000000 |
#define PWM_2_GENA_ACTLOAD_INV 0x00000004 |
#define PWM_2_GENA_ACTLOAD_ZERO 0x00000008 |
#define PWM_2_GENA_ACTLOAD_ONE 0x0000000C |
#define PWM_2_GENA_ACTZERO_M 0x00000003 |
#define PWM_2_GENA_ACTZERO_NONE 0x00000000 |
#define PWM_2_GENA_ACTZERO_INV 0x00000001 |
#define PWM_2_GENA_ACTZERO_ZERO 0x00000002 |
#define PWM_2_GENA_ACTZERO_ONE 0x00000003 |
#define PWM_2_GENB_ACTCMPBD_M 0x00000C00 |
#define PWM_2_GENB_ACTCMPBD_NONE 0x00000000 |
#define PWM_2_GENB_ACTCMPBD_INV 0x00000400 |
#define PWM_2_GENB_ACTCMPBD_ZERO 0x00000800 |
#define PWM_2_GENB_ACTCMPBD_ONE 0x00000C00 |
#define PWM_2_GENB_ACTCMPBU_M 0x00000300 |
#define PWM_2_GENB_ACTCMPBU_NONE 0x00000000 |
#define PWM_2_GENB_ACTCMPBU_INV 0x00000100 |
#define PWM_2_GENB_ACTCMPBU_ZERO 0x00000200 |
#define PWM_2_GENB_ACTCMPBU_ONE 0x00000300 |
#define PWM_2_GENB_ACTCMPAD_M 0x000000C0 |
#define PWM_2_GENB_ACTCMPAD_NONE 0x00000000 |
#define PWM_2_GENB_ACTCMPAD_INV 0x00000040 |
#define PWM_2_GENB_ACTCMPAD_ZERO 0x00000080 |
#define PWM_2_GENB_ACTCMPAD_ONE 0x000000C0 |
#define PWM_2_GENB_ACTCMPAU_M 0x00000030 |
#define PWM_2_GENB_ACTCMPAU_NONE 0x00000000 |
#define PWM_2_GENB_ACTCMPAU_INV 0x00000010 |
#define PWM_2_GENB_ACTCMPAU_ZERO 0x00000020 |
#define PWM_2_GENB_ACTCMPAU_ONE 0x00000030 |
#define PWM_2_GENB_ACTLOAD_M 0x0000000C |
#define PWM_2_GENB_ACTLOAD_NONE 0x00000000 |
#define PWM_2_GENB_ACTLOAD_INV 0x00000004 |
#define PWM_2_GENB_ACTLOAD_ZERO 0x00000008 |
#define PWM_2_GENB_ACTLOAD_ONE 0x0000000C |
#define PWM_2_GENB_ACTZERO_M 0x00000003 |
#define PWM_2_GENB_ACTZERO_NONE 0x00000000 |
#define PWM_2_GENB_ACTZERO_INV 0x00000001 |
#define PWM_2_GENB_ACTZERO_ZERO 0x00000002 |
#define PWM_2_GENB_ACTZERO_ONE 0x00000003 |
#define PWM_2_DBCTL_ENABLE 0x00000001 |
#define PWM_2_DBRISE_RISEDELAY_M 0x00000FFF |
#define PWM_2_DBRISE_RISEDELAY_S 0 |
#define PWM_2_DBFALL_FALLDELAY_M 0x00000FFF |
#define PWM_2_DBFALL_FALLDELAY_S 0 |
#define PWM_2_FLTSRC0_FAULT3 0x00000008 |
#define PWM_2_FLTSRC0_FAULT2 0x00000004 |
#define PWM_2_FLTSRC0_FAULT1 0x00000002 |
#define PWM_2_FLTSRC0_FAULT0 0x00000001 |
#define PWM_2_FLTSRC1_DCMP7 0x00000080 |
#define PWM_2_FLTSRC1_DCMP6 0x00000040 |
#define PWM_2_FLTSRC1_DCMP5 0x00000020 |
#define PWM_2_FLTSRC1_DCMP4 0x00000010 |
#define PWM_2_FLTSRC1_DCMP3 0x00000008 |
#define PWM_2_FLTSRC1_DCMP2 0x00000004 |
#define PWM_2_FLTSRC1_DCMP1 0x00000002 |
#define PWM_2_FLTSRC1_DCMP0 0x00000001 |
#define PWM_2_MINFLTPER_MFP_M 0x0000FFFF |
#define PWM_2_MINFLTPER_MFP_S 0 |
#define PWM_3_CTL_LATCH 0x00040000 |
#define PWM_3_CTL_MINFLTPER 0x00020000 |
#define PWM_3_CTL_FLTSRC 0x00010000 |
#define PWM_3_CTL_DBFALLUPD_M 0x0000C000 |
#define PWM_3_CTL_DBFALLUPD_I 0x00000000 |
#define PWM_3_CTL_DBFALLUPD_LS 0x00008000 |
#define PWM_3_CTL_DBFALLUPD_GS 0x0000C000 |
#define PWM_3_CTL_DBRISEUPD_M 0x00003000 |
#define PWM_3_CTL_DBRISEUPD_I 0x00000000 |
#define PWM_3_CTL_DBRISEUPD_LS 0x00002000 |
#define PWM_3_CTL_DBRISEUPD_GS 0x00003000 |
#define PWM_3_CTL_DBCTLUPD_M 0x00000C00 |
#define PWM_3_CTL_DBCTLUPD_I 0x00000000 |
#define PWM_3_CTL_DBCTLUPD_LS 0x00000800 |
#define PWM_3_CTL_DBCTLUPD_GS 0x00000C00 |
#define PWM_3_CTL_GENBUPD_M 0x00000300 |
#define PWM_3_CTL_GENBUPD_I 0x00000000 |
#define PWM_3_CTL_GENBUPD_LS 0x00000200 |
#define PWM_3_CTL_GENBUPD_GS 0x00000300 |
#define PWM_3_CTL_GENAUPD_M 0x000000C0 |
#define PWM_3_CTL_GENAUPD_I 0x00000000 |
#define PWM_3_CTL_GENAUPD_LS 0x00000080 |
#define PWM_3_CTL_GENAUPD_GS 0x000000C0 |
#define PWM_3_CTL_CMPBUPD 0x00000020 |
#define PWM_3_CTL_CMPAUPD 0x00000010 |
#define PWM_3_CTL_LOADUPD 0x00000008 |
#define PWM_3_CTL_DEBUG 0x00000004 |
#define PWM_3_CTL_MODE 0x00000002 |
#define PWM_3_CTL_ENABLE 0x00000001 |
#define PWM_3_INTEN_TRCMPBD 0x00002000 |
#define PWM_3_INTEN_TRCMPBU 0x00001000 |
#define PWM_3_INTEN_TRCMPAD 0x00000800 |
#define PWM_3_INTEN_TRCMPAU 0x00000400 |
#define PWM_3_INTEN_TRCNTLOAD 0x00000200 |
#define PWM_3_INTEN_TRCNTZERO 0x00000100 |
#define PWM_3_INTEN_INTCMPBD 0x00000020 |
#define PWM_3_INTEN_INTCMPBU 0x00000010 |
#define PWM_3_INTEN_INTCMPAD 0x00000008 |
#define PWM_3_INTEN_INTCMPAU 0x00000004 |
#define PWM_3_INTEN_INTCNTLOAD 0x00000002 |
#define PWM_3_INTEN_INTCNTZERO 0x00000001 |
#define PWM_3_RIS_INTCMPBD 0x00000020 |
#define PWM_3_RIS_INTCMPBU 0x00000010 |
#define PWM_3_RIS_INTCMPAD 0x00000008 |
#define PWM_3_RIS_INTCMPAU 0x00000004 |
#define PWM_3_RIS_INTCNTLOAD 0x00000002 |
#define PWM_3_RIS_INTCNTZERO 0x00000001 |
#define PWM_3_ISC_INTCMPBD 0x00000020 |
#define PWM_3_ISC_INTCMPBU 0x00000010 |
#define PWM_3_ISC_INTCMPAD 0x00000008 |
#define PWM_3_ISC_INTCMPAU 0x00000004 |
#define PWM_3_ISC_INTCNTLOAD 0x00000002 |
#define PWM_3_ISC_INTCNTZERO 0x00000001 |
#define PWM_3_LOAD_LOAD_M 0x0000FFFF |
#define PWM_3_LOAD_LOAD_S 0 |
#define PWM_3_COUNT_COUNT_M 0x0000FFFF |
#define PWM_3_COUNT_COUNT_S 0 |
#define PWM_3_CMPA_COMPA_M 0x0000FFFF |
#define PWM_3_CMPA_COMPA_S 0 |
#define PWM_3_CMPB_COMPB_M 0x0000FFFF |
#define PWM_3_CMPB_COMPB_S 0 |
#define PWM_3_GENA_ACTCMPBD_M 0x00000C00 |
#define PWM_3_GENA_ACTCMPBD_NONE 0x00000000 |
#define PWM_3_GENA_ACTCMPBD_INV 0x00000400 |
#define PWM_3_GENA_ACTCMPBD_ZERO 0x00000800 |
#define PWM_3_GENA_ACTCMPBD_ONE 0x00000C00 |
#define PWM_3_GENA_ACTCMPBU_M 0x00000300 |
#define PWM_3_GENA_ACTCMPBU_NONE 0x00000000 |
#define PWM_3_GENA_ACTCMPBU_INV 0x00000100 |
#define PWM_3_GENA_ACTCMPBU_ZERO 0x00000200 |
#define PWM_3_GENA_ACTCMPBU_ONE 0x00000300 |
#define PWM_3_GENA_ACTCMPAD_M 0x000000C0 |
#define PWM_3_GENA_ACTCMPAD_NONE 0x00000000 |
#define PWM_3_GENA_ACTCMPAD_INV 0x00000040 |
#define PWM_3_GENA_ACTCMPAD_ZERO 0x00000080 |
#define PWM_3_GENA_ACTCMPAD_ONE 0x000000C0 |
#define PWM_3_GENA_ACTCMPAU_M 0x00000030 |
#define PWM_3_GENA_ACTCMPAU_NONE 0x00000000 |
#define PWM_3_GENA_ACTCMPAU_INV 0x00000010 |
#define PWM_3_GENA_ACTCMPAU_ZERO 0x00000020 |
#define PWM_3_GENA_ACTCMPAU_ONE 0x00000030 |
#define PWM_3_GENA_ACTLOAD_M 0x0000000C |
#define PWM_3_GENA_ACTLOAD_NONE 0x00000000 |
#define PWM_3_GENA_ACTLOAD_INV 0x00000004 |
#define PWM_3_GENA_ACTLOAD_ZERO 0x00000008 |
#define PWM_3_GENA_ACTLOAD_ONE 0x0000000C |
#define PWM_3_GENA_ACTZERO_M 0x00000003 |
#define PWM_3_GENA_ACTZERO_NONE 0x00000000 |
#define PWM_3_GENA_ACTZERO_INV 0x00000001 |
#define PWM_3_GENA_ACTZERO_ZERO 0x00000002 |
#define PWM_3_GENA_ACTZERO_ONE 0x00000003 |
#define PWM_3_GENB_ACTCMPBD_M 0x00000C00 |
#define PWM_3_GENB_ACTCMPBD_NONE 0x00000000 |
#define PWM_3_GENB_ACTCMPBD_INV 0x00000400 |
#define PWM_3_GENB_ACTCMPBD_ZERO 0x00000800 |
#define PWM_3_GENB_ACTCMPBD_ONE 0x00000C00 |
#define PWM_3_GENB_ACTCMPBU_M 0x00000300 |
#define PWM_3_GENB_ACTCMPBU_NONE 0x00000000 |
#define PWM_3_GENB_ACTCMPBU_INV 0x00000100 |
#define PWM_3_GENB_ACTCMPBU_ZERO 0x00000200 |
#define PWM_3_GENB_ACTCMPBU_ONE 0x00000300 |
#define PWM_3_GENB_ACTCMPAD_M 0x000000C0 |
#define PWM_3_GENB_ACTCMPAD_NONE 0x00000000 |
#define PWM_3_GENB_ACTCMPAD_INV 0x00000040 |
#define PWM_3_GENB_ACTCMPAD_ZERO 0x00000080 |
#define PWM_3_GENB_ACTCMPAD_ONE 0x000000C0 |
#define PWM_3_GENB_ACTCMPAU_M 0x00000030 |
#define PWM_3_GENB_ACTCMPAU_NONE 0x00000000 |
#define PWM_3_GENB_ACTCMPAU_INV 0x00000010 |
#define PWM_3_GENB_ACTCMPAU_ZERO 0x00000020 |
#define PWM_3_GENB_ACTCMPAU_ONE 0x00000030 |
#define PWM_3_GENB_ACTLOAD_M 0x0000000C |
#define PWM_3_GENB_ACTLOAD_NONE 0x00000000 |
#define PWM_3_GENB_ACTLOAD_INV 0x00000004 |
#define PWM_3_GENB_ACTLOAD_ZERO 0x00000008 |
#define PWM_3_GENB_ACTLOAD_ONE 0x0000000C |
#define PWM_3_GENB_ACTZERO_M 0x00000003 |
#define PWM_3_GENB_ACTZERO_NONE 0x00000000 |
#define PWM_3_GENB_ACTZERO_INV 0x00000001 |
#define PWM_3_GENB_ACTZERO_ZERO 0x00000002 |
#define PWM_3_GENB_ACTZERO_ONE 0x00000003 |
#define PWM_3_DBCTL_ENABLE 0x00000001 |
#define PWM_3_DBRISE_RISEDELAY_M 0x00000FFF |
#define PWM_3_DBRISE_RISEDELAY_S 0 |
#define PWM_3_DBFALL_FALLDELAY_M 0x00000FFF |
#define PWM_3_DBFALL_FALLDELAY_S 0 |
#define PWM_3_FLTSRC0_FAULT3 0x00000008 |
#define PWM_3_FLTSRC0_FAULT2 0x00000004 |
#define PWM_3_FLTSRC0_FAULT1 0x00000002 |
#define PWM_3_FLTSRC0_FAULT0 0x00000001 |
#define PWM_3_FLTSRC1_DCMP7 0x00000080 |
#define PWM_3_FLTSRC1_DCMP6 0x00000040 |
#define PWM_3_FLTSRC1_DCMP5 0x00000020 |
#define PWM_3_FLTSRC1_DCMP4 0x00000010 |
#define PWM_3_FLTSRC1_DCMP3 0x00000008 |
#define PWM_3_FLTSRC1_DCMP2 0x00000004 |
#define PWM_3_FLTSRC1_DCMP1 0x00000002 |
#define PWM_3_FLTSRC1_DCMP0 0x00000001 |
#define PWM_3_MINFLTPER_MFP_M 0x0000FFFF |
#define PWM_3_MINFLTPER_MFP_S 0 |
#define PWM_0_FLTSEN_FAULT3 0x00000008 |
#define PWM_0_FLTSEN_FAULT2 0x00000004 |
#define PWM_0_FLTSEN_FAULT1 0x00000002 |
#define PWM_0_FLTSEN_FAULT0 0x00000001 |
#define PWM_0_FLTSTAT0_FAULT3 0x00000008 |
#define PWM_0_FLTSTAT0_FAULT2 0x00000004 |
#define PWM_0_FLTSTAT0_FAULT1 0x00000002 |
#define PWM_0_FLTSTAT0_FAULT0 0x00000001 |
#define PWM_0_FLTSTAT1_DCMP7 0x00000080 |
#define PWM_0_FLTSTAT1_DCMP6 0x00000040 |
#define PWM_0_FLTSTAT1_DCMP5 0x00000020 |
#define PWM_0_FLTSTAT1_DCMP4 0x00000010 |
#define PWM_0_FLTSTAT1_DCMP3 0x00000008 |
#define PWM_0_FLTSTAT1_DCMP2 0x00000004 |
#define PWM_0_FLTSTAT1_DCMP1 0x00000002 |
#define PWM_0_FLTSTAT1_DCMP0 0x00000001 |
#define PWM_1_FLTSEN_FAULT3 0x00000008 |
#define PWM_1_FLTSEN_FAULT2 0x00000004 |
#define PWM_1_FLTSEN_FAULT1 0x00000002 |
#define PWM_1_FLTSEN_FAULT0 0x00000001 |
#define PWM_1_FLTSTAT0_FAULT3 0x00000008 |
#define PWM_1_FLTSTAT0_FAULT2 0x00000004 |
#define PWM_1_FLTSTAT0_FAULT1 0x00000002 |
#define PWM_1_FLTSTAT0_FAULT0 0x00000001 |
#define PWM_1_FLTSTAT1_DCMP7 0x00000080 |
#define PWM_1_FLTSTAT1_DCMP6 0x00000040 |
#define PWM_1_FLTSTAT1_DCMP5 0x00000020 |
#define PWM_1_FLTSTAT1_DCMP4 0x00000010 |
#define PWM_1_FLTSTAT1_DCMP3 0x00000008 |
#define PWM_1_FLTSTAT1_DCMP2 0x00000004 |
#define PWM_1_FLTSTAT1_DCMP1 0x00000002 |
#define PWM_1_FLTSTAT1_DCMP0 0x00000001 |
#define PWM_2_FLTSEN_FAULT3 0x00000008 |
#define PWM_2_FLTSEN_FAULT2 0x00000004 |
#define PWM_2_FLTSEN_FAULT1 0x00000002 |
#define PWM_2_FLTSEN_FAULT0 0x00000001 |
#define PWM_2_FLTSTAT0_FAULT3 0x00000008 |
#define PWM_2_FLTSTAT0_FAULT2 0x00000004 |
#define PWM_2_FLTSTAT0_FAULT1 0x00000002 |
#define PWM_2_FLTSTAT0_FAULT0 0x00000001 |
#define PWM_2_FLTSTAT1_DCMP7 0x00000080 |
#define PWM_2_FLTSTAT1_DCMP6 0x00000040 |
#define PWM_2_FLTSTAT1_DCMP5 0x00000020 |
#define PWM_2_FLTSTAT1_DCMP4 0x00000010 |
#define PWM_2_FLTSTAT1_DCMP3 0x00000008 |
#define PWM_2_FLTSTAT1_DCMP2 0x00000004 |
#define PWM_2_FLTSTAT1_DCMP1 0x00000002 |
#define PWM_2_FLTSTAT1_DCMP0 0x00000001 |
#define PWM_3_FLTSEN_FAULT3 0x00000008 |
#define PWM_3_FLTSEN_FAULT2 0x00000004 |
#define PWM_3_FLTSEN_FAULT1 0x00000002 |
#define PWM_3_FLTSEN_FAULT0 0x00000001 |
#define PWM_3_FLTSTAT0_FAULT3 0x00000008 |
#define PWM_3_FLTSTAT0_FAULT2 0x00000004 |
#define PWM_3_FLTSTAT0_FAULT1 0x00000002 |
#define PWM_3_FLTSTAT0_FAULT0 0x00000001 |
#define PWM_3_FLTSTAT1_DCMP7 0x00000080 |
#define PWM_3_FLTSTAT1_DCMP6 0x00000040 |
#define PWM_3_FLTSTAT1_DCMP5 0x00000020 |
#define PWM_3_FLTSTAT1_DCMP4 0x00000010 |
#define PWM_3_FLTSTAT1_DCMP3 0x00000008 |
#define PWM_3_FLTSTAT1_DCMP2 0x00000004 |
#define PWM_3_FLTSTAT1_DCMP1 0x00000002 |
#define PWM_3_FLTSTAT1_DCMP0 0x00000001 |
#define PWM_PP_GCNT_M 0x0000000F |
#define PWM_PP_FCNT_M 0x000000F0 |
#define PWM_PP_ESYNC 0x00000100 |
#define PWM_PP_EFAULT 0x00000200 |
#define PWM_PP_ONE 0x00000400 |
#define PWM_PP_GCNT_S 0 |
#define PWM_PP_FCNT_S 4 |
#define PWM_CC_USEPWM 0x00000100 |
Referenced by PWMClockGet(), and PWMClockSet().
#define PWM_CC_PWMDIV_M 0x00000007 |
Referenced by PWMClockGet(), and PWMClockSet().
#define PWM_CC_PWMDIV_2 0x00000000 |
#define PWM_CC_PWMDIV_4 0x00000001 |
#define PWM_CC_PWMDIV_8 0x00000002 |
#define PWM_CC_PWMDIV_16 0x00000003 |
#define PWM_CC_PWMDIV_32 0x00000004 |
#define PWM_CC_PWMDIV_64 0x00000005 |
#define PWM_O_X_CTL 0x00000000 |
Referenced by PWMGenConfigure(), PWMGenDisable(), PWMGenEnable(), PWMGenPeriodGet(), PWMGenPeriodSet(), PWMPulseWidthGet(), and PWMPulseWidthSet().
#define PWM_O_X_INTEN 0x00000004 |
Referenced by PWMGenIntTrigDisable(), and PWMGenIntTrigEnable().
#define PWM_O_X_RIS 0x00000008 |
Referenced by PWMGenIntStatus().
#define PWM_O_X_ISC 0x0000000C |
Referenced by PWMGenIntClear(), and PWMGenIntStatus().
#define PWM_O_X_LOAD 0x00000010 |
Referenced by PWMGenPeriodGet(), PWMGenPeriodSet(), PWMPulseWidthGet(), and PWMPulseWidthSet().
#define PWM_O_X_COUNT 0x00000014 |
#define PWM_O_X_CMPA 0x00000018 |
Referenced by PWMPulseWidthGet(), and PWMPulseWidthSet().
#define PWM_O_X_CMPB 0x0000001C |
Referenced by PWMPulseWidthGet(), and PWMPulseWidthSet().
#define PWM_O_X_GENA 0x00000020 |
Referenced by PWMGenConfigure().
#define PWM_O_X_GENB 0x00000024 |
Referenced by PWMGenConfigure().
#define PWM_O_X_DBCTL 0x00000028 |
Referenced by PWMDeadBandDisable(), and PWMDeadBandEnable().
#define PWM_O_X_DBRISE 0x0000002C |
Referenced by PWMDeadBandEnable().
#define PWM_O_X_DBFALL 0x00000030 |
Referenced by PWMDeadBandEnable().
#define PWM_O_X_FLTSRC0 0x00000034 |
Referenced by PWMGenFaultTriggerGet(), and PWMGenFaultTriggerSet().
#define PWM_O_X_FLTSRC1 0x00000038 |
Referenced by PWMGenFaultTriggerGet(), and PWMGenFaultTriggerSet().
#define PWM_O_X_MINFLTPER 0x0000003C |
Referenced by PWMGenFaultConfigure().
#define PWM_GEN_0_OFFSET 0x00000040 |
#define PWM_GEN_1_OFFSET 0x00000080 |
#define PWM_GEN_2_OFFSET 0x000000C0 |
#define PWM_GEN_3_OFFSET 0x00000100 |
#define PWM_X_CTL_LATCH 0x00040000 |
Referenced by PWMGenConfigure().
#define PWM_X_CTL_MINFLTPER 0x00020000 |
Referenced by PWMGenConfigure().
#define PWM_X_CTL_FLTSRC 0x00010000 |
Referenced by PWMGenConfigure().
#define PWM_X_CTL_DBFALLUPD_M 0x0000C000 |
Referenced by PWMGenConfigure().
#define PWM_X_CTL_DBFALLUPD_I 0x00000000 |
#define PWM_X_CTL_DBFALLUPD_LS 0x00008000 |
#define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 |
#define PWM_X_CTL_DBRISEUPD_M 0x00003000 |
Referenced by PWMGenConfigure().
#define PWM_X_CTL_DBRISEUPD_I 0x00000000 |
#define PWM_X_CTL_DBRISEUPD_LS 0x00002000 |
#define PWM_X_CTL_DBRISEUPD_GS 0x00003000 |
#define PWM_X_CTL_DBCTLUPD_M 0x00000C00 |
Referenced by PWMGenConfigure().
#define PWM_X_CTL_DBCTLUPD_I 0x00000000 |
#define PWM_X_CTL_DBCTLUPD_LS 0x00000800 |
#define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 |
#define PWM_X_CTL_GENBUPD_M 0x00000300 |
Referenced by PWMGenConfigure().
#define PWM_X_CTL_GENBUPD_I 0x00000000 |
#define PWM_X_CTL_GENBUPD_LS 0x00000200 |
#define PWM_X_CTL_GENBUPD_GS 0x00000300 |
#define PWM_X_CTL_GENAUPD_M 0x000000C0 |
Referenced by PWMGenConfigure().
#define PWM_X_CTL_GENAUPD_I 0x00000000 |
#define PWM_X_CTL_GENAUPD_LS 0x00000080 |
#define PWM_X_CTL_GENAUPD_GS 0x000000C0 |
#define PWM_X_CTL_CMPBUPD 0x00000020 |
Referenced by PWMGenConfigure().
#define PWM_X_CTL_CMPAUPD 0x00000010 |
Referenced by PWMGenConfigure().
#define PWM_X_CTL_LOADUPD 0x00000008 |
Referenced by PWMGenConfigure().
#define PWM_X_CTL_DEBUG 0x00000004 |
Referenced by PWMGenConfigure().
#define PWM_X_CTL_MODE 0x00000002 |
Referenced by PWMGenConfigure(), PWMGenPeriodGet(), PWMGenPeriodSet(), PWMPulseWidthGet(), and PWMPulseWidthSet().
#define PWM_X_CTL_ENABLE 0x00000001 |
Referenced by PWMGenDisable(), and PWMGenEnable().
#define PWM_X_INTEN_TRCMPBD 0x00002000 |
#define PWM_X_INTEN_TRCMPBU 0x00001000 |
#define PWM_X_INTEN_TRCMPAD 0x00000800 |
#define PWM_X_INTEN_TRCMPAU 0x00000400 |
#define PWM_X_INTEN_TRCNTLOAD 0x00000200 |
#define PWM_X_INTEN_TRCNTZERO 0x00000100 |
#define PWM_X_INTEN_INTCMPBD 0x00000020 |
#define PWM_X_INTEN_INTCMPBU 0x00000010 |
#define PWM_X_INTEN_INTCMPAD 0x00000008 |
#define PWM_X_INTEN_INTCMPAU 0x00000004 |
#define PWM_X_INTEN_INTCNTLOAD 0x00000002 |
#define PWM_X_INTEN_INTCNTZERO 0x00000001 |
#define PWM_X_RIS_INTCMPBD 0x00000020 |
#define PWM_X_RIS_INTCMPBU 0x00000010 |
#define PWM_X_RIS_INTCMPAD 0x00000008 |
#define PWM_X_RIS_INTCMPAU 0x00000004 |
#define PWM_X_RIS_INTCNTLOAD 0x00000002 |
#define PWM_X_RIS_INTCNTZERO 0x00000001 |
#define PWM_X_ISC_INTCMPBD 0x00000020 |
#define PWM_X_ISC_INTCMPBU 0x00000010 |
#define PWM_X_ISC_INTCMPAD 0x00000008 |
#define PWM_X_ISC_INTCMPAU 0x00000004 |
#define PWM_X_ISC_INTCNTLOAD 0x00000002 |
#define PWM_X_ISC_INTCNTZERO 0x00000001 |
#define PWM_X_LOAD_M 0x0000FFFF |
#define PWM_X_LOAD_S 0 |
#define PWM_X_COUNT_M 0x0000FFFF |
#define PWM_X_COUNT_S 0 |
#define PWM_X_CMPA_M 0x0000FFFF |
#define PWM_X_CMPA_S 0 |
#define PWM_X_CMPB_M 0x0000FFFF |
#define PWM_X_CMPB_S 0 |
#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 |
#define PWM_X_GENA_ACTCMPBD_NONE 0x00000000 |
#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 |
#define PWM_X_GENA_ACTCMPBD_ZERO 0x00000800 |
#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 |
#define PWM_X_GENA_ACTCMPBU_M 0x00000300 |
#define PWM_X_GENA_ACTCMPBU_NONE 0x00000000 |
#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 |
#define PWM_X_GENA_ACTCMPBU_ZERO 0x00000200 |
#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 |
#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 |
#define PWM_X_GENA_ACTCMPAD_NONE 0x00000000 |
#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 |
#define PWM_X_GENA_ACTCMPAD_ZERO 0x00000080 |
Referenced by PWMGenConfigure().
#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 |
#define PWM_X_GENA_ACTCMPAU_M 0x00000030 |
#define PWM_X_GENA_ACTCMPAU_NONE 0x00000000 |
#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 |
#define PWM_X_GENA_ACTCMPAU_ZERO 0x00000020 |
#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 |
Referenced by PWMGenConfigure().
#define PWM_X_GENA_ACTLOAD_M 0x0000000C |
#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 |
#define PWM_X_GENA_ACTLOAD_INV 0x00000004 |
#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 |
#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C |
Referenced by PWMGenConfigure().
#define PWM_X_GENA_ACTZERO_M 0x00000003 |
#define PWM_X_GENA_ACTZERO_NONE 0x00000000 |
#define PWM_X_GENA_ACTZERO_INV 0x00000001 |
#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 |
#define PWM_X_GENA_ACTZERO_ONE 0x00000003 |
#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 |
#define PWM_X_GENB_ACTCMPBD_NONE 0x00000000 |
#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 |
#define PWM_X_GENB_ACTCMPBD_ZERO 0x00000800 |
Referenced by PWMGenConfigure().
#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 |
#define PWM_X_GENB_ACTCMPBU_M 0x00000300 |
#define PWM_X_GENB_ACTCMPBU_NONE 0x00000000 |
#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 |
#define PWM_X_GENB_ACTCMPBU_ZERO 0x00000200 |
#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 |
Referenced by PWMGenConfigure().
#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 |
#define PWM_X_GENB_ACTCMPAD_NONE 0x00000000 |
#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 |
#define PWM_X_GENB_ACTCMPAD_ZERO 0x00000080 |
#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 |
#define PWM_X_GENB_ACTCMPAU_M 0x00000030 |
#define PWM_X_GENB_ACTCMPAU_NONE 0x00000000 |
#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 |
#define PWM_X_GENB_ACTCMPAU_ZERO 0x00000020 |
#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 |
#define PWM_X_GENB_ACTLOAD_M 0x0000000C |
#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 |
#define PWM_X_GENB_ACTLOAD_INV 0x00000004 |
#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 |
#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C |
Referenced by PWMGenConfigure().
#define PWM_X_GENB_ACTZERO_M 0x00000003 |
#define PWM_X_GENB_ACTZERO_NONE 0x00000000 |
#define PWM_X_GENB_ACTZERO_INV 0x00000001 |
#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 |
#define PWM_X_GENB_ACTZERO_ONE 0x00000003 |
#define PWM_X_DBCTL_ENABLE 0x00000001 |
Referenced by PWMDeadBandDisable(), and PWMDeadBandEnable().
#define PWM_X_DBRISE_DELAY_M 0x00000FFF |
#define PWM_X_DBRISE_DELAY_S 0 |
#define PWM_X_DBFALL_DELAY_M 0x00000FFF |
#define PWM_X_DBFALL_DELAY_S 0 |
#define PWM_X_FLTSRC0_FAULT3 0x00000008 |
#define PWM_X_FLTSRC0_FAULT2 0x00000004 |
#define PWM_X_FLTSRC0_FAULT1 0x00000002 |
#define PWM_X_FLTSRC0_FAULT0 0x00000001 |
#define PWM_X_FLTSRC1_DCMP7 0x00000080 |
#define PWM_X_FLTSRC1_DCMP6 0x00000040 |
#define PWM_X_FLTSRC1_DCMP5 0x00000020 |
#define PWM_X_FLTSRC1_DCMP4 0x00000010 |
#define PWM_X_FLTSRC1_DCMP3 0x00000008 |
#define PWM_X_FLTSRC1_DCMP2 0x00000004 |
#define PWM_X_FLTSRC1_DCMP1 0x00000002 |
#define PWM_X_FLTSRC1_DCMP0 0x00000001 |
#define PWM_X_MINFLTPER_M 0x0000FFFF |
Referenced by PWMGenFaultConfigure().
#define PWM_X_MINFLTPER_S 0 |
#define PWM_O_X_FLTSEN 0x00000000 |
Referenced by PWMGenFaultConfigure().
#define PWM_O_X_FLTSTAT0 0x00000004 |
Referenced by PWMGenFaultClear(), and PWMGenFaultStatus().
#define PWM_O_X_FLTSTAT1 0x00000008 |
Referenced by PWMGenFaultClear(), and PWMGenFaultStatus().
#define PWM_EXT_0_OFFSET 0x00000800 |
#define PWM_EXT_1_OFFSET 0x00000880 |
#define PWM_EXT_2_OFFSET 0x00000900 |
#define PWM_EXT_3_OFFSET 0x00000980 |
#define PWM_X_FLTSEN_FAULT3 0x00000008 |
#define PWM_X_FLTSEN_FAULT2 0x00000004 |
#define PWM_X_FLTSEN_FAULT1 0x00000002 |
#define PWM_X_FLTSEN_FAULT0 0x00000001 |
#define PWM_X_FLTSTAT0_FAULT3 0x00000008 |
#define PWM_X_FLTSTAT0_FAULT2 0x00000004 |
#define PWM_X_FLTSTAT0_FAULT1 0x00000002 |
#define PWM_X_FLTSTAT0_FAULT0 0x00000001 |
#define PWM_X_FLTSTAT1_DCMP7 0x00000080 |
#define PWM_X_FLTSTAT1_DCMP6 0x00000040 |
#define PWM_X_FLTSTAT1_DCMP5 0x00000020 |
#define PWM_X_FLTSTAT1_DCMP4 0x00000010 |
#define PWM_X_FLTSTAT1_DCMP3 0x00000008 |
#define PWM_X_FLTSTAT1_DCMP2 0x00000004 |
#define PWM_X_FLTSTAT1_DCMP1 0x00000002 |
#define PWM_X_FLTSTAT1_DCMP0 0x00000001 |