hw_i2c.h
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1 //*****************************************************************************
2 //
3 // hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
4 //
5 // Copyright (c) 2005-2017 Texas Instruments Incorporated. All rights reserved.
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36 //*****************************************************************************
37 
38 #ifndef __HW_I2C_H__
39 #define __HW_I2C_H__
40 
41 //*****************************************************************************
42 //
43 // The following are defines for the I2C register offsets.
44 //
45 //*****************************************************************************
46 #define I2C_O_MSA 0x00000000 // I2C Master Slave Address
47 #define I2C_O_MCS 0x00000004 // I2C Master Control/Status
48 #define I2C_O_MDR 0x00000008 // I2C Master Data
49 #define I2C_O_MTPR 0x0000000C // I2C Master Timer Period
50 #define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask
51 #define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status
52 #define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt
53  // Status
54 #define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear
55 #define I2C_O_MCR 0x00000020 // I2C Master Configuration
56 #define I2C_O_MCLKOCNT 0x00000024 // I2C Master Clock Low Timeout
57  // Count
58 #define I2C_O_MBMON 0x0000002C // I2C Master Bus Monitor
59 #define I2C_O_MBLEN 0x00000030 // I2C Master Burst Length
60 #define I2C_O_MBCNT 0x00000034 // I2C Master Burst Count
61 #define I2C_O_SOAR 0x00000800 // I2C Slave Own Address
62 #define I2C_O_SCSR 0x00000804 // I2C Slave Control/Status
63 #define I2C_O_SDR 0x00000808 // I2C Slave Data
64 #define I2C_O_SIMR 0x0000080C // I2C Slave Interrupt Mask
65 #define I2C_O_SRIS 0x00000810 // I2C Slave Raw Interrupt Status
66 #define I2C_O_SMIS 0x00000814 // I2C Slave Masked Interrupt
67  // Status
68 #define I2C_O_SICR 0x00000818 // I2C Slave Interrupt Clear
69 #define I2C_O_SOAR2 0x0000081C // I2C Slave Own Address 2
70 #define I2C_O_SACKCTL 0x00000820 // I2C Slave ACK Control
71 #define I2C_O_FIFODATA 0x00000F00 // I2C FIFO Data
72 #define I2C_O_FIFOCTL 0x00000F04 // I2C FIFO Control
73 #define I2C_O_FIFOSTATUS 0x00000F08 // I2C FIFO Status
74 #define I2C_O_PP 0x00000FC0 // I2C Peripheral Properties
75 #define I2C_O_PC 0x00000FC4 // I2C Peripheral Configuration
76 
77 //*****************************************************************************
78 //
79 // The following are defines for the bit fields in the I2C_O_MSA register.
80 //
81 //*****************************************************************************
82 #define I2C_MSA_SA_M 0x000000FE // I2C Slave Address
83 #define I2C_MSA_RS 0x00000001 // Receive not send
84 #define I2C_MSA_SA_S 1
85 
86 //*****************************************************************************
87 //
88 // The following are defines for the bit fields in the I2C_O_MCS register.
89 //
90 //*****************************************************************************
91 #define I2C_MCS_ACTDMARX 0x80000000 // DMA RX Active Status
92 #define I2C_MCS_ACTDMATX 0x40000000 // DMA TX Active Status
93 #define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error
94 #define I2C_MCS_BURST 0x00000040 // Burst Enable
95 #define I2C_MCS_BUSBSY 0x00000040 // Bus Busy
96 #define I2C_MCS_IDLE 0x00000020 // I2C Idle
97 #define I2C_MCS_QCMD 0x00000020 // Quick Command
98 #define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost
99 #define I2C_MCS_HS 0x00000010 // High-Speed Enable
100 #define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable
101 #define I2C_MCS_DATACK 0x00000008 // Acknowledge Data
102 #define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address
103 #define I2C_MCS_STOP 0x00000004 // Generate STOP
104 #define I2C_MCS_ERROR 0x00000002 // Error
105 #define I2C_MCS_START 0x00000002 // Generate START
106 #define I2C_MCS_RUN 0x00000001 // I2C Master Enable
107 #define I2C_MCS_BUSY 0x00000001 // I2C Busy
108 
109 //*****************************************************************************
110 //
111 // The following are defines for the bit fields in the I2C_O_MDR register.
112 //
113 //*****************************************************************************
114 #define I2C_MDR_DATA_M 0x000000FF // This byte contains the data
115  // transferred during a transaction
116 #define I2C_MDR_DATA_S 0
117 
118 //*****************************************************************************
119 //
120 // The following are defines for the bit fields in the I2C_O_MTPR register.
121 //
122 //*****************************************************************************
123 #define I2C_MTPR_PULSEL_M 0x00070000 // Glitch Suppression Pulse Width
124 #define I2C_MTPR_PULSEL_BYPASS 0x00000000 // Bypass
125 #define I2C_MTPR_PULSEL_1 0x00010000 // 1 clock
126 #define I2C_MTPR_PULSEL_2 0x00020000 // 2 clocks
127 #define I2C_MTPR_PULSEL_3 0x00030000 // 3 clocks
128 #define I2C_MTPR_PULSEL_4 0x00040000 // 4 clocks
129 #define I2C_MTPR_PULSEL_8 0x00050000 // 8 clocks
130 #define I2C_MTPR_PULSEL_16 0x00060000 // 16 clocks
131 #define I2C_MTPR_PULSEL_31 0x00070000 // 31 clocks
132 #define I2C_MTPR_HS 0x00000080 // High-Speed Enable
133 #define I2C_MTPR_TPR_M 0x0000007F // Timer Period
134 #define I2C_MTPR_TPR_S 0
135 
136 //*****************************************************************************
137 //
138 // The following are defines for the bit fields in the I2C_O_MIMR register.
139 //
140 //*****************************************************************************
141 #define I2C_MIMR_RXFFIM 0x00000800 // Receive FIFO Full Interrupt Mask
142 #define I2C_MIMR_TXFEIM 0x00000400 // Transmit FIFO Empty Interrupt
143  // Mask
144 #define I2C_MIMR_RXIM 0x00000200 // Receive FIFO Request Interrupt
145  // Mask
146 #define I2C_MIMR_TXIM 0x00000100 // Transmit FIFO Request Interrupt
147  // Mask
148 #define I2C_MIMR_ARBLOSTIM 0x00000080 // Arbitration Lost Interrupt Mask
149 #define I2C_MIMR_STOPIM 0x00000040 // STOP Detection Interrupt Mask
150 #define I2C_MIMR_STARTIM 0x00000020 // START Detection Interrupt Mask
151 #define I2C_MIMR_NACKIM 0x00000010 // Address/Data NACK Interrupt Mask
152 #define I2C_MIMR_DMATXIM 0x00000008 // Transmit DMA Interrupt Mask
153 #define I2C_MIMR_DMARXIM 0x00000004 // Receive DMA Interrupt Mask
154 #define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask
155 #define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask
156 
157 //*****************************************************************************
158 //
159 // The following are defines for the bit fields in the I2C_O_MRIS register.
160 //
161 //*****************************************************************************
162 #define I2C_MRIS_RXFFRIS 0x00000800 // Receive FIFO Full Raw Interrupt
163  // Status
164 #define I2C_MRIS_TXFERIS 0x00000400 // Transmit FIFO Empty Raw
165  // Interrupt Status
166 #define I2C_MRIS_RXRIS 0x00000200 // Receive FIFO Request Raw
167  // Interrupt Status
168 #define I2C_MRIS_TXRIS 0x00000100 // Transmit Request Raw Interrupt
169  // Status
170 #define I2C_MRIS_ARBLOSTRIS 0x00000080 // Arbitration Lost Raw Interrupt
171  // Status
172 #define I2C_MRIS_STOPRIS 0x00000040 // STOP Detection Raw Interrupt
173  // Status
174 #define I2C_MRIS_STARTRIS 0x00000020 // START Detection Raw Interrupt
175  // Status
176 #define I2C_MRIS_NACKRIS 0x00000010 // Address/Data NACK Raw Interrupt
177  // Status
178 #define I2C_MRIS_DMATXRIS 0x00000008 // Transmit DMA Raw Interrupt
179  // Status
180 #define I2C_MRIS_DMARXRIS 0x00000004 // Receive DMA Raw Interrupt Status
181 #define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt
182  // Status
183 #define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status
184 
185 //*****************************************************************************
186 //
187 // The following are defines for the bit fields in the I2C_O_MMIS register.
188 //
189 //*****************************************************************************
190 #define I2C_MMIS_RXFFMIS 0x00000800 // Receive FIFO Full Interrupt Mask
191 #define I2C_MMIS_TXFEMIS 0x00000400 // Transmit FIFO Empty Interrupt
192  // Mask
193 #define I2C_MMIS_RXMIS 0x00000200 // Receive FIFO Request Interrupt
194  // Mask
195 #define I2C_MMIS_TXMIS 0x00000100 // Transmit Request Interrupt Mask
196 #define I2C_MMIS_ARBLOSTMIS 0x00000080 // Arbitration Lost Interrupt Mask
197 #define I2C_MMIS_STOPMIS 0x00000040 // STOP Detection Interrupt Mask
198 #define I2C_MMIS_STARTMIS 0x00000020 // START Detection Interrupt Mask
199 #define I2C_MMIS_NACKMIS 0x00000010 // Address/Data NACK Interrupt Mask
200 #define I2C_MMIS_DMATXMIS 0x00000008 // Transmit DMA Interrupt Status
201 #define I2C_MMIS_DMARXMIS 0x00000004 // Receive DMA Interrupt Status
202 #define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt
203  // Status
204 #define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status
205 
206 //*****************************************************************************
207 //
208 // The following are defines for the bit fields in the I2C_O_MICR register.
209 //
210 //*****************************************************************************
211 #define I2C_MICR_RXFFIC 0x00000800 // Receive FIFO Full Interrupt
212  // Clear
213 #define I2C_MICR_TXFEIC 0x00000400 // Transmit FIFO Empty Interrupt
214  // Clear
215 #define I2C_MICR_RXIC 0x00000200 // Receive FIFO Request Interrupt
216  // Clear
217 #define I2C_MICR_TXIC 0x00000100 // Transmit FIFO Request Interrupt
218  // Clear
219 #define I2C_MICR_ARBLOSTIC 0x00000080 // Arbitration Lost Interrupt Clear
220 #define I2C_MICR_STOPIC 0x00000040 // STOP Detection Interrupt Clear
221 #define I2C_MICR_STARTIC 0x00000020 // START Detection Interrupt Clear
222 #define I2C_MICR_NACKIC 0x00000010 // Address/Data NACK Interrupt
223  // Clear
224 #define I2C_MICR_DMATXIC 0x00000008 // Transmit DMA Interrupt Clear
225 #define I2C_MICR_DMARXIC 0x00000004 // Receive DMA Interrupt Clear
226 #define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear
227 #define I2C_MICR_IC 0x00000001 // Master Interrupt Clear
228 
229 //*****************************************************************************
230 //
231 // The following are defines for the bit fields in the I2C_O_MCR register.
232 //
233 //*****************************************************************************
234 #define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable
235 #define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable
236 #define I2C_MCR_LPBK 0x00000001 // I2C Loopback
237 
238 //*****************************************************************************
239 //
240 // The following are defines for the bit fields in the I2C_O_MCLKOCNT register.
241 //
242 //*****************************************************************************
243 #define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count
244 #define I2C_MCLKOCNT_CNTL_S 0
245 
246 //*****************************************************************************
247 //
248 // The following are defines for the bit fields in the I2C_O_MBMON register.
249 //
250 //*****************************************************************************
251 #define I2C_MBMON_SDA 0x00000002 // I2C SDA Status
252 #define I2C_MBMON_SCL 0x00000001 // I2C SCL Status
253 
254 //*****************************************************************************
255 //
256 // The following are defines for the bit fields in the I2C_O_MBLEN register.
257 //
258 //*****************************************************************************
259 #define I2C_MBLEN_CNTL_M 0x000000FF // I2C Burst Length
260 #define I2C_MBLEN_CNTL_S 0
261 
262 //*****************************************************************************
263 //
264 // The following are defines for the bit fields in the I2C_O_MBCNT register.
265 //
266 //*****************************************************************************
267 #define I2C_MBCNT_CNTL_M 0x000000FF // I2C Master Burst Count
268 #define I2C_MBCNT_CNTL_S 0
269 
270 //*****************************************************************************
271 //
272 // The following are defines for the bit fields in the I2C_O_SOAR register.
273 //
274 //*****************************************************************************
275 #define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address
276 #define I2C_SOAR_OAR_S 0
277 
278 //*****************************************************************************
279 //
280 // The following are defines for the bit fields in the I2C_O_SCSR register.
281 //
282 //*****************************************************************************
283 #define I2C_SCSR_ACTDMARX 0x80000000 // DMA RX Active Status
284 #define I2C_SCSR_ACTDMATX 0x40000000 // DMA TX Active Status
285 #define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write
286 #define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status
287 #define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched
288 #define I2C_SCSR_FBR 0x00000004 // First Byte Received
289 #define I2C_SCSR_RXFIFO 0x00000004 // RX FIFO Enable
290 #define I2C_SCSR_TXFIFO 0x00000002 // TX FIFO Enable
291 #define I2C_SCSR_TREQ 0x00000002 // Transmit Request
292 #define I2C_SCSR_DA 0x00000001 // Device Active
293 #define I2C_SCSR_RREQ 0x00000001 // Receive Request
294 
295 //*****************************************************************************
296 //
297 // The following are defines for the bit fields in the I2C_O_SDR register.
298 //
299 //*****************************************************************************
300 #define I2C_SDR_DATA_M 0x000000FF // Data for Transfer
301 #define I2C_SDR_DATA_S 0
302 
303 //*****************************************************************************
304 //
305 // The following are defines for the bit fields in the I2C_O_SIMR register.
306 //
307 //*****************************************************************************
308 #define I2C_SIMR_RXFFIM 0x00000100 // Receive FIFO Full Interrupt Mask
309 #define I2C_SIMR_TXFEIM 0x00000080 // Transmit FIFO Empty Interrupt
310  // Mask
311 #define I2C_SIMR_RXIM 0x00000040 // Receive FIFO Request Interrupt
312  // Mask
313 #define I2C_SIMR_TXIM 0x00000020 // Transmit FIFO Request Interrupt
314  // Mask
315 #define I2C_SIMR_DMATXIM 0x00000010 // Transmit DMA Interrupt Mask
316 #define I2C_SIMR_DMARXIM 0x00000008 // Receive DMA Interrupt Mask
317 #define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask
318 #define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask
319 #define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask
320 
321 //*****************************************************************************
322 //
323 // The following are defines for the bit fields in the I2C_O_SRIS register.
324 //
325 //*****************************************************************************
326 #define I2C_SRIS_RXFFRIS 0x00000100 // Receive FIFO Full Raw Interrupt
327  // Status
328 #define I2C_SRIS_TXFERIS 0x00000080 // Transmit FIFO Empty Raw
329  // Interrupt Status
330 #define I2C_SRIS_RXRIS 0x00000040 // Receive FIFO Request Raw
331  // Interrupt Status
332 #define I2C_SRIS_TXRIS 0x00000020 // Transmit Request Raw Interrupt
333  // Status
334 #define I2C_SRIS_DMATXRIS 0x00000010 // Transmit DMA Raw Interrupt
335  // Status
336 #define I2C_SRIS_DMARXRIS 0x00000008 // Receive DMA Raw Interrupt Status
337 #define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt
338  // Status
339 #define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt
340  // Status
341 #define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status
342 
343 //*****************************************************************************
344 //
345 // The following are defines for the bit fields in the I2C_O_SMIS register.
346 //
347 //*****************************************************************************
348 #define I2C_SMIS_RXFFMIS 0x00000100 // Receive FIFO Full Interrupt Mask
349 #define I2C_SMIS_TXFEMIS 0x00000080 // Transmit FIFO Empty Interrupt
350  // Mask
351 #define I2C_SMIS_RXMIS 0x00000040 // Receive FIFO Request Interrupt
352  // Mask
353 #define I2C_SMIS_TXMIS 0x00000020 // Transmit FIFO Request Interrupt
354  // Mask
355 #define I2C_SMIS_DMATXMIS 0x00000010 // Transmit DMA Masked Interrupt
356  // Status
357 #define I2C_SMIS_DMARXMIS 0x00000008 // Receive DMA Masked Interrupt
358  // Status
359 #define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt
360  // Status
361 #define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt
362  // Status
363 #define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status
364 
365 //*****************************************************************************
366 //
367 // The following are defines for the bit fields in the I2C_O_SICR register.
368 //
369 //*****************************************************************************
370 #define I2C_SICR_RXFFIC 0x00000100 // Receive FIFO Full Interrupt Mask
371 #define I2C_SICR_TXFEIC 0x00000080 // Transmit FIFO Empty Interrupt
372  // Mask
373 #define I2C_SICR_RXIC 0x00000040 // Receive Request Interrupt Mask
374 #define I2C_SICR_TXIC 0x00000020 // Transmit Request Interrupt Mask
375 #define I2C_SICR_DMATXIC 0x00000010 // Transmit DMA Interrupt Clear
376 #define I2C_SICR_DMARXIC 0x00000008 // Receive DMA Interrupt Clear
377 #define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear
378 #define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear
379 #define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear
380 
381 //*****************************************************************************
382 //
383 // The following are defines for the bit fields in the I2C_O_SOAR2 register.
384 //
385 //*****************************************************************************
386 #define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable
387 #define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2
388 #define I2C_SOAR2_OAR2_S 0
389 
390 //*****************************************************************************
391 //
392 // The following are defines for the bit fields in the I2C_O_SACKCTL register.
393 //
394 //*****************************************************************************
395 #define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value
396 #define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable
397 
398 //*****************************************************************************
399 //
400 // The following are defines for the bit fields in the I2C_O_FIFODATA register.
401 //
402 //*****************************************************************************
403 #define I2C_FIFODATA_DATA_M 0x000000FF // I2C TX FIFO Write Data Byte
404 #define I2C_FIFODATA_DATA_S 0
405 
406 //*****************************************************************************
407 //
408 // The following are defines for the bit fields in the I2C_O_FIFOCTL register.
409 //
410 //*****************************************************************************
411 #define I2C_FIFOCTL_RXASGNMT 0x80000000 // RX Control Assignment
412 #define I2C_FIFOCTL_RXFLUSH 0x40000000 // RX FIFO Flush
413 #define I2C_FIFOCTL_DMARXENA 0x20000000 // DMA RX Channel Enable
414 #define I2C_FIFOCTL_RXTRIG_M 0x00070000 // RX FIFO Trigger
415 #define I2C_FIFOCTL_TXASGNMT 0x00008000 // TX Control Assignment
416 #define I2C_FIFOCTL_TXFLUSH 0x00004000 // TX FIFO Flush
417 #define I2C_FIFOCTL_DMATXENA 0x00002000 // DMA TX Channel Enable
418 #define I2C_FIFOCTL_TXTRIG_M 0x00000007 // TX FIFO Trigger
419 #define I2C_FIFOCTL_RXTRIG_S 16
420 #define I2C_FIFOCTL_TXTRIG_S 0
421 
422 //*****************************************************************************
423 //
424 // The following are defines for the bit fields in the I2C_O_FIFOSTATUS
425 // register.
426 //
427 //*****************************************************************************
428 #define I2C_FIFOSTATUS_RXABVTRIG \
429  0x00040000 // RX FIFO Above Trigger Level
430 #define I2C_FIFOSTATUS_RXFF 0x00020000 // RX FIFO Full
431 #define I2C_FIFOSTATUS_RXFE 0x00010000 // RX FIFO Empty
432 #define I2C_FIFOSTATUS_TXBLWTRIG \
433  0x00000004 // TX FIFO Below Trigger Level
434 #define I2C_FIFOSTATUS_TXFF 0x00000002 // TX FIFO Full
435 #define I2C_FIFOSTATUS_TXFE 0x00000001 // TX FIFO Empty
436 
437 //*****************************************************************************
438 //
439 // The following are defines for the bit fields in the I2C_O_PP register.
440 //
441 //*****************************************************************************
442 #define I2C_PP_HS 0x00000001 // High-Speed Capable
443 
444 //*****************************************************************************
445 //
446 // The following are defines for the bit fields in the I2C_O_PC register.
447 //
448 //*****************************************************************************
449 #define I2C_PC_HS 0x00000001 // High-Speed Capable
450 
451 #endif // __HW_I2C_H__
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