32 #ifndef __SYSCTL_A_H__ 
   33 #define __SYSCTL_A_H__ 
   37 #include <ti/devices/msp432p4xx/inc/msp.h> 
   41 #ifdef __MCU_HAS_SYSCTL_A__ 
   66 #define SYSCTL_A_HARD_RESET 1 
   67 #define SYSCTL_A_SOFT_RESET 0 
   69 #define SYSCTL_A_PERIPH_LCD SYSCTL_A_PERIHALT_CTL_HALT_LCD 
   70 #define SYSCTL_A_PERIPH_DMA SYSCTL_A_PERIHALT_CTL_HALT_DMA 
   71 #define SYSCTL_A_PERIPH_WDT SYSCTL_A_PERIHALT_CTL_HALT_WDT 
   72 #define SYSCTL_A_PERIPH_ADC SYSCTL_A_PERIHALT_CTL_HALT_ADC 
   73 #define SYSCTL_A_PERIPH_EUSCIB3 SYSCTL_A_PERIHALT_CTL_HALT_EUB3 
   74 #define SYSCTL_A_PERIPH_EUSCIB2 SYSCTL_A_PERIHALT_CTL_HALT_EUB2 
   75 #define SYSCTL_A_PERIPH_EUSCIB1 SYSCTL_A_PERIHALT_CTL_HALT_EUB1 
   76 #define SYSCTL_A_PERIPH_EUSCIB0 SYSCTL_A_PERIHALT_CTL_HALT_EUB0 
   77 #define SYSCTL_A_PERIPH_EUSCIA3 SYSCTL_A_PERIHALT_CTL_HALT_EUA3 
   78 #define SYSCTL_A_PERIPH_EUSCIA2 SYSCTL_A_PERIHALT_CTL_HALT_EUA2 
   79 #define SYSCTL_A_PERIPH_EUSCIA1 SYSCTL_A_PERIHALT_CTL_HALT_EUA1 
   80 #define SYSCTL_A_PERIPH_EUSCIA0 SYSCTL_A_PERIHALT_CTL_HALT_EUA0 
   81 #define SYSCTL_A_PERIPH_TIMER32_0_MODULE SYSCTL_A_PERIHALT_CTL_HALT_T32_0 
   82 #define SYSCTL_A_PERIPH_TIMER16_3 SYSCTL_A_PERIHALT_CTL_HALT_T16_3 
   83 #define SYSCTL_A_PERIPH_TIMER16_2 SYSCTL_A_PERIHALT_CTL_HALT_T16_2 
   84 #define SYSCTL_A_PERIPH_TIMER16_1 SYSCTL_A_PERIHALT_CTL_HALT_T16_1 
   85 #define SYSCTL_A_PERIPH_TIMER16_0 SYSCTL_A_PERIHALT_CTL_HALT_T16_0 
   87 #define SYSCTL_A_NMIPIN_SRC SYSCTL_A_NMI_CTLSTAT_PIN_SRC 
   88 #define SYSCTL_A_PCM_SRC SYSCTL_A_NMI_CTLSTAT_PCM_SRC 
   89 #define SYSCTL_A_PSS_SRC SYSCTL_A_NMI_CTLSTAT_PSS_SRC 
   90 #define SYSCTL_A_CS_SRC SYSCTL_A_NMI_CTLSTAT_CS_SRC 
   92 #define SYSCTL_A_REBOOT_KEY   0x6900 
   94 #define SYSCTL_A_1_2V_REF        (uint32_t)&TLV->ADC14_REF1P2V_TS30C - (uint32_t)TLV_BASE 
   95 #define SYSCTL_A_1_45V_REF       (uint32_t)&TLV->ADC14_REF1P45V_TS30C - (uint32_t)TLV_BASE 
   96 #define SYSCTL_A_2_5V_REF        (uint32_t)&TLV->ADC14_REF2P5V_TS30C - (uint32_t)TLV_BASE 
   98 #define SYSCTL_A_85_DEGREES_C    4 
   99 #define SYSCTL_A_30_DEGREES_C    0 
  101 #define SYSCTL_A_BANKMASK       0x80000000 
  102 #define SRAMCTL_CTL0_BANK       0x10000000 
  103 #define SRAMCTL_CTL1_BANK       0x20000000 
  104 #define SRAMCTL_CTL2_BANK       0x30000000 
  105 #define SRAMCTL_CTL3_BANK       0x40000000 
  108 #define TLV_START               0x00201004 
  109 #define TLV_TAG_RESERVED1      1 
  110 #define TLV_TAG_RESERVED2      2 
  112 #define TLV_TAG_FLASHCTL       4 
  113 #define TLV_TAG_ADC14          5 
  114 #define TLV_TAG_RESERVED6      6 
  115 #define TLV_TAG_RESERVED7      7 
  116 #define TLV_TAG_REF            8 
  117 #define TLV_TAG_RESERVED9      9 
  118 #define TLV_TAG_RESERVED10     10 
  119 #define TLV_TAG_DEVINFO        11 
  120 #define TLV_TAG_DIEREC         12 
  121 #define TLV_TAG_RANDNUM        13 
  122 #define TLV_TAG_RESERVED14     14 
  123 #define TLV_TAG_BSL            15 
  124 #define TLV_TAGEND             0x0BD0E11D 
  251         uint_fast8_t *length, uint32_t **data_address);
 
  540         uint32_t temperature);
 
  560 #endif // __SYSCTL_A_H__ 
bool SysCtl_A_disableSRAM(uint32_t addr)
Definition: sysctl_a.c:203
uint32_t rDCOER_FCAL_RSEL5
Definition: sysctl_a.h:148
void SysCtl_A_disableNMISource(uint_fast8_t flags)
Definition: sysctl_a.c:108
void SysCtl_A_setWDTTimeoutResetType(uint_fast8_t resetType)
Definition: sysctl_a.c:141
uint32_t rDCOER_MAXPOSTUNE_RSEL5
Definition: sysctl_a.h:151
uint_fast16_t SysCtl_A_getTempCalibrationConstant(uint32_t refVoltage, uint32_t temperature)
Definition: sysctl_a.c:167
uint_fast8_t SysCtl_A_getNMISourceStatus(void)
Definition: sysctl_a.c:118
void SysCtl_A_disablePeripheralAtCPUHalt(uint_fast16_t devices)
Definition: sysctl_a.c:136
uint_least32_t SysCtl_A_getInfoFlashSize(void)
Definition: sysctl_a.c:103
void SysCtl_A_rebootDevice(void)
Definition: sysctl_a.c:126
uint32_t rDCOER_CONSTK_RSEL04
Definition: sysctl_a.h:153
uint32_t rDCOIR_FCAL_RSEL5
Definition: sysctl_a.h:140
bool SysCtl_A_disableSRAMRetention(uint32_t startAddr, uint32_t endAddr)
Definition: sysctl_a.c:323
uint32_t rDCOIR_CONSTK_RSEL5
Definition: sysctl_a.h:146
uint32_t rDCOIR_MAXNEGTUNE_RSEL04
Definition: sysctl_a.h:142
void SysCtl_A_disableGlitchFilter(void)
Definition: sysctl_a.c:162
Definition: sysctl_a.h:137
void SysCtl_A_getTLVInfo(uint_fast8_t tag, uint_fast8_t instance, uint_fast8_t *length, uint32_t **data_address)
Definition: sysctl_a.c:44
bool SysCtl_A_enableSRAMRetention(uint32_t startAddr, uint32_t endAddr)
Definition: sysctl_a.c:233
uint_least32_t SysCtl_A_getSRAMSize(void)
Definition: sysctl_a.c:93
uint32_t rDCOER_MAXNEGTUNE_RSEL04
Definition: sysctl_a.h:150
Definition: sysctl_a.h:131
uint32_t rDCOIR_CONSTK_RSEL04
Definition: sysctl_a.h:145
void SysCtl_A_enableGlitchFilter(void)
Definition: sysctl_a.c:157
void SysCtl_A_setWDTPasswordViolationResetType(uint_fast8_t resetType)
Definition: sysctl_a.c:149
uint32_t rDCOIR_FCAL_RSEL04
Definition: sysctl_a.h:139
uint32_t maxErasePulses
Definition: sysctl_a.h:134
uint32_t rDCOIR_MAXPOSTUNE_RSEL04
Definition: sysctl_a.h:141
uint32_t rDCOER_FCAL_RSEL04
Definition: sysctl_a.h:147
uint32_t rDCOIR_MAXNEGTUNE_RSEL5
Definition: sysctl_a.h:144
uint32_t rDCOER_MAXNEGTUNE_RSEL5
Definition: sysctl_a.h:152
void SysCtl_A_enablePeripheralAtCPUHalt(uint_fast16_t devices)
Definition: sysctl_a.c:131
uint32_t rDCOER_MAXPOSTUNE_RSEL04
Definition: sysctl_a.h:149
uint32_t rDCOER_CONSTK_RSEL5
Definition: sysctl_a.h:154
uint_least32_t SysCtl_A_getFlashSize(void)
Definition: sysctl_a.c:98
uint32_t rDCOIR_MAXPOSTUNE_RSEL5
Definition: sysctl_a.h:143
uint32_t maxProgramPulses
Definition: sysctl_a.h:133
bool SysCtl_A_enableSRAM(uint32_t addr)
Definition: sysctl_a.c:173
void SysCtl_A_enableNMISource(uint_fast8_t flags)
Definition: sysctl_a.c:113