CaptureMSP432_HWAttrs 'capturePort'

PIN 2.0, TimerA0.
#define	CaptureMSP432_P2_0_TA0

PIN 2.0, TimerA1.
#define	CaptureMSP432_P2_0_TA1

PIN 2.1, TimerA0.
#define	CaptureMSP432_P2_1_TA0

PIN 2.1, TimerA1.
#define	CaptureMSP432_P2_1_TA1

PIN 2.2, TimerA0.
#define	CaptureMSP432_P2_2_TA0

PIN 2.2, TimerA1.
#define	CaptureMSP432_P2_2_TA1

PIN 2.3, TimerA0.
#define	CaptureMSP432_P2_3_TA0

PIN 2.3, TimerA1.
#define	CaptureMSP432_P2_3_TA1

PIN 2.4, TimerA0.
#define	CaptureMSP432_P2_4_TA0

PIN 2.4, TimerA1.
#define	CaptureMSP432_P2_4_TA1

PIN 2.5, TimerA0.
#define	CaptureMSP432_P2_5_TA0

PIN 2.5, TimerA1.
#define	CaptureMSP432_P2_5_TA1

PIN 2.6, TimerA0.
#define	CaptureMSP432_P2_6_TA0

PIN 2.6, TimerA1.
#define	CaptureMSP432_P2_6_TA1

PIN 2.7, TimerA0.
#define	CaptureMSP432_P2_7_TA0

PIN 2.7, TimerA1.
#define	CaptureMSP432_P2_7_TA1

PIN 3.0, TimerA0.
#define	CaptureMSP432_P3_0_TA0

PIN 3.0, TimerA1.
#define	CaptureMSP432_P3_0_TA1

PIN 3.1, TimerA0.
#define	CaptureMSP432_P3_1_TA0

PIN 3.1, TimerA1.
#define	CaptureMSP432_P3_1_TA1

PIN 3.2, TimerA0.
#define	CaptureMSP432_P3_2_TA0

PIN 3.2, TimerA1.
#define	CaptureMSP432_P3_2_TA1

PIN 3.3, TimerA0.
#define	CaptureMSP432_P3_3_TA0

PIN 3.3, TimerA1.
#define	CaptureMSP432_P3_3_TA1

PIN 3.4, TimerA0.
#define	CaptureMSP432_P3_4_TA0

PIN 3.4, TimerA1.
#define	CaptureMSP432_P3_4_TA1

PIN 3.5, TimerA0.
#define	CaptureMSP432_P3_5_TA0

PIN 3.5, TimerA1.
#define	CaptureMSP432_P3_5_TA1

PIN 3.6, TimerA0.
#define	CaptureMSP432_P3_6_TA0

PIN 3.6, TimerA1.
#define	CaptureMSP432_P3_6_TA1

PIN 3.7, TimerA0.
#define	CaptureMSP432_P3_7_TA0

PIN 3.7, TimerA1.
#define	CaptureMSP432_P3_7_TA1

PIN 5.6, TimerA2.
#define	CaptureMSP432_P5_6_TA2

PIN 5.7, TimerA2.
#define	CaptureMSP432_P5_7_TA2

PIN 6.6, TimerA2.
#define	CaptureMSP432_P6_6_TA2

PIN 6.7, TimerA2.
#define	CaptureMSP432_P6_7_TA2

PIN 7.0, TimerA0.
#define	CaptureMSP432_P7_0_TA0

PIN 7.0, TimerA1.
#define	CaptureMSP432_P7_0_TA1

PIN 7.1, TimerA0.
#define	CaptureMSP432_P7_1_TA0

PIN 7.1, TimerA1.
#define	CaptureMSP432_P7_1_TA1

PIN 7.3,7TimerA0.
#define	CaptureMSP432_P7_2_TA0

PIN 7.3,7TimerA1.
#define	CaptureMSP432_P7_2_TA1

PIN 7.3, TimerA0.
#define	CaptureMSP432_P7_3_TA0

PIN 7.3, TimerA1.
#define	CaptureMSP432_P7_3_TA1

PIN 7.4, TimerA0.
#define	CaptureMSP432_P7_4_TA0

PIN 7.4, TimerA1.
#define	CaptureMSP432_P7_4_TA1

PIN 7.5, TimerA0.
#define	CaptureMSP432_P7_5_TA0

PIN 7.5, TimerA1.
#define	CaptureMSP432_P7_5_TA1

PIN 7.6, TimerA0.
#define	CaptureMSP432_P7_6_TA0

PIN 7.6, TimerA1.
#define	CaptureMSP432_P7_6_TA1

PIN 7.7, TimerA0.
#define	CaptureMSP432_P7_7_TA0

PIN 7.7, TimerA1.
#define	CaptureMSP432_P7_7_TA1

PIN 8.0, TimerA1.
#define	CaptureMSP432_P8_0_TA1

PIN 8.1, TimerA2.
#define	CaptureMSP432_P8_1_TA2

PIN 8.3,7TimerA3.
#define	CaptureMSP432_P8_2_TA3

PIN 9.3,7TimerA3.
#define	CaptureMSP432_P9_2_TA3

PIN 9.3, TimerA3.
#define	CaptureMSP432_P9_3_TA3

PIN 10.4, TimerA3.
#define	CaptureMSP432_P10_4_TA3

PIN 10.5, TimerA3.
#define	CaptureMSP432_P10_5_TA3

Detailed Description

field options.

Macro Definition Documentation

CaptureMSP432_P2_0_TA0

#define CaptureMSP432_P2_0_TA0

Value:

((PMAP_TA0CCR1A << CAPTUREMSP432_PMAP_OFS) | 0x20 | \
       (INT_TA0_N << CAPTUREMSP432_INT_OFS) | \
       (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P2_0_TA1

#define CaptureMSP432_P2_0_TA1

Value:

((PMAP_TA1CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x20 | (INT_TA1_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P2_1_TA0

#define CaptureMSP432_P2_1_TA0

Value:

((PMAP_TA0CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x21 | (INT_TA0_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P2_1_TA1

#define CaptureMSP432_P2_1_TA1

Value:

((PMAP_TA1CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x21 | (INT_TA2_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P2_2_TA0

#define CaptureMSP432_P2_2_TA0

Value:

((PMAP_TA0CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x22 | (INT_TA0_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P2_2_TA1

#define CaptureMSP432_P2_2_TA1

Value:

((PMAP_TA1CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x22 | (INT_TA1_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P2_3_TA0

#define CaptureMSP432_P2_3_TA0

Value:

((PMAP_TA0CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x23 | (INT_TA0_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P2_3_TA1

#define CaptureMSP432_P2_3_TA1

Value:

((PMAP_TA1CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x23 | (INT_TA1_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P2_4_TA0

#define CaptureMSP432_P2_4_TA0

Value:

((PMAP_TA0CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x24 | (INT_TA0_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P2_4_TA1

#define CaptureMSP432_P2_4_TA1

Value:

((PMAP_TA1CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x24 | (INT_TA1_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P2_5_TA0

#define CaptureMSP432_P2_5_TA0

Value:

((PMAP_TA0CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x25 | (INT_TA0_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P2_5_TA1

#define CaptureMSP432_P2_5_TA1

Value:

((PMAP_TA1CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x25 | (INT_TA1_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P2_6_TA0

#define CaptureMSP432_P2_6_TA0

Value:

((PMAP_TA0CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x26 | (INT_TA0_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P2_6_TA1

#define CaptureMSP432_P2_6_TA1

Value:

((PMAP_TA1CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x26 | (INT_TA1_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P2_7_TA0

#define CaptureMSP432_P2_7_TA0

Value:

((PMAP_TA0CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x27 | (INT_TA0_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P2_7_TA1

#define CaptureMSP432_P2_7_TA1

Value:

((PMAP_TA1CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x27 | (INT_TA1_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P3_0_TA0

#define CaptureMSP432_P3_0_TA0

Value:

((PMAP_TA0CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x30 | (INT_TA0_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P3_0_TA1

#define CaptureMSP432_P3_0_TA1

Value:

((PMAP_TA1CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x30 | (INT_TA1_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P3_1_TA0

#define CaptureMSP432_P3_1_TA0

Value:

((PMAP_TA0CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x31 | (INT_TA0_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P3_1_TA1

#define CaptureMSP432_P3_1_TA1

Value:

((PMAP_TA1CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x31 | (INT_TA1_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P3_2_TA0

#define CaptureMSP432_P3_2_TA0

Value:

((PMAP_TA0CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x32 | (INT_TA0_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P3_2_TA1

#define CaptureMSP432_P3_2_TA1

Value:

((PMAP_TA1CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x32 | (INT_TA1_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P3_3_TA0

#define CaptureMSP432_P3_3_TA0

Value:

((PMAP_TA0CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x33 | (INT_TA0_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P3_3_TA1

#define CaptureMSP432_P3_3_TA1

Value:

((PMAP_TA1CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x33 | (INT_TA1_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P3_4_TA0

#define CaptureMSP432_P3_4_TA0

Value:

((PMAP_TA0CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x34 | (INT_TA0_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P3_4_TA1

#define CaptureMSP432_P3_4_TA1

Value:

((PMAP_TA1CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x34 | (INT_TA1_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P3_5_TA0

#define CaptureMSP432_P3_5_TA0

Value:

((PMAP_TA0CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x35 | (INT_TA0_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P3_5_TA1

#define CaptureMSP432_P3_5_TA1

Value:

((PMAP_TA1CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x35 | (INT_TA1_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P3_6_TA0

#define CaptureMSP432_P3_6_TA0

Value:

((PMAP_TA0CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x36 | (INT_TA0_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P3_6_TA1

#define CaptureMSP432_P3_6_TA1

Value:

((PMAP_TA1CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x36 | (INT_TA1_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P3_7_TA0

#define CaptureMSP432_P3_7_TA0

Value:

((PMAP_TA0CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x37 | (INT_TA0_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P3_7_TA1

#define CaptureMSP432_P3_7_TA1

Value:

((PMAP_TA1CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x37 | (INT_TA1_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P5_6_TA2

#define CaptureMSP432_P5_6_TA2

Value:

(0x56 | (INT_TA2_N << CAPTUREMSP432_INT_OFS) |  \
        (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P5_7_TA2

#define CaptureMSP432_P5_7_TA2

Value:

(0x57 | (INT_TA2_N << CAPTUREMSP432_INT_OFS) |  \
        (TIMER_A_CAPTURECOMPARE_REGISTER_2 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P6_6_TA2

#define CaptureMSP432_P6_6_TA2

Value:

(0x66 | (INT_TA2_N << CAPTUREMSP432_INT_OFS) |  \
        (TIMER_A_CAPTURECOMPARE_REGISTER_3 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P6_7_TA2

#define CaptureMSP432_P6_7_TA2

Value:

(0x67 | (INT_TA2_N << CAPTUREMSP432_INT_OFS) |  \
        (TIMER_A_CAPTURECOMPARE_REGISTER_4 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P7_0_TA0

#define CaptureMSP432_P7_0_TA0

Value:

((PMAP_TA0CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x70 | (INT_TA0_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P7_0_TA1

#define CaptureMSP432_P7_0_TA1

Value:

((PMAP_TA1CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x70 | (INT_TA1_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P7_1_TA0

#define CaptureMSP432_P7_1_TA0

Value:

((PMAP_TA0CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x71 | (INT_TA0_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P7_1_TA1

#define CaptureMSP432_P7_1_TA1

Value:

((PMAP_TA1CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x71 | (INT_TA1_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P7_2_TA0

#define CaptureMSP432_P7_2_TA0

Value:

((PMAP_TA0CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x72 | (INT_TA0_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P7_2_TA1

#define CaptureMSP432_P7_2_TA1

Value:

((PMAP_TA1CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x72 | (INT_TA1_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P7_3_TA0

#define CaptureMSP432_P7_3_TA0

Value:

((PMAP_TA0CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x73 | (INT_TA0_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P7_3_TA1

#define CaptureMSP432_P7_3_TA1

Value:

((PMAP_TA1CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x73 | (INT_TA1_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P7_4_TA0

#define CaptureMSP432_P7_4_TA0

Value:

((PMAP_TA0CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x74 | (INT_TA0_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P7_4_TA1

#define CaptureMSP432_P7_4_TA1

Value:

((PMAP_TA1CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x74 | (INT_TA1_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P7_5_TA0

#define CaptureMSP432_P7_5_TA0

Value:

((PMAP_TA0CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x75 | (INT_TA0_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P7_5_TA1

#define CaptureMSP432_P7_5_TA1

Value:

((PMAP_TA1CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x75 | (INT_TA1_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P7_6_TA0

#define CaptureMSP432_P7_6_TA0

Value:

((PMAP_TA0CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x76 | (INT_TA0_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P7_6_TA1

#define CaptureMSP432_P7_6_TA1

Value:

((PMAP_TA1CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x76 | (INT_TA1_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P7_7_TA0

#define CaptureMSP432_P7_7_TA0

Value:

((PMAP_TA0CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x77 | (INT_TA0_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P7_7_TA1

#define CaptureMSP432_P7_7_TA1

Value:

((PMAP_TA1CCR1A << CAPTUREMSP432_PMAP_OFS) | \
            0x77 | (INT_TA1_N << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P8_0_TA1

#define CaptureMSP432_P8_0_TA1

Value:

(0x80 | (INT_TA1_0 << CAPTUREMSP432_INT_OFS) |  \
            (TIMER_A_CAPTURECOMPARE_REGISTER_0 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P8_1_TA2

#define CaptureMSP432_P8_1_TA2

Value:

(0x81 | (INT_TA2_0 << CAPTUREMSP432_INT_OFS) |  \
            (TIMER_A_CAPTURECOMPARE_REGISTER_0 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P8_2_TA3

#define CaptureMSP432_P8_2_TA3

Value:

(0x82 | (INT_TA3_N << CAPTUREMSP432_INT_OFS) |  \
            (TIMER_A_CAPTURECOMPARE_REGISTER_2 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P9_2_TA3

#define CaptureMSP432_P9_2_TA3

Value:

(0x92 | (INT_TA3_N << CAPTUREMSP432_INT_OFS) |  \
            (TIMER_A_CAPTURECOMPARE_REGISTER_3 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P9_3_TA3

#define CaptureMSP432_P9_3_TA3

Value:

(0x93 | (INT_TA3_N << CAPTUREMSP432_INT_OFS) |  \
            (TIMER_A_CAPTURECOMPARE_REGISTER_4 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P10_4_TA3

#define CaptureMSP432_P10_4_TA3

Value:

(0xA4 | (INT_TA3_0 << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_0 << CAPTUREMSP432_CCR_OFS))

CaptureMSP432_P10_5_TA3

#define CaptureMSP432_P10_5_TA3

Value:

(0xA5 | (INT_TA3_1 << CAPTUREMSP432_INT_OFS) | \
            (TIMER_A_CAPTURECOMPARE_REGISTER_1 << CAPTUREMSP432_CCR_OFS))