47 #ifndef ti_drivers_power_PowerMSP432__include 48 #define ti_drivers_power_PowerMSP432__include 62 #define PowerMSP432_RESUMETIMESLEEP 32 65 #define PowerMSP432_TOTALTIMESLEEP 40 68 #define PowerMSP432_RESUMETIMEDEEPSLEEP_0 16 71 #define PowerMSP432_TOTALTIMEDEEPSLEEP_0 40 74 #define PowerMSP432_RESUMETIMEDEEPSLEEP_1 16 77 #define PowerMSP432_TOTALTIMEDEEPSLEEP_1 40 80 #define PowerMSP432_PERIPH_ADC14 0 83 #define PowerMSP432_PERIPH_DMA 1 86 #define PowerMSP432_PERIPH_EUSCI_A0 2 89 #define PowerMSP432_PERIPH_EUSCI_A1 3 92 #define PowerMSP432_PERIPH_EUSCI_A2 4 95 #define PowerMSP432_PERIPH_EUSCI_A3 5 98 #define PowerMSP432_PERIPH_EUSCI_B0 6 101 #define PowerMSP432_PERIPH_EUSCI_B1 7 104 #define PowerMSP432_PERIPH_EUSCI_B2 8 107 #define PowerMSP432_PERIPH_EUSCI_B3 9 110 #define PowerMSP432_PERIPH_TIMER_A0 10 113 #define PowerMSP432_PERIPH_TIMER_A1 11 116 #define PowerMSP432_PERIPH_TIMER_A2 12 119 #define PowerMSP432_PERIPH_TIMER_A3 13 122 #define PowerMSP432_PERIPH_TIMER_T32 14 127 #define PowerMSP432_DISALLOW_SLEEP 0 130 #define PowerMSP432_DISALLOW_DEEPSLEEP_0 1 133 #define PowerMSP432_DISALLOW_DEEPSLEEP_1 2 136 #define PowerMSP432_DISALLOW_SHUTDOWN_0 3 139 #define PowerMSP432_DISALLOW_SHUTDOWN_1 4 142 #define PowerMSP432_DISALLOW_PERFLEVEL_0 5 145 #define PowerMSP432_DISALLOW_PERFLEVEL_1 6 148 #define PowerMSP432_DISALLOW_PERFLEVEL_2 7 151 #define PowerMSP432_DISALLOW_PERFLEVEL_3 8 154 #define PowerMSP432_DISALLOW_PERFLEVEL_4 9 157 #define PowerMSP432_DISALLOW_PERFLEVEL_5 10 160 #define PowerMSP432_DISALLOW_PERFLEVEL_6 11 163 #define PowerMSP432_DISALLOW_PERFLEVEL_7 12 166 #define PowerMSP432_DISALLOW_PERF_CHANGES 13 170 #define PowerMSP432_NUMCONSTRAINTS 14 178 #define PowerMSP432_ENTERING_SLEEP 0x1 181 #define PowerMSP432_ENTERING_DEEPSLEEP 0x2 184 #define PowerMSP432_ENTERING_SHUTDOWN 0x4 187 #define PowerMSP432_AWAKE_SLEEP 0x8 190 #define PowerMSP432_AWAKE_DEEPSLEEP 0x10 193 #define PowerMSP432_START_CHANGE_PERF_LEVEL 0x20 196 #define PowerMSP432_DONE_CHANGE_PERF_LEVEL 0x40 200 #define PowerMSP432_NUMEVENTS 7 204 #define PowerMSP432_SLEEP 0x1 205 #define PowerMSP432_DEEPSLEEP_0 0x2 206 #define PowerMSP432_DEEPSLEEP_1 0x4 209 #define PowerMSP432_SHUTDOWN_0 0x0 210 #define PowerMSP432_SHUTDOWN_1 0x1 213 #define CS_DCO_TUNE_FREQ 0x7 695 void (*resumeShutdownHookFxn)(void);
806 uint32_t constraintMask;
808 unsigned int currentPerfLevel;
810 bool perfInitialized;
812 uint8_t constraintCounts[PowerMSP432_NUMCONSTRAINTS];
814 } PowerMSP432_ModuleState;
876 void PowerMSP432_schedulerDisable(
void);
883 void PowerMSP432_schedulerRestore(
void);
886 uint_fast16_t PowerMSP432_getNumPerfLevels(
void);
889 int_fast16_t PowerMSP432_getFreqs(uint_fast16_t level,
898 #define Power_getDependencyCount(resourceId) Power_EINVALIDINPUT 899 #define Power_releaseDependency(resourceId) Power_EINVALIDINPUT 900 #define Power_setDependency(resourceId) Power_EINVALIDINPUT unsigned int SMCLK
The expected SMCLK frequency for this performance level, in Hz.
Definition: PowerMSP432.h:518
bool enablePerf
Boolean specifying if performance scaling is enabled.
Definition: PowerMSP432.h:613
uint32_t numCustom
Number of custom performance levels.
Definition: PowerMSP432.h:705
unsigned int clockSource
The clock source for this performance level.
Definition: PowerMSP432.h:392
Structure holding device frequencies (in Hz)
Definition: PowerMSP432.h:538
void PowerMSP432_sleepPolicy(void)
The SLEEP Power Policy.
unsigned int SELB
The BCLK source.
Definition: PowerMSP432.h:441
unsigned int LFXTDRIVE
The low frequency crystal (LFXT) drive level.
Definition: PowerMSP432.h:736
unsigned int MCLK
Definition: PowerMSP432.h:539
unsigned int DIVA
The ACLK source divider.
Definition: PowerMSP432.h:455
unsigned int HSMCLK
Definition: PowerMSP432.h:540
bool bypassLFXT
Boolean specifying if the LFXT pin should be configured for LFXT bypass.
Definition: PowerMSP432.h:772
void(* Power_PolicyInitFxn)(void)
Power policy initialization function pointer.
Definition: Power.h:402
unsigned int flashWaitStates
The number of Flash wait-states to be used for this performance level.
Definition: PowerMSP432.h:473
bool configurePinHFXT
Boolean specifying if the HFXT pin should be configured for HFXT function.
Definition: PowerMSP432.h:745
unsigned int HSMCLK
The expected HSMCLK frequency for this performance level, in Hz.
Definition: PowerMSP432.h:511
PowerMSP432_PerfLevel * customPerfLevels
Pointer to an optional array of custom performance levels.
Definition: PowerMSP432.h:701
bool enableInterruptsCS
Boolean specifying if interrupts from the Clock System (CS) should be enabled for catching clock and ...
Definition: PowerMSP432.h:788
unsigned int SELM
The MCLK source.
Definition: PowerMSP432.h:406
unsigned int DIVS
The SMCLK source divider.
Definition: PowerMSP432.h:434
unsigned int tuneFreqDCO
The target center frequency for custom tuning of the DCO, in Hz. This frequency value is used only wh...
Definition: PowerMSP432.h:534
void PowerMSP432_initPolicy(void)
The Power Policy initialization function.
unsigned int DCORESEL
The DCO frequency range selection.
Definition: PowerMSP432.h:399
void(* Power_PolicyFxn)(void)
Power policy function pointer.
Definition: Power.h:407
bool useExtendedPerf
Boolean specifying if extended performance scaling features are to be supported.
Definition: PowerMSP432.h:722
Power global configuration (MSP432-specific)
Definition: PowerMSP432.h:547
unsigned int VCORE
The core voltage level.
Definition: PowerMSP432.h:386
bool enableParking
Boolean specifying if pull resistors should be automatically applied to input pins during PowerMSP432...
Definition: PowerMSP432.h:684
unsigned int BCLK
The BCLK frequency for this performance level. Currently only 32768 Hz is supported.
Definition: PowerMSP432.h:523
unsigned int activeState
The active state for the device.
Definition: PowerMSP432.h:369
bool enablePolicy
Boolean specifying if the Power Policy function is enabled.
Definition: PowerMSP432.h:602
unsigned int BCLK
Definition: PowerMSP432.h:542
unsigned int DIVM
The MCLK source divider.
Definition: PowerMSP432.h:413
void PowerMSP432_deepSleepPolicy(void)
The DEEPSLEEP Power Policy.
unsigned int ACLK
The ACLK frequency for this performance level. Currently only 32768 Hz is supported.
Definition: PowerMSP432.h:528
unsigned int DIVHS
The HSMCLK source divider.
Definition: PowerMSP432.h:427
Power_PolicyFxn policyFxn
The Power Policy function.
Definition: PowerMSP432.h:577
unsigned int SELA
The ACLK source.
Definition: PowerMSP432.h:448
unsigned int priorityInterruptsCS
The interrupt priority to be configured for CS interrupts.
Definition: PowerMSP432.h:792
unsigned int SELS
The HSMCLK and SMCLK source.
Definition: PowerMSP432.h:420
unsigned int ACLK
Definition: PowerMSP432.h:543
bool enableFlashBuffer
Boolean specifying if Flash read buffering should be enabled for this performance level...
Definition: PowerMSP432.h:497
unsigned int HFXTFREQ
The high frequency crystal (HFXT) frequency.
Definition: PowerMSP432.h:729
bool configurePinLFXT
Boolean specifying if the LFXT pin should be configured for LFXT function.
Definition: PowerMSP432.h:763
bool bypassHFXT
Boolean specifying if the HFXT pin should be configured for HFXT bypass.
Definition: PowerMSP432.h:754
Power_PolicyInitFxn policyInitFxn
The Power Policy's initialization function.
Definition: PowerMSP432.h:554
unsigned int MCLK
The expected MCLK frequency for this performance level, in Hz.
Definition: PowerMSP432.h:504
Structure defining a performance level.
Definition: PowerMSP432.h:352
unsigned int SMCLK
Definition: PowerMSP432.h:541
unsigned int initialPerfLevel
The initial performance level to be established during Power Manager initialization.
Definition: PowerMSP432.h:589
Linked List interface for use in drivers.