I2CMSP432.h
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1 /*
2  * Copyright (c) 2015-2019, Texas Instruments Incorporated
3  * All rights reserved.
4  *
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31  */
32 /*!****************************************************************************
33  * @file I2CMSP432.h
34  *
35  * @brief I2C driver implementation for the EUSCI controller on MSP432
36  *
37  * This I2C driver implementation is designed to operate on a EUCSI controller
38  * in I2C mode. The I2CMSP432 header file should be included in an application
39  * as follows:
40  * @code
41  * #include <ti/drivers/I2C.h>
42  * #include <ti/drivers/I2CMSP432.h>
43  * @endcode
44  *
45  * Refer to @ref I2C.h for a complete description of APIs & example of use.
46  *
47  * ## Supported Bit Rates ##
48  * - #I2C_100kHz
49  * - #I2C_400kHz
50  * - #I2C_1000kHz
51  *
52  ******************************************************************************
53  */
54 
55 #ifndef ti_drivers_i2c_I2CMSP432__include
56 #define ti_drivers_i2c_I2CMSP432__include
57 
58 #include <stdint.h>
59 #include <stdbool.h>
60 
61 #include <ti/drivers/I2C.h>
62 #include <ti/drivers/dpl/HwiP.h>
63 #include <ti/drivers/dpl/SemaphoreP.h>
64 #include <ti/drivers/Power.h>
65 
66 #ifdef __cplusplus
67 extern "C" {
68 #endif
69 
70 /*
71  * I2C port/pin defines for pin configuration. Ports P2, P3, and P7 are
72  * configurable through the port mapping controller.
73  * Value specifies the pin function and ranges from 0 to 31
74  * pin range: 0 - 7, port range: 0 - 15
75  *
76  *
77  * 15 - 10 9 8 7 - 4 3 - 0
78  * -------------------------------
79  * | VALUE | X | X | PORT | PIN |
80  * -------------------------------
81  *
82  * value = pinConfig >> 10
83  * port = (pinConfig >> 4) & 0xf
84  * pin = pinConfig & 0x7
85  *
86  * pmap = port * 0x8; // 2 -> 0x10, 3 -> 0x18, 7 -> 0x38
87  * portMapReconfigure = PMAP_ENABLE_RECONFIGURATION;
88  *
89  * Code from pmap.c:
90  * //Get write-access to port mapping registers:
91  * PMAP->KEYID = PMAP_KEYID_VAL;
92  *
93  * //Enable/Disable reconfiguration during runtime
94  * PMAP->CTL = (PMAP->CTL & ~PMAP_CTL_PRECFG) | portMapReconfigure;
95  * HWREG8(PMAP_BASE + pin + pmap) = value;
96  *
97  * For non-configurable ports (bits 20 - 12 will be 0).
98  * Bits 8 and 9 hold the module function (PRIMARY, SECONDARY, or
99  * TERTIALRY).
100  *
101  * 9 8 7 - 4 3 - 0
102  * -----------------------------------
103  * | PnSEL1.x | PnSEL0.x | PORT | PIN |
104  * -----------------------------------
105  *
106  * moduleFunction = (pinConfig >> 8) & 0x3
107  * port = (pinConfig >> 4) & 0xf
108  * pin = 1 << (pinConfig & 0xf)
109  *
110  * MAP_GPIO_setAsPeripheralModuleFunctionInputPin(port,
111  * pin, moduleFunction);
112  * or:
113  * MAP_GPIO_setAsPeripheralModuleFunctionOutputPin(port,
114  * pin, moduleFunction);
115  *
116  */
117 
118 #define I2CMSP432_P1_6_UCB0SDA 0x00000116
119 
120 #define I2CMSP432_P1_7_UCB0SCL 0x00000117
121 
123 #define I2CMSP432_P2_0_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x20)
124 
125 #define I2CMSP432_P2_0_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x20)
126 
127 #define I2CMSP432_P2_0_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x20)
128 
129 #define I2CMSP432_P2_0_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x20)
130 
132 #define I2CMSP432_P2_1_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x21)
133 
134 #define I2CMSP432_P2_1_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x21)
135 
136 #define I2CMSP432_P2_1_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x21)
137 
138 #define I2CMSP432_P2_1_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x21)
139 
141 #define I2CMSP432_P2_2_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x22)
142 
143 #define I2CMSP432_P2_2_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x22)
144 
145 #define I2CMSP432_P2_2_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x22)
146 
147 #define I2CMSP432_P2_2_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x22)
148 
150 #define I2CMSP432_P2_3_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x23)
151 
152 #define I2CMSP432_P2_3_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x23)
153 
154 #define I2CMSP432_P2_3_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x23)
155 
156 #define I2CMSP432_P2_3_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x23)
157 
159 #define I2CMSP432_P2_4_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x24)
160 
161 #define I2CMSP432_P2_4_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x24)
162 
163 #define I2CMSP432_P2_4_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x24)
164 
165 #define I2CMSP432_P2_4_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x24)
166 
168 #define I2CMSP432_P2_5_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x25)
169 
170 #define I2CMSP432_P2_5_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x25)
171 
172 #define I2CMSP432_P2_5_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x25)
173 
174 #define I2CMSP432_P2_5_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x25)
175 
177 #define I2CMSP432_P2_6_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x26)
178 
179 #define I2CMSP432_P2_6_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x26)
180 
181 #define I2CMSP432_P2_6_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x26)
182 
183 #define I2CMSP432_P2_6_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x26)
184 
186 #define I2CMSP432_P2_7_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x27)
187 
188 #define I2CMSP432_P2_7_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x27)
189 
190 #define I2CMSP432_P2_7_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x27)
191 
192 #define I2CMSP432_P2_7_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x27)
193 
195 #define I2CMSP432_P3_0_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x30)
196 
197 #define I2CMSP432_P3_0_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x30)
198 
199 #define I2CMSP432_P3_0_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x30)
200 
201 #define I2CMSP432_P3_0_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x30)
202 
204 #define I2CMSP432_P3_1_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x31)
205 
206 #define I2CMSP432_P3_1_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x31)
207 
208 #define I2CMSP432_P3_1_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x31)
209 
210 #define I2CMSP432_P3_1_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x31)
211 
213 #define I2CMSP432_P3_2_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x32)
214 
215 #define I2CMSP432_P3_2_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x32)
216 
217 #define I2CMSP432_P3_2_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x32)
218 
219 #define I2CMSP432_P3_2_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x32)
220 
222 #define I2CMSP432_P3_3_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x33)
223 
224 #define I2CMSP432_P3_3_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x33)
225 
226 #define I2CMSP432_P3_3_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x33)
227 
228 #define I2CMSP432_P3_3_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x33)
229 
231 #define I2CMSP432_P3_4_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x34)
232 
233 #define I2CMSP432_P3_4_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x34)
234 
235 #define I2CMSP432_P3_4_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x34)
236 
237 #define I2CMSP432_P3_4_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x34)
238 
240 #define I2CMSP432_P3_5_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x35)
241 
242 #define I2CMSP432_P3_5_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x35)
243 
244 #define I2CMSP432_P3_5_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x35)
245 
246 #define I2CMSP432_P3_5_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x35)
247 
249 #define I2CMSP432_P3_6_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x36)
250 
251 #define I2CMSP432_P3_6_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x36)
252 
253 #define I2CMSP432_P3_6_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x36)
254 
255 #define I2CMSP432_P3_6_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x36)
256 
258 #define I2CMSP432_P3_7_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x37)
259 
260 #define I2CMSP432_P3_7_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x37)
261 
262 #define I2CMSP432_P3_7_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x37)
263 
264 #define I2CMSP432_P3_7_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x37)
265 
267 #define I2CMSP432_P6_4_UCB1SDA 0x00000164
268 
269 #define I2CMSP432_P6_5_UCB1SCL 0x00000165
270 
271 #define I2CMSP432_P6_6_UCB3SDA 0x00000266
272 
273 #define I2CMSP432_P6_7_UCB3SCL 0x00000267
274 
276 #define I2CMSP432_P7_0_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x70)
277 
278 #define I2CMSP432_P7_0_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x70)
279 
280 #define I2CMSP432_P7_0_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x70)
281 
282 #define I2CMSP432_P7_0_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x70)
283 
285 #define I2CMSP432_P7_1_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x71)
286 
287 #define I2CMSP432_P7_1_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x71)
288 
289 #define I2CMSP432_P7_1_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x71)
290 
291 #define I2CMSP432_P7_1_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x71)
292 
294 #define I2CMSP432_P7_2_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x72)
295 
296 #define I2CMSP432_P7_2_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x72)
297 
298 #define I2CMSP432_P7_2_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x72)
299 
300 #define I2CMSP432_P7_2_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x72)
301 
303 #define I2CMSP432_P7_3_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x73)
304 
305 #define I2CMSP432_P7_3_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x73)
306 
307 #define I2CMSP432_P7_3_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x73)
308 
309 #define I2CMSP432_P7_3_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x73)
310 
312 #define I2CMSP432_P7_4_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x74)
313 
314 #define I2CMSP432_P7_4_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x74)
315 
316 #define I2CMSP432_P7_4_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x74)
317 
318 #define I2CMSP432_P7_4_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x74)
319 
321 #define I2CMSP432_P7_5_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x75)
322 
323 #define I2CMSP432_P7_5_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x75)
324 
325 #define I2CMSP432_P7_5_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x75)
326 
327 #define I2CMSP432_P7_5_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x75)
328 
330 #define I2CMSP432_P7_6_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x76)
331 
332 #define I2CMSP432_P7_6_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x76)
333 
334 #define I2CMSP432_P7_6_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x76)
335 
336 #define I2CMSP432_P7_6_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x76)
337 
339 #define I2CMSP432_P7_7_UCB0SDA ((PMAP_UCB0SDA << 10) | 0x77)
340 
341 #define I2CMSP432_P7_7_UCB0SCL ((PMAP_UCB0SCL << 10) | 0x77)
342 
343 #define I2CMSP432_P7_7_UCB2SDA ((PMAP_UCB2SDA << 10) | 0x77)
344 
345 #define I2CMSP432_P7_7_UCB2SCL ((PMAP_UCB2SCL << 10) | 0x77)
346 
348 #define I2CMSP432_P10_2_UCB3SDA 0x000001A2
349 
350 #define I2CMSP432_P10_3_UCB3SCL 0x000001A3
351 
363 /* Add I2CMSP432_STATUS_* macros here */
364 
377 /* Add I2CMSP432_CMD_* macros here */
378 
381 /* I2C function table pointer */
382 extern const I2C_FxnTable I2CMSP432_fxnTable;
383 
390 typedef enum {
391  I2CMSP432_IDLE_MODE = 0, /* I2C is not performing a transaction */
392  I2CMSP432_WRITE_MODE, /* I2C is currently performing write operations */
393  I2CMSP432_READ_MODE, /* I2C is currently performing read operations */
394  I2CMSP432_TIMEOUT, /* I2C timed-out */
395  I2CMSP432_ERROR = 0xFF /* I2C error has occurred, exit gracefully */
396 } I2CMSP432_Mode;
436 typedef struct {
438  uint32_t baseAddr;
440  uint32_t intNum;
442  uint32_t intPriority;
444  uint8_t clockSource;
446  uint16_t clkPin;
448  uint16_t dataPin;
450 
456 typedef struct {
457  SemaphoreP_Handle mutex; /* Grants exclusive access to I2C */
458  SemaphoreP_Handle transferComplete; /* Notify finished I2C transfer */
459 
460  HwiP_Handle hwiHandle;
461 
462  I2C_Transaction *currentTransaction; /* Ptr to current I2C transaction */
463  I2C_CallbackFxn transferCallbackFxn; /* Callback function pointer */
464 
465  /* I2C transaction pointers for I2C_MODE_CALLBACK */
466  I2C_Transaction *headPtr; /* Head ptr for queued transactions */
467  I2C_Transaction *tailPtr; /* Tail ptr for queued transactions */
468 
469  uint8_t *writeBufIdx; /* Internal inc. writeBuf index */
470  size_t writeCountIdx; /* Internal dec. writeCounter */
471 
472  uint8_t *readBufIdx; /* Internal inc. readBuf index */
473  size_t readCountIdx; /* Internal dec. readCounter */
474 
475  Power_NotifyObj perfChangeNotify;
476  uint32_t perfConstraintMask;
477 
478  volatile I2CMSP432_Mode mode; /* Stores the I2C state */
479  I2C_TransferMode transferMode; /* Blocking or Callback mode */
480  uint32_t bitRate; /* SPI bit rate in Hz */
481  bool isOpen; /* To determine if the SPI is open */
482 } I2CMSP432_Object;
485 #ifdef __cplusplus
486 }
487 #endif
488 
489 #endif /* ti_drivers_i2c_I2CMSP432__include */
uint16_t clkPin
Definition: I2CMSP432.h:446
Power Manager.
const I2C_FxnTable I2CMSP432_fxnTable
I2C_TransferMode
Return behavior of I2C_Transfer() specified in the I2C_Params.
Definition: I2C.h:458
uint32_t intNum
Definition: I2CMSP432.h:440
The definition of an I2C function table that contains the required set of functions to control a spec...
Definition: I2C.h:604
Power notify object structure.
Definition: Power.h:443
uint16_t dataPin
Definition: I2CMSP432.h:448
uint32_t intPriority
Definition: I2CMSP432.h:442
uint8_t clockSource
Definition: I2CMSP432.h:444
void(* I2C_CallbackFxn)(I2C_Handle handle, I2C_Transaction *transaction, bool transferStatus)
The definition of a callback function.
Definition: I2C.h:508
uint32_t baseAddr
Definition: I2CMSP432.h:438
Defines a transaction to be used with I2C_transfer()
Definition: I2C.h:381
I2CMSP432 Hardware attributes.
Definition: I2CMSP432.h:436
Inter-Integrated Circuit (I2C) Driver.
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