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CC27xxDriverLibrary
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#define FPB_O_FP_CTRL 0x00000000U |
#define FPB_O_FP_REMAP 0x00000004U |
#define FPB_O_FP_COMP0 0x00000008U |
#define FPB_O_FP_COMP1 0x0000000CU |
#define FPB_O_FP_COMP2 0x00000010U |
#define FPB_O_FP_COMP3 0x00000014U |
#define FPB_O_FP_COMP4 0x00000018U |
#define FPB_O_FP_COMP5 0x0000001CU |
#define FPB_O_FP_COMP6 0x00000020U |
#define FPB_O_FP_COMP7 0x00000024U |
#define FPB_O_FP_DEVARCH 0x00000FBCU |
#define FPB_O_FP_DEVTYPE 0x00000FCCU |
#define FPB_O_FP_PIDR4 0x00000FD0U |
#define FPB_O_FP_PIDR5 0x00000FD4U |
#define FPB_O_FP_PIDR6 0x00000FD8U |
#define FPB_O_FP_PIDR7 0x00000FDCU |
#define FPB_O_FP_PIDR0 0x00000FE0U |
#define FPB_O_FP_PIDR1 0x00000FE4U |
#define FPB_O_FP_PIDR2 0x00000FE8U |
#define FPB_O_FP_PIDR3 0x00000FECU |
#define FPB_O_FP_CIDR0 0x00000FF0U |
#define FPB_O_FP_CIDR1 0x00000FF4U |
#define FPB_O_FP_CIDR2 0x00000FF8U |
#define FPB_O_FP_CIDR3 0x00000FFCU |
#define FPB_FP_CTRL_REV_W 4U |
#define FPB_FP_CTRL_REV_M 0xF0000000U |
#define FPB_FP_CTRL_REV_S 28U |
#define FPB_FP_CTRL_RES0_W 13U |
#define FPB_FP_CTRL_RES0_M 0x0FFF8000U |
#define FPB_FP_CTRL_RES0_S 15U |
#define FPB_FP_CTRL_NUM_CODE_14_12__W 3U |
#define FPB_FP_CTRL_NUM_CODE_14_12__M 0x00007000U |
#define FPB_FP_CTRL_NUM_CODE_14_12__S 12U |
#define FPB_FP_CTRL_NUM_LIT_W 4U |
#define FPB_FP_CTRL_NUM_LIT_M 0x00000F00U |
#define FPB_FP_CTRL_NUM_LIT_S 8U |
#define FPB_FP_CTRL_NUM_CODE_7_4__W 4U |
#define FPB_FP_CTRL_NUM_CODE_7_4__M 0x000000F0U |
#define FPB_FP_CTRL_NUM_CODE_7_4__S 4U |
#define FPB_FP_CTRL_RES0_1_W 2U |
#define FPB_FP_CTRL_RES0_1_M 0x0000000CU |
#define FPB_FP_CTRL_RES0_1_S 2U |
#define FPB_FP_CTRL_KEY 0x00000002U |
#define FPB_FP_CTRL_KEY_M 0x00000002U |
#define FPB_FP_CTRL_KEY_S 1U |
#define FPB_FP_CTRL_ENABLE 0x00000001U |
#define FPB_FP_CTRL_ENABLE_M 0x00000001U |
#define FPB_FP_CTRL_ENABLE_S 0U |
#define FPB_FP_REMAP_RES0_W 2U |
#define FPB_FP_REMAP_RES0_M 0xC0000000U |
#define FPB_FP_REMAP_RES0_S 30U |
#define FPB_FP_REMAP_RMPSPT 0x20000000U |
#define FPB_FP_REMAP_RMPSPT_M 0x20000000U |
#define FPB_FP_REMAP_RMPSPT_S 29U |
#define FPB_FP_REMAP_REMAP_W 24U |
#define FPB_FP_REMAP_REMAP_M 0x1FFFFFE0U |
#define FPB_FP_REMAP_REMAP_S 5U |
#define FPB_FP_REMAP_RES0_1_W 5U |
#define FPB_FP_REMAP_RES0_1_M 0x0000001FU |
#define FPB_FP_REMAP_RES0_1_S 0U |
#define FPB_FP_COMP0_BPADDR_W 31U |
#define FPB_FP_COMP0_BPADDR_M 0xFFFFFFFEU |
#define FPB_FP_COMP0_BPADDR_S 1U |
#define FPB_FP_COMP0_BE 0x00000001U |
#define FPB_FP_COMP0_BE_M 0x00000001U |
#define FPB_FP_COMP0_BE_S 0U |
#define FPB_FP_COMP1_BPADDR_W 31U |
#define FPB_FP_COMP1_BPADDR_M 0xFFFFFFFEU |
#define FPB_FP_COMP1_BPADDR_S 1U |
#define FPB_FP_COMP1_BE 0x00000001U |
#define FPB_FP_COMP1_BE_M 0x00000001U |
#define FPB_FP_COMP1_BE_S 0U |
#define FPB_FP_COMP2_BPADDR_W 31U |
#define FPB_FP_COMP2_BPADDR_M 0xFFFFFFFEU |
#define FPB_FP_COMP2_BPADDR_S 1U |
#define FPB_FP_COMP2_BE 0x00000001U |
#define FPB_FP_COMP2_BE_M 0x00000001U |
#define FPB_FP_COMP2_BE_S 0U |
#define FPB_FP_COMP3_BPADDR_W 31U |
#define FPB_FP_COMP3_BPADDR_M 0xFFFFFFFEU |
#define FPB_FP_COMP3_BPADDR_S 1U |
#define FPB_FP_COMP3_BE 0x00000001U |
#define FPB_FP_COMP3_BE_M 0x00000001U |
#define FPB_FP_COMP3_BE_S 0U |
#define FPB_FP_COMP4_BPADDR_W 31U |
#define FPB_FP_COMP4_BPADDR_M 0xFFFFFFFEU |
#define FPB_FP_COMP4_BPADDR_S 1U |
#define FPB_FP_COMP4_BE 0x00000001U |
#define FPB_FP_COMP4_BE_M 0x00000001U |
#define FPB_FP_COMP4_BE_S 0U |
#define FPB_FP_COMP5_BPADDR_W 31U |
#define FPB_FP_COMP5_BPADDR_M 0xFFFFFFFEU |
#define FPB_FP_COMP5_BPADDR_S 1U |
#define FPB_FP_COMP5_BE 0x00000001U |
#define FPB_FP_COMP5_BE_M 0x00000001U |
#define FPB_FP_COMP5_BE_S 0U |
#define FPB_FP_COMP6_BPADDR_W 31U |
#define FPB_FP_COMP6_BPADDR_M 0xFFFFFFFEU |
#define FPB_FP_COMP6_BPADDR_S 1U |
#define FPB_FP_COMP6_BE 0x00000001U |
#define FPB_FP_COMP6_BE_M 0x00000001U |
#define FPB_FP_COMP6_BE_S 0U |
#define FPB_FP_COMP7_BPADDR_W 31U |
#define FPB_FP_COMP7_BPADDR_M 0xFFFFFFFEU |
#define FPB_FP_COMP7_BPADDR_S 1U |
#define FPB_FP_COMP7_BE 0x00000001U |
#define FPB_FP_COMP7_BE_M 0x00000001U |
#define FPB_FP_COMP7_BE_S 0U |
#define FPB_FP_DEVARCH_ARCHITECT_W 11U |
#define FPB_FP_DEVARCH_ARCHITECT_M 0xFFE00000U |
#define FPB_FP_DEVARCH_ARCHITECT_S 21U |
#define FPB_FP_DEVARCH_PRESENT 0x00100000U |
#define FPB_FP_DEVARCH_PRESENT_M 0x00100000U |
#define FPB_FP_DEVARCH_PRESENT_S 20U |
#define FPB_FP_DEVARCH_REVISION_W 4U |
#define FPB_FP_DEVARCH_REVISION_M 0x000F0000U |
#define FPB_FP_DEVARCH_REVISION_S 16U |
#define FPB_FP_DEVARCH_ARCHVER_W 4U |
#define FPB_FP_DEVARCH_ARCHVER_M 0x0000F000U |
#define FPB_FP_DEVARCH_ARCHVER_S 12U |
#define FPB_FP_DEVARCH_ARCHPART_W 12U |
#define FPB_FP_DEVARCH_ARCHPART_M 0x00000FFFU |
#define FPB_FP_DEVARCH_ARCHPART_S 0U |
#define FPB_FP_DEVTYPE_RES0_W 24U |
#define FPB_FP_DEVTYPE_RES0_M 0xFFFFFF00U |
#define FPB_FP_DEVTYPE_RES0_S 8U |
#define FPB_FP_DEVTYPE_SUB_W 4U |
#define FPB_FP_DEVTYPE_SUB_M 0x000000F0U |
#define FPB_FP_DEVTYPE_SUB_S 4U |
#define FPB_FP_DEVTYPE_MAJOR_W 4U |
#define FPB_FP_DEVTYPE_MAJOR_M 0x0000000FU |
#define FPB_FP_DEVTYPE_MAJOR_S 0U |
#define FPB_FP_PIDR4_RES0_W 24U |
#define FPB_FP_PIDR4_RES0_M 0xFFFFFF00U |
#define FPB_FP_PIDR4_RES0_S 8U |
#define FPB_FP_PIDR4_SIZE_W 4U |
#define FPB_FP_PIDR4_SIZE_M 0x000000F0U |
#define FPB_FP_PIDR4_SIZE_S 4U |
#define FPB_FP_PIDR4_DES_2_W 4U |
#define FPB_FP_PIDR4_DES_2_M 0x0000000FU |
#define FPB_FP_PIDR4_DES_2_S 0U |
#define FPB_FP_PIDR5_RES0_W 32U |
#define FPB_FP_PIDR5_RES0_M 0xFFFFFFFFU |
#define FPB_FP_PIDR5_RES0_S 0U |
#define FPB_FP_PIDR6_RES0_W 32U |
#define FPB_FP_PIDR6_RES0_M 0xFFFFFFFFU |
#define FPB_FP_PIDR6_RES0_S 0U |
#define FPB_FP_PIDR7_RES0_W 32U |
#define FPB_FP_PIDR7_RES0_M 0xFFFFFFFFU |
#define FPB_FP_PIDR7_RES0_S 0U |
#define FPB_FP_PIDR0_RES0_W 24U |
#define FPB_FP_PIDR0_RES0_M 0xFFFFFF00U |
#define FPB_FP_PIDR0_RES0_S 8U |
#define FPB_FP_PIDR0_PART_0_W 8U |
#define FPB_FP_PIDR0_PART_0_M 0x000000FFU |
#define FPB_FP_PIDR0_PART_0_S 0U |
#define FPB_FP_PIDR1_RES0_W 24U |
#define FPB_FP_PIDR1_RES0_M 0xFFFFFF00U |
#define FPB_FP_PIDR1_RES0_S 8U |
#define FPB_FP_PIDR1_DES_0_W 4U |
#define FPB_FP_PIDR1_DES_0_M 0x000000F0U |
#define FPB_FP_PIDR1_DES_0_S 4U |
#define FPB_FP_PIDR1_PART_1_W 4U |
#define FPB_FP_PIDR1_PART_1_M 0x0000000FU |
#define FPB_FP_PIDR1_PART_1_S 0U |
#define FPB_FP_PIDR2_RES0_W 24U |
#define FPB_FP_PIDR2_RES0_M 0xFFFFFF00U |
#define FPB_FP_PIDR2_RES0_S 8U |
#define FPB_FP_PIDR2_REVISION_W 4U |
#define FPB_FP_PIDR2_REVISION_M 0x000000F0U |
#define FPB_FP_PIDR2_REVISION_S 4U |
#define FPB_FP_PIDR2_JEDEC 0x00000008U |
#define FPB_FP_PIDR2_JEDEC_M 0x00000008U |
#define FPB_FP_PIDR2_JEDEC_S 3U |
#define FPB_FP_PIDR2_DES_1_W 3U |
#define FPB_FP_PIDR2_DES_1_M 0x00000007U |
#define FPB_FP_PIDR2_DES_1_S 0U |
#define FPB_FP_PIDR3_RES0_W 24U |
#define FPB_FP_PIDR3_RES0_M 0xFFFFFF00U |
#define FPB_FP_PIDR3_RES0_S 8U |
#define FPB_FP_PIDR3_REVAND_W 4U |
#define FPB_FP_PIDR3_REVAND_M 0x000000F0U |
#define FPB_FP_PIDR3_REVAND_S 4U |
#define FPB_FP_PIDR3_CMOD_W 4U |
#define FPB_FP_PIDR3_CMOD_M 0x0000000FU |
#define FPB_FP_PIDR3_CMOD_S 0U |
#define FPB_FP_CIDR0_RES0_W 24U |
#define FPB_FP_CIDR0_RES0_M 0xFFFFFF00U |
#define FPB_FP_CIDR0_RES0_S 8U |
#define FPB_FP_CIDR0_PRMBL_0_W 8U |
#define FPB_FP_CIDR0_PRMBL_0_M 0x000000FFU |
#define FPB_FP_CIDR0_PRMBL_0_S 0U |
#define FPB_FP_CIDR1_RES0_W 24U |
#define FPB_FP_CIDR1_RES0_M 0xFFFFFF00U |
#define FPB_FP_CIDR1_RES0_S 8U |
#define FPB_FP_CIDR1_CLASS_W 4U |
#define FPB_FP_CIDR1_CLASS_M 0x000000F0U |
#define FPB_FP_CIDR1_CLASS_S 4U |
#define FPB_FP_CIDR1_PRMBL_1_W 4U |
#define FPB_FP_CIDR1_PRMBL_1_M 0x0000000FU |
#define FPB_FP_CIDR1_PRMBL_1_S 0U |
#define FPB_FP_CIDR2_RES0_W 24U |
#define FPB_FP_CIDR2_RES0_M 0xFFFFFF00U |
#define FPB_FP_CIDR2_RES0_S 8U |
#define FPB_FP_CIDR2_PRMBL_2_W 8U |
#define FPB_FP_CIDR2_PRMBL_2_M 0x000000FFU |
#define FPB_FP_CIDR2_PRMBL_2_S 0U |
#define FPB_FP_CIDR3_RES0_W 24U |
#define FPB_FP_CIDR3_RES0_M 0xFFFFFF00U |
#define FPB_FP_CIDR3_RES0_S 8U |
#define FPB_FP_CIDR3_PRMBL_3_W 8U |
#define FPB_FP_CIDR3_PRMBL_3_M 0x000000FFU |
#define FPB_FP_CIDR3_PRMBL_3_S 0U |