[apu.h] Algorithm Processing Unit (APU)

Collaboration diagram for [apu.h] Algorithm Processing Unit (APU):

Modules
	[apu.h] APU Vector Operations
	[apu.h] APU Matrix Operations
	[apu.h] APU Advanced Operations

Macros
#define	APU_FBA_ENABLE   1
	Enable Forward/Backward Averaging. More...
#define	APU_FBA_DISABLE   0
	Disable Forward/Backward Averaging. More...
#define	APU_MEMORY_INTERLEAVED   1
	Set APU memory in interleaved mode. More...
#define	APU_MEMORY_MIRRORED   0
	Set APU memory in mirrored mode. More...
#define	APU_GET_DATA_MEM_OFFSET(x)   ((uint32_t)x - (uint32_t)VCERAM_DATA0_BASE) >> 3
#define	APU_GET_DATA_MEM_ABS(x)   ((uint32_t)VCERAM_DATA0_BASE + (((uint32_t)x) << 3))

Functions
void	APUWaitOnIrq (void)
	Wait for the APU interrupt. More...
bool	APUOperationDone (void)
	Check if the APU has completed its operation. More...
void	APUWaitOp (void)
	Wait for the APU to start and finish. More...
void	APUSetConfig (uint32_t memConfig)
	Configure the APU. More...
void	APUNop (void)
	APU NOP. More...

Detailed Description

Introduction

The APU - Algorithm Processing Unit - is a generic mathematical acceleration module that is able to operate with single-precision floating point numbers (IEEE 754 format) and is optimized to work with complex numbers. This module is able to deal with vector (and matrix) operations efficiently

Numerical Representation Supported by APU

In this material, a "number" is meant to represent a complex number, or two single precision IEEE 754 floating point numbers. There are two possible representations for complex numbers, cartesian or polar.

• Cartesian Representation: In cartesian representation a complex number is stored as two real numbers, with bits 63:32 being the imaginary part and bits 31:0 the real part.
• Polar Representation: In polar representation, a complex number is stored as two real numbers, where bits 63:32 are the phase (theta) and bits 31:0 the magnitude (r). In both representations, 64 bit numbers can indicate a real number simply by making the upper 32-bits all zero.

  Note

  Most of APU API work with Cartesian respresentation. Therefore, unless clearly stated otherwise in the API function description, the API input/output numbers are assumed to be in Cartesian representation. The APU HW will NOT automatically take care of number representation conversions, it is up to the FW and the user to make sure that the proper conversions are employed before an operation takes place between two complex numbers stored using different representations. In other words, adding two numbers one stored in Cartesian format and the other in Polar format, produces wrong results.

APU Data Memory

Memory Configurations

The data memory can be used by the APU in two different configurations, depending on the application. These configurations are known as "Interleaved Mode" (RAID 0) or "Mirrored Mode" (RAID 1). The APU shall be configured to either of those operation modes.

• Interleaved Mode: In this mode of operation, even word addresses are mapped to Bank 0 and odd word addresses are mapped to Bank 1. A word in this context is a 64-bit word (8 Bytes).
• Mirrored Mode: In this mode of operation, a unified memory map of 1024 words is available for the application. Read addresses towards bank 0 and read addresses towards bank 1 can proceed in parallel. In summary, Mirrored mode reduces the total number of available words to 1024, but gives the application total flexibility around the storage of those elements and allows unrestricted access to two elements in parallel. Interleaved mode offers dual the storage (2048 words) with the limitations of simultaneous reads being restricted to even/odd addresses. Note that for the advanced algorithms are implemented exclusively on Mirrored modes.

Data Memory View

The data memories is seen differently from the CPU system side and from the APU side. Essentially, the CPU will observe the normal 32-bit, byte oriented, memory map, whereas the APU will operate and observe a 64-bit wide word-oriented map. The CPU will operate with a 32-bit global address and then APU will only need a 12 bit local address. This table illustrates the differences in the two views.

|--------------------------------------------------------------------------------------------------------------|
| System Address Scheme                                                          | APU Address Scheme          |
|--------------------------------------|----|----|----|---------|----|---|-------|-----------------------------|
| imag(x)                                             | real(x)                  | x                           |
|--------------------------------------|----|----|----|---------|----|---|-------|-----------------------------|
| 7                                    | 6  | 5  | 4  | 3       | 2  | 1 | 0     | 0                           |
| 15                                   | 14 | 13 | 12 | 11      | 10 | 9 | 8     | 1                           |
|                                      |    |    |    |         |    |   |       | ...                         |
| 8*k+7                                |    |    |    |         |    |   | 8*k   | k                           |
|                                      |    |    |    |         |    |   |       | ...                         |
| 8191                                 |    |    |    |         |    |   | 8194  | 1023                        |
|                                      |    |    |    |         |    |   |       | ...                         |
| 16383                                |    |    |    |         |    |   | 16376 | 2047                        |
|--------------------------------------|----|----|----|---------|----|---|-------|-----------------------------|

Vector/Matrix Storage

Vector Storage

Vector X with length N is stored by N units in APU memory from address start_address to end_address = start_address

• N - 1. Generally, element X[i] (with i = 0 to N-1) is stored at start_address + i in APU memory.

From system address scheme:

Address(real(X[i])) = start_address + i * 8;
Address(imag(X[i])) = start_address + i * 8 + 4;

Matrix Storage

Matrix A[MxN] with M rows and N columns is stored by M*N units in APU memory in the column-major order from start_address to end_address = start_address + M*N - 1. Generally, element A[i,j] (i = 0 to M-1, j = 0 to N-1) is stored at start_addres + j * M + i in APU memory

From system address scheme:

Address(real(A[i,j])) = start_address + (j * M + i) * 8;
Address(imag(A[i,j])) = start_address + (j * M + i) * 8 + 4;

Triangular Matrix Storage

Triangular matrix T[NxN] with N rows and N columns can be stored in an efficient manner by N*(N+1)/2 units in the data memory from address start_address to end_address = start_address + N*(N+1)/2 - 1. A simple way to access these matrices is to create the following LUT in the system CPU: LUT = [0,1,3,6,10,15,21,28,36,45,55,66,78,91,105,120,136,153,171,190,210,231,253,276,300,325,351,378,406,435,465] with LUT[j] (j = 0 to N-1) is basically the order of element T[0,j] in APU memory. Generally, element T[i,j] (i,j = 0 to N-1) is stored at start_address + LUT[j] + i in APU memory.

Note

This equation only holds true for values of i <=j (which is the definition of an upper triangular matrix). Symmetric matrices and hermitian matrices can also be stored in APU memory as upper triangular matrices as described.

From system address scheme:

Address(real(A[i,j])) = start_address + (LUT[j] + i)*8;
Address(imag(A[i,j])) = start_address + (LUT[j] + i)*8 + 4;

API

The API functions can be grouped like this:

APU Control Operations:

• APUWaitOnIrq()
• APUOperationDone()
• APUWaitOp()
• APUSetConfig()
• APUNop()

Vector Operations:

• APUVectorDot()
• APUVectorDotConj()
• APUVectorMult()
• APUVectorSum()
• APUVectorCart2Pol()
• APUVectorPol2Cart()
• APUVectorSort()

Matrix Operations:

• APUMatrixMult()
• APUMatrixMultHerm()
• APUMatrixMultSym()
• APUMatrixSum()
• APUMatrixScalarMult()
• APUMatrixNorm()
• APUMatrixScalarSum()
• APUMatrixScalarSum()

Advanced Operations:

• APUSpSmoothCovMatrix()
• APUJacobiEVD()
• APUGaussJordanElim()
• APUConfigFft()
• APUComputeFft()
• APUComputeIfft()
• APUUnitCircle()

Macro Definition Documentation

APU_FBA_ENABLE

#define APU_FBA_ENABLE   1

Enable Forward/Backward Averaging.

APU_FBA_DISABLE

#define APU_FBA_DISABLE   0

Disable Forward/Backward Averaging.

APU_MEMORY_INTERLEAVED

#define APU_MEMORY_INTERLEAVED   1

Set APU memory in interleaved mode.

Referenced by APUSetConfig().

APU_MEMORY_MIRRORED

#define APU_MEMORY_MIRRORED   0

Set APU memory in mirrored mode.

Referenced by APUSetConfig().

APU_GET_DATA_MEM_OFFSET

#define APU_GET_DATA_MEM_OFFSET

(

x

)

((uint32_t)x - (uint32_t)VCERAM_DATA0_BASE) >> 3

Referenced by APUComputeFft(), APUComputeIfft(), APUConfigFft(), APUGaussJordanElim(), APUJacobiEVD(), APUMatrixMult(), APUMatrixMultHerm(), APUMatrixMultSym(), APUMatrixNorm(), APUMatrixScalarMult(), APUMatrixScalarSum(), APUMatrixSum(), APUSpSmoothCovMatrix(), APUUnitCircle(), APUVectorCart2Pol(), APUVectorDot(), APUVectorDotConj(), APUVectorMult(), APUVectorMultConj(), APUVectorPol2Cart(), APUVectorSort(), and APUVectorSum().

APU_GET_DATA_MEM_ABS

#define APU_GET_DATA_MEM_ABS

(

x

)

((uint32_t)VCERAM_DATA0_BASE + (((uint32_t)x) << 3))

Referenced by APUGaussJordanElim(), and APUJacobiEVD().

Function Documentation

APUWaitOnIrq()

void APUWaitOnIrq

(

void

)

Wait for the APU interrupt.

This function busy-waits until the APU API interrupt is set.

Returns

None

References HWREG, VCE_BASE, VCE_ICLR_API_YES, VCE_O_ICLR, VCE_O_RIS, and VCE_RIS_API_M.

APUOperationDone()

bool APUOperationDone

(

void

)

Check if the APU has completed its operation.

Checks the APU message box to see if it has completed its operation.

Returns

None

References APU_MSGBOX_CMDOK, HWREG, VCE_BASE, and VCE_O_MSGBOX.

Referenced by APUWaitOp().

APUWaitOp()

void APUWaitOp

(

void

)

Wait for the APU to start and finish.

Wait for the APU to both begin and complete its operation.

Returns

None

References APUOperationDone().

APUSetConfig()

void APUSetConfig

(

uint32_t

memConfig

)

Configure the APU.

Enable the APU, initialize it and configure its memory mode.

Parameters

memConfig

is the memory configuration mode, either mirrored or interleaved. Must be one of the following: APU_MEMORY_INTERLEAVED APU_MEMORY_MIRRORED

Returns

None

References APU_API_CONFIG, APU_MEMORY_INTERLEAVED, APU_MEMORY_MIRRORED, HWREG, VCE_BASE, VCE_ENABLE_TOPSM_ONE, VCE_INIT_TOPSM_ONE, VCE_LSECTL_MEMORY_INTERLEAVED, VCE_LSECTL_MEMORY_MIRRORED, VCE_O_API, VCE_O_CMDPAR0, VCE_O_ENABLE, and VCE_O_INIT.

APUNop()

void APUNop

(

void

)

APU NOP.

Configure the APU to do nothing.

Returns

None

References APU_API_NOP, HWREG, VCE_BASE, and VCE_O_API.