Macros
#define	CPU_TPIU_O_SSPSR 0x00000000

#define	CPU_TPIU_O_CSPSR 0x00000004

#define	CPU_TPIU_O_ACPR 0x00000010

#define	CPU_TPIU_O_SPPR 0x000000F0

#define	CPU_TPIU_O_FFSR 0x00000300

#define	CPU_TPIU_O_FFCR 0x00000304

#define	CPU_TPIU_O_FSCR 0x00000308

#define	CPU_TPIU_O_CLAIMMASK 0x00000FA0

#define	CPU_TPIU_O_CLAIMSET 0x00000FA0

#define	CPU_TPIU_O_CLAIMTAG 0x00000FA4

#define	CPU_TPIU_O_CLAIMCLR 0x00000FA4

#define	CPU_TPIU_O_LAR 0x00000FB0

#define	CPU_TPIU_O_DEVID 0x00000FC8

#define	CPU_TPIU_SSPSR_FOUR 0x00000008

#define	CPU_TPIU_SSPSR_FOUR_BITN 3

#define	CPU_TPIU_SSPSR_FOUR_M 0x00000008

#define	CPU_TPIU_SSPSR_FOUR_S 3

#define	CPU_TPIU_SSPSR_THREE 0x00000004

#define	CPU_TPIU_SSPSR_THREE_BITN 2

#define	CPU_TPIU_SSPSR_THREE_M 0x00000004

#define	CPU_TPIU_SSPSR_THREE_S 2

#define	CPU_TPIU_SSPSR_TWO 0x00000002

#define	CPU_TPIU_SSPSR_TWO_BITN 1

#define	CPU_TPIU_SSPSR_TWO_M 0x00000002

#define	CPU_TPIU_SSPSR_TWO_S 1

#define	CPU_TPIU_SSPSR_ONE 0x00000001

#define	CPU_TPIU_SSPSR_ONE_BITN 0

#define	CPU_TPIU_SSPSR_ONE_M 0x00000001

#define	CPU_TPIU_SSPSR_ONE_S 0

#define	CPU_TPIU_CSPSR_FOUR 0x00000008

#define	CPU_TPIU_CSPSR_FOUR_BITN 3

#define	CPU_TPIU_CSPSR_FOUR_M 0x00000008

#define	CPU_TPIU_CSPSR_FOUR_S 3

#define	CPU_TPIU_CSPSR_THREE 0x00000004

#define	CPU_TPIU_CSPSR_THREE_BITN 2

#define	CPU_TPIU_CSPSR_THREE_M 0x00000004

#define	CPU_TPIU_CSPSR_THREE_S 2

#define	CPU_TPIU_CSPSR_TWO 0x00000002

#define	CPU_TPIU_CSPSR_TWO_BITN 1

#define	CPU_TPIU_CSPSR_TWO_M 0x00000002

#define	CPU_TPIU_CSPSR_TWO_S 1

#define	CPU_TPIU_CSPSR_ONE 0x00000001

#define	CPU_TPIU_CSPSR_ONE_BITN 0

#define	CPU_TPIU_CSPSR_ONE_M 0x00000001

#define	CPU_TPIU_CSPSR_ONE_S 0

#define	CPU_TPIU_ACPR_PRESCALER_W 13

#define	CPU_TPIU_ACPR_PRESCALER_M 0x00001FFF

#define	CPU_TPIU_ACPR_PRESCALER_S 0

#define	CPU_TPIU_SPPR_PROTOCOL_W 2

#define	CPU_TPIU_SPPR_PROTOCOL_M 0x00000003

#define	CPU_TPIU_SPPR_PROTOCOL_S 0

#define	CPU_TPIU_SPPR_PROTOCOL_SWO_NRZ 0x00000002

#define	CPU_TPIU_SPPR_PROTOCOL_SWO_MANCHESTER 0x00000001

#define	CPU_TPIU_SPPR_PROTOCOL_TRACEPORT 0x00000000

#define	CPU_TPIU_FFSR_FTNONSTOP 0x00000008

#define	CPU_TPIU_FFSR_FTNONSTOP_BITN 3

#define	CPU_TPIU_FFSR_FTNONSTOP_M 0x00000008

#define	CPU_TPIU_FFSR_FTNONSTOP_S 3

#define	CPU_TPIU_FFCR_TRIGIN 0x00000100

#define	CPU_TPIU_FFCR_TRIGIN_BITN 8

#define	CPU_TPIU_FFCR_TRIGIN_M 0x00000100

#define	CPU_TPIU_FFCR_TRIGIN_S 8

#define	CPU_TPIU_FFCR_ENFCONT 0x00000002

#define	CPU_TPIU_FFCR_ENFCONT_BITN 1

#define	CPU_TPIU_FFCR_ENFCONT_M 0x00000002

#define	CPU_TPIU_FFCR_ENFCONT_S 1

#define	CPU_TPIU_FSCR_FSCR_W 32

#define	CPU_TPIU_FSCR_FSCR_M 0xFFFFFFFF

#define	CPU_TPIU_FSCR_FSCR_S 0

#define	CPU_TPIU_CLAIMMASK_CLAIMMASK_W 32

#define	CPU_TPIU_CLAIMMASK_CLAIMMASK_M 0xFFFFFFFF

#define	CPU_TPIU_CLAIMMASK_CLAIMMASK_S 0

#define	CPU_TPIU_CLAIMSET_CLAIMSET_W 32

#define	CPU_TPIU_CLAIMSET_CLAIMSET_M 0xFFFFFFFF

#define	CPU_TPIU_CLAIMSET_CLAIMSET_S 0

#define	CPU_TPIU_CLAIMTAG_CLAIMTAG_W 32

#define	CPU_TPIU_CLAIMTAG_CLAIMTAG_M 0xFFFFFFFF

#define	CPU_TPIU_CLAIMTAG_CLAIMTAG_S 0

#define	CPU_TPIU_CLAIMCLR_CLAIMCLR_W 32

#define	CPU_TPIU_CLAIMCLR_CLAIMCLR_M 0xFFFFFFFF

#define	CPU_TPIU_CLAIMCLR_CLAIMCLR_S 0

#define	CPU_TPIU_DEVID_NRZ_SWO 0x00000400

#define	CPU_TPIU_DEVID_NRZ_SWO_BITN 11

#define	CPU_TPIU_DEVID_NRZ_SWO_M 0x00000400

#define	CPU_TPIU_DEVID_NRZ_SWO_S 11

#define	CPU_TPIU_DEVID_MANCHESTER_SWO 0x00000200

#define	CPU_TPIU_DEVID_MANCHESTER_SWO_BITN 10

#define	CPU_TPIU_DEVID_MANCHESTER_SWO_M 0x00000200

#define	CPU_TPIU_DEVID_MANCHESTER_SWO_S 10

#define	CPU_TPIU_DEVID_PARALLEL_TRACE 0x00000100

#define	CPU_TPIU_DEVID_PARALLEL_TRACE_BITN 9

#define	CPU_TPIU_DEVID_PARALLEL_TRACE_M 0x00000100

#define	CPU_TPIU_DEVID_PARALLEL_TRACE_S 9

#define	CPU_TPIU_DEVID_FIFO_SIZE_W 2

#define	CPU_TPIU_DEVID_FIFO_SIZE_M 0x000001C0

#define	CPU_TPIU_DEVID_FIFO_SIZE_S 6

#define	CPU_TPIU_DEVID_ASYNC_TRACECLKIN 0x00000020

#define	CPU_TPIU_DEVID_ASYNC_TRACECLKIN_BITN 5

#define	CPU_TPIU_DEVID_ASYNC_TRACECLKIN_M 0x00000020

#define	CPU_TPIU_DEVID_ASYNC_TRACECLKIN_S 5

#define	CPU_TPIU_DEVID_NUM_INPUTS_W 5

#define	CPU_TPIU_DEVID_NUM_INPUTS_M 0x0000001F

#define	CPU_TPIU_DEVID_NUM_INPUTS_S 0

#define	CPU_TPIU_DEVID_NUM_INPUTS_ONE 0x00000000

#define	CPU_TPIU_DEVID_NUM_INPUTS_TWO 0x00000001

Macro Definition Documentation

§ CPU_TPIU_O_SSPSR

#define CPU_TPIU_O_SSPSR 0x00000000

§ CPU_TPIU_O_CSPSR

#define CPU_TPIU_O_CSPSR 0x00000004

§ CPU_TPIU_O_ACPR

#define CPU_TPIU_O_ACPR 0x00000010

§ CPU_TPIU_O_SPPR

#define CPU_TPIU_O_SPPR 0x000000F0

§ CPU_TPIU_O_FFSR

#define CPU_TPIU_O_FFSR 0x00000300

§ CPU_TPIU_O_FFCR

#define CPU_TPIU_O_FFCR 0x00000304

§ CPU_TPIU_O_FSCR

#define CPU_TPIU_O_FSCR 0x00000308

§ CPU_TPIU_O_CLAIMMASK

#define CPU_TPIU_O_CLAIMMASK 0x00000FA0

§ CPU_TPIU_O_CLAIMSET

#define CPU_TPIU_O_CLAIMSET 0x00000FA0

§ CPU_TPIU_O_CLAIMTAG

#define CPU_TPIU_O_CLAIMTAG 0x00000FA4

§ CPU_TPIU_O_CLAIMCLR

#define CPU_TPIU_O_CLAIMCLR 0x00000FA4

§ CPU_TPIU_O_LAR

#define CPU_TPIU_O_LAR 0x00000FB0

§ CPU_TPIU_O_DEVID

#define CPU_TPIU_O_DEVID 0x00000FC8

§ CPU_TPIU_SSPSR_FOUR

#define CPU_TPIU_SSPSR_FOUR 0x00000008

§ CPU_TPIU_SSPSR_FOUR_BITN

#define CPU_TPIU_SSPSR_FOUR_BITN 3

§ CPU_TPIU_SSPSR_FOUR_M

#define CPU_TPIU_SSPSR_FOUR_M 0x00000008

§ CPU_TPIU_SSPSR_FOUR_S

#define CPU_TPIU_SSPSR_FOUR_S 3

§ CPU_TPIU_SSPSR_THREE

#define CPU_TPIU_SSPSR_THREE 0x00000004

§ CPU_TPIU_SSPSR_THREE_BITN

#define CPU_TPIU_SSPSR_THREE_BITN 2

§ CPU_TPIU_SSPSR_THREE_M

#define CPU_TPIU_SSPSR_THREE_M 0x00000004

§ CPU_TPIU_SSPSR_THREE_S

#define CPU_TPIU_SSPSR_THREE_S 2

§ CPU_TPIU_SSPSR_TWO

#define CPU_TPIU_SSPSR_TWO 0x00000002

§ CPU_TPIU_SSPSR_TWO_BITN

#define CPU_TPIU_SSPSR_TWO_BITN 1

§ CPU_TPIU_SSPSR_TWO_M

#define CPU_TPIU_SSPSR_TWO_M 0x00000002

§ CPU_TPIU_SSPSR_TWO_S

#define CPU_TPIU_SSPSR_TWO_S 1

§ CPU_TPIU_SSPSR_ONE

#define CPU_TPIU_SSPSR_ONE 0x00000001

§ CPU_TPIU_SSPSR_ONE_BITN

#define CPU_TPIU_SSPSR_ONE_BITN 0

§ CPU_TPIU_SSPSR_ONE_M

#define CPU_TPIU_SSPSR_ONE_M 0x00000001

§ CPU_TPIU_SSPSR_ONE_S

#define CPU_TPIU_SSPSR_ONE_S 0

§ CPU_TPIU_CSPSR_FOUR

#define CPU_TPIU_CSPSR_FOUR 0x00000008

§ CPU_TPIU_CSPSR_FOUR_BITN

#define CPU_TPIU_CSPSR_FOUR_BITN 3

§ CPU_TPIU_CSPSR_FOUR_M

#define CPU_TPIU_CSPSR_FOUR_M 0x00000008

§ CPU_TPIU_CSPSR_FOUR_S

#define CPU_TPIU_CSPSR_FOUR_S 3

§ CPU_TPIU_CSPSR_THREE

#define CPU_TPIU_CSPSR_THREE 0x00000004

§ CPU_TPIU_CSPSR_THREE_BITN

#define CPU_TPIU_CSPSR_THREE_BITN 2

§ CPU_TPIU_CSPSR_THREE_M

#define CPU_TPIU_CSPSR_THREE_M 0x00000004

§ CPU_TPIU_CSPSR_THREE_S

#define CPU_TPIU_CSPSR_THREE_S 2

§ CPU_TPIU_CSPSR_TWO

#define CPU_TPIU_CSPSR_TWO 0x00000002

§ CPU_TPIU_CSPSR_TWO_BITN

#define CPU_TPIU_CSPSR_TWO_BITN 1

§ CPU_TPIU_CSPSR_TWO_M

#define CPU_TPIU_CSPSR_TWO_M 0x00000002

§ CPU_TPIU_CSPSR_TWO_S

#define CPU_TPIU_CSPSR_TWO_S 1

§ CPU_TPIU_CSPSR_ONE

#define CPU_TPIU_CSPSR_ONE 0x00000001

§ CPU_TPIU_CSPSR_ONE_BITN

#define CPU_TPIU_CSPSR_ONE_BITN 0

§ CPU_TPIU_CSPSR_ONE_M

#define CPU_TPIU_CSPSR_ONE_M 0x00000001

§ CPU_TPIU_CSPSR_ONE_S

#define CPU_TPIU_CSPSR_ONE_S 0

§ CPU_TPIU_ACPR_PRESCALER_W

#define CPU_TPIU_ACPR_PRESCALER_W 13

§ CPU_TPIU_ACPR_PRESCALER_M

#define CPU_TPIU_ACPR_PRESCALER_M 0x00001FFF

§ CPU_TPIU_ACPR_PRESCALER_S

#define CPU_TPIU_ACPR_PRESCALER_S 0

§ CPU_TPIU_SPPR_PROTOCOL_W

#define CPU_TPIU_SPPR_PROTOCOL_W 2

§ CPU_TPIU_SPPR_PROTOCOL_M

#define CPU_TPIU_SPPR_PROTOCOL_M 0x00000003

§ CPU_TPIU_SPPR_PROTOCOL_S

#define CPU_TPIU_SPPR_PROTOCOL_S 0

§ CPU_TPIU_SPPR_PROTOCOL_SWO_NRZ

#define CPU_TPIU_SPPR_PROTOCOL_SWO_NRZ 0x00000002

§ CPU_TPIU_SPPR_PROTOCOL_SWO_MANCHESTER

#define CPU_TPIU_SPPR_PROTOCOL_SWO_MANCHESTER 0x00000001

§ CPU_TPIU_SPPR_PROTOCOL_TRACEPORT

#define CPU_TPIU_SPPR_PROTOCOL_TRACEPORT 0x00000000

§ CPU_TPIU_FFSR_FTNONSTOP

#define CPU_TPIU_FFSR_FTNONSTOP 0x00000008

§ CPU_TPIU_FFSR_FTNONSTOP_BITN

#define CPU_TPIU_FFSR_FTNONSTOP_BITN 3

§ CPU_TPIU_FFSR_FTNONSTOP_M

#define CPU_TPIU_FFSR_FTNONSTOP_M 0x00000008

§ CPU_TPIU_FFSR_FTNONSTOP_S

#define CPU_TPIU_FFSR_FTNONSTOP_S 3

§ CPU_TPIU_FFCR_TRIGIN

#define CPU_TPIU_FFCR_TRIGIN 0x00000100

§ CPU_TPIU_FFCR_TRIGIN_BITN

#define CPU_TPIU_FFCR_TRIGIN_BITN 8

§ CPU_TPIU_FFCR_TRIGIN_M

#define CPU_TPIU_FFCR_TRIGIN_M 0x00000100

§ CPU_TPIU_FFCR_TRIGIN_S

#define CPU_TPIU_FFCR_TRIGIN_S 8

§ CPU_TPIU_FFCR_ENFCONT

#define CPU_TPIU_FFCR_ENFCONT 0x00000002

§ CPU_TPIU_FFCR_ENFCONT_BITN

#define CPU_TPIU_FFCR_ENFCONT_BITN 1

§ CPU_TPIU_FFCR_ENFCONT_M

#define CPU_TPIU_FFCR_ENFCONT_M 0x00000002

§ CPU_TPIU_FFCR_ENFCONT_S

#define CPU_TPIU_FFCR_ENFCONT_S 1

§ CPU_TPIU_FSCR_FSCR_W

#define CPU_TPIU_FSCR_FSCR_W 32

§ CPU_TPIU_FSCR_FSCR_M

#define CPU_TPIU_FSCR_FSCR_M 0xFFFFFFFF

§ CPU_TPIU_FSCR_FSCR_S

#define CPU_TPIU_FSCR_FSCR_S 0

§ CPU_TPIU_CLAIMMASK_CLAIMMASK_W

#define CPU_TPIU_CLAIMMASK_CLAIMMASK_W 32

§ CPU_TPIU_CLAIMMASK_CLAIMMASK_M

#define CPU_TPIU_CLAIMMASK_CLAIMMASK_M 0xFFFFFFFF

§ CPU_TPIU_CLAIMMASK_CLAIMMASK_S

#define CPU_TPIU_CLAIMMASK_CLAIMMASK_S 0

§ CPU_TPIU_CLAIMSET_CLAIMSET_W

#define CPU_TPIU_CLAIMSET_CLAIMSET_W 32

§ CPU_TPIU_CLAIMSET_CLAIMSET_M

#define CPU_TPIU_CLAIMSET_CLAIMSET_M 0xFFFFFFFF

§ CPU_TPIU_CLAIMSET_CLAIMSET_S

#define CPU_TPIU_CLAIMSET_CLAIMSET_S 0

§ CPU_TPIU_CLAIMTAG_CLAIMTAG_W

#define CPU_TPIU_CLAIMTAG_CLAIMTAG_W 32

§ CPU_TPIU_CLAIMTAG_CLAIMTAG_M

#define CPU_TPIU_CLAIMTAG_CLAIMTAG_M 0xFFFFFFFF

§ CPU_TPIU_CLAIMTAG_CLAIMTAG_S

#define CPU_TPIU_CLAIMTAG_CLAIMTAG_S 0

§ CPU_TPIU_CLAIMCLR_CLAIMCLR_W

#define CPU_TPIU_CLAIMCLR_CLAIMCLR_W 32

§ CPU_TPIU_CLAIMCLR_CLAIMCLR_M

#define CPU_TPIU_CLAIMCLR_CLAIMCLR_M 0xFFFFFFFF

§ CPU_TPIU_CLAIMCLR_CLAIMCLR_S

#define CPU_TPIU_CLAIMCLR_CLAIMCLR_S 0

§ CPU_TPIU_DEVID_NRZ_SWO

#define CPU_TPIU_DEVID_NRZ_SWO 0x00000400

§ CPU_TPIU_DEVID_NRZ_SWO_BITN

#define CPU_TPIU_DEVID_NRZ_SWO_BITN 11

§ CPU_TPIU_DEVID_NRZ_SWO_M

#define CPU_TPIU_DEVID_NRZ_SWO_M 0x00000400

§ CPU_TPIU_DEVID_NRZ_SWO_S

#define CPU_TPIU_DEVID_NRZ_SWO_S 11

§ CPU_TPIU_DEVID_MANCHESTER_SWO

#define CPU_TPIU_DEVID_MANCHESTER_SWO 0x00000200

§ CPU_TPIU_DEVID_MANCHESTER_SWO_BITN

#define CPU_TPIU_DEVID_MANCHESTER_SWO_BITN 10

§ CPU_TPIU_DEVID_MANCHESTER_SWO_M

#define CPU_TPIU_DEVID_MANCHESTER_SWO_M 0x00000200

§ CPU_TPIU_DEVID_MANCHESTER_SWO_S

#define CPU_TPIU_DEVID_MANCHESTER_SWO_S 10

§ CPU_TPIU_DEVID_PARALLEL_TRACE

#define CPU_TPIU_DEVID_PARALLEL_TRACE 0x00000100

§ CPU_TPIU_DEVID_PARALLEL_TRACE_BITN

#define CPU_TPIU_DEVID_PARALLEL_TRACE_BITN 9

§ CPU_TPIU_DEVID_PARALLEL_TRACE_M

#define CPU_TPIU_DEVID_PARALLEL_TRACE_M 0x00000100

§ CPU_TPIU_DEVID_PARALLEL_TRACE_S

#define CPU_TPIU_DEVID_PARALLEL_TRACE_S 9

§ CPU_TPIU_DEVID_FIFO_SIZE_W

#define CPU_TPIU_DEVID_FIFO_SIZE_W 2

§ CPU_TPIU_DEVID_FIFO_SIZE_M

#define CPU_TPIU_DEVID_FIFO_SIZE_M 0x000001C0

§ CPU_TPIU_DEVID_FIFO_SIZE_S

#define CPU_TPIU_DEVID_FIFO_SIZE_S 6

§ CPU_TPIU_DEVID_ASYNC_TRACECLKIN

#define CPU_TPIU_DEVID_ASYNC_TRACECLKIN 0x00000020

§ CPU_TPIU_DEVID_ASYNC_TRACECLKIN_BITN

#define CPU_TPIU_DEVID_ASYNC_TRACECLKIN_BITN 5

§ CPU_TPIU_DEVID_ASYNC_TRACECLKIN_M

#define CPU_TPIU_DEVID_ASYNC_TRACECLKIN_M 0x00000020

§ CPU_TPIU_DEVID_ASYNC_TRACECLKIN_S

#define CPU_TPIU_DEVID_ASYNC_TRACECLKIN_S 5

§ CPU_TPIU_DEVID_NUM_INPUTS_W

#define CPU_TPIU_DEVID_NUM_INPUTS_W 5

§ CPU_TPIU_DEVID_NUM_INPUTS_M

#define CPU_TPIU_DEVID_NUM_INPUTS_M 0x0000001F

§ CPU_TPIU_DEVID_NUM_INPUTS_S

#define CPU_TPIU_DEVID_NUM_INPUTS_S 0

§ CPU_TPIU_DEVID_NUM_INPUTS_ONE

#define CPU_TPIU_DEVID_NUM_INPUTS_ONE 0x00000000

§ CPU_TPIU_DEVID_NUM_INPUTS_TWO

#define CPU_TPIU_DEVID_NUM_INPUTS_TWO 0x00000001

Macros