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M_CAN controller v3.2.1 register definitions.
Go to the source code of this file.
| #define MCAN_CREL 0x00000000U |
| #define MCAN_ENDN 0x00000004U |
| #define MCAN_DBTP 0x0000000CU |
| #define MCAN_TEST 0x00000010U |
| #define MCAN_RWD 0x00000014U |
| #define MCAN_CCCR 0x00000018U |
| #define MCAN_NBTP 0x0000001CU |
| #define MCAN_TSCC 0x00000020U |
| #define MCAN_TSCV 0x00000024U |
| #define MCAN_TOCC 0x00000028U |
| #define MCAN_TOCV 0x0000002CU |
| #define MCAN_ECR 0x00000040U |
| #define MCAN_PSR 0x00000044U |
| #define MCAN_TDCR 0x00000048U |
| #define MCAN_IR 0x00000050U |
| #define MCAN_IE 0x00000054U |
| #define MCAN_ILS 0x00000058U |
| #define MCAN_ILE 0x0000005CU |
| #define MCAN_GFC 0x00000080U |
| #define MCAN_SIDFC 0x00000084U |
| #define MCAN_XIDFC 0x00000088U |
| #define MCAN_XIDAM 0x00000090U |
| #define MCAN_HPMS 0x00000094U |
| #define MCAN_NDAT1 0x00000098U |
| #define MCAN_NDAT2 0x0000009CU |
| #define MCAN_RXF0C 0x000000A0U |
| #define MCAN_RXF0S 0x000000A4U |
| #define MCAN_RXF0A 0x000000A8U |
| #define MCAN_RXBC 0x000000ACU |
| #define MCAN_RXF1C 0x000000B0U |
| #define MCAN_RXF1S 0x000000B4U |
| #define MCAN_RXF1A 0x000000B8U |
| #define MCAN_RXESC 0x000000BCU |
| #define MCAN_TXBC 0x000000C0U |
| #define MCAN_TXFQS 0x000000C4U |
| #define MCAN_TXESC 0x000000C8U |
| #define MCAN_TXBRP 0x000000CCU |
| #define MCAN_TXBAR 0x000000D0U |
| #define MCAN_TXBCR 0x000000D4U |
| #define MCAN_TXBTO 0x000000D8U |
| #define MCAN_TXBCF 0x000000DCU |
| #define MCAN_TXBTIE 0x000000E0U |
| #define MCAN_TXBCIE 0x000000E4U |
| #define MCAN_TXEFC 0x000000F0U |
| #define MCAN_TXEFS 0x000000F4U |
| #define MCAN_TXEFA 0x000000F8U |
| #define MCAN_CREL_REL_WIDTH 4U |
| #define MCAN_CREL_REL_MASK 0xF0000000U |
| #define MCAN_CREL_REL_SHIFT 28U |
| #define MCAN_CREL_STEP_WIDTH 4U |
| #define MCAN_CREL_STEP_MASK 0x0F000000U |
| #define MCAN_CREL_STEP_SHIFT 24U |
| #define MCAN_CREL_SUBSTEP_WIDTH 4U |
| #define MCAN_CREL_SUBSTEP_MASK 0x00F00000U |
| #define MCAN_CREL_SUBSTEP_SHIFT 20U |
| #define MCAN_CREL_YEAR_WIDTH 4U |
| #define MCAN_CREL_YEAR_MASK 0x000F0000U |
| #define MCAN_CREL_YEAR_SHIFT 16U |
| #define MCAN_CREL_MON_WIDTH 8U |
| #define MCAN_CREL_MON_MASK 0x0000FF00U |
| #define MCAN_CREL_MON_SHIFT 8U |
| #define MCAN_CREL_DAY_WIDTH 8U |
| #define MCAN_CREL_DAY_MASK 0x000000FFU |
| #define MCAN_CREL_DAY_SHIFT 0U |
| #define MCAN_ENDN_ETV_WIDTH 32U |
| #define MCAN_ENDN_ETV_MASK 0xFFFFFFFFU |
| #define MCAN_ENDN_ETV_SHIFT 0U |
| #define MCAN_ENDN_ETV_VALUE 0x87654321U |
| #define MCAN_DBTP_TDC 0x00800000U |
| #define MCAN_DBTP_TDC_MASK 0x00800000U |
| #define MCAN_DBTP_TDC_SHIFT 23U |
| #define MCAN_DBTP_DBRP_WIDTH 5U |
| #define MCAN_DBTP_DBRP_MASK 0x001F0000U |
| #define MCAN_DBTP_DBRP_SHIFT 16U |
| #define MCAN_DBTP_DTSEG1_WIDTH 5U |
| #define MCAN_DBTP_DTSEG1_MASK 0x00001F00U |
| #define MCAN_DBTP_DTSEG1_SHIFT 8U |
| #define MCAN_DBTP_DTSEG2_WIDTH 4U |
| #define MCAN_DBTP_DTSEG2_MASK 0x000000F0U |
| #define MCAN_DBTP_DTSEG2_SHIFT 4U |
| #define MCAN_DBTP_DSJW_WIDTH 4U |
| #define MCAN_DBTP_DSJW_MASK 0x0000000FU |
| #define MCAN_DBTP_DSJW_SHIFT 0U |
| #define MCAN_TEST_RX 0x00000080U |
| #define MCAN_TEST_RX_MASK 0x00000080U |
| #define MCAN_TEST_RX_SHIFT 7U |
| #define MCAN_TEST_TX_WIDTH 2U |
| #define MCAN_TEST_TX_MASK 0x00000060U |
| #define MCAN_TEST_TX_SHIFT 5U |
| #define MCAN_TEST_LBCK 0x00000010U |
| #define MCAN_TEST_LBCK_MASK 0x00000010U |
| #define MCAN_TEST_LBCK_SHIFT 4U |
| #define MCAN_RWD_WDV_WIDTH 8U |
| #define MCAN_RWD_WDV_MASK 0x0000FF00U |
| #define MCAN_RWD_WDV_SHIFT 8U |
| #define MCAN_RWD_WDC_WIDTH 8U |
| #define MCAN_RWD_WDC_MASK 0x000000FFU |
| #define MCAN_RWD_WDC_SHIFT 0U |
| #define MCAN_CCCR_NISO 0x00008000U |
| #define MCAN_CCCR_NISO_MASK 0x00008000U |
| #define MCAN_CCCR_NISO_SHIFT 15U |
| #define MCAN_CCCR_TXP 0x00004000U |
| #define MCAN_CCCR_TXP_MASK 0x00004000U |
| #define MCAN_CCCR_TXP_SHIFT 14U |
| #define MCAN_CCCR_EFBI 0x00002000U |
| #define MCAN_CCCR_EFBI_MASK 0x00002000U |
| #define MCAN_CCCR_EFBI_SHIFT 13U |
| #define MCAN_CCCR_PXHD 0x00001000U |
| #define MCAN_CCCR_PXHD_MASK 0x00001000U |
| #define MCAN_CCCR_PXHD_SHIFT 12U |
| #define MCAN_CCCR_BRSE 0x00000200U |
| #define MCAN_CCCR_BRSE_MASK 0x00000200U |
| #define MCAN_CCCR_BRSE_SHIFT 9U |
| #define MCAN_CCCR_FDOE 0x00000100U |
| #define MCAN_CCCR_FDOE_MASK 0x00000100U |
| #define MCAN_CCCR_FDOE_SHIFT 8U |
| #define MCAN_CCCR_TEST 0x00000080U |
| #define MCAN_CCCR_TEST_MASK 0x00000080U |
| #define MCAN_CCCR_TEST_SHIFT 7U |
| #define MCAN_CCCR_DAR 0x00000040U |
| #define MCAN_CCCR_DAR_MASK 0x00000040U |
| #define MCAN_CCCR_DAR_SHIFT 6U |
| #define MCAN_CCCR_MON 0x00000020U |
| #define MCAN_CCCR_MON_MASK 0x00000020U |
| #define MCAN_CCCR_MON_SHIFT 5U |
| #define MCAN_CCCR_CSR 0x00000010U |
| #define MCAN_CCCR_CSR_MASK 0x00000010U |
| #define MCAN_CCCR_CSR_SHIFT 4U |
| #define MCAN_CCCR_CSA 0x00000008U |
| #define MCAN_CCCR_CSA_MASK 0x00000008U |
| #define MCAN_CCCR_CSA_SHIFT 3U |
| #define MCAN_CCCR_ASM 0x00000004U |
| #define MCAN_CCCR_ASM_MASK 0x00000004U |
| #define MCAN_CCCR_ASM_SHIFT 2U |
| #define MCAN_CCCR_CCE 0x00000002U |
| #define MCAN_CCCR_CCE_MASK 0x00000002U |
| #define MCAN_CCCR_CCE_SHIFT 1U |
| #define MCAN_CCCR_INIT 0x00000001U |
| #define MCAN_CCCR_INIT_MASK 0x00000001U |
| #define MCAN_CCCR_INIT_SHIFT 0U |
| #define MCAN_NBTP_NSJW_WIDTH 7U |
| #define MCAN_NBTP_NSJW_MASK 0xFE000000U |
| #define MCAN_NBTP_NSJW_SHIFT 25U |
| #define MCAN_NBTP_NBRP_WIDTH 9U |
| #define MCAN_NBTP_NBRP_MASK 0x01FF0000U |
| #define MCAN_NBTP_NBRP_SHIFT 16U |
| #define MCAN_NBTP_NTSEG1_WIDTH 8U |
| #define MCAN_NBTP_NTSEG1_MASK 0x0000FF00U |
| #define MCAN_NBTP_NTSEG1_SHIFT 8U |
| #define MCAN_NBTP_NTSEG2_WIDTH 7U |
| #define MCAN_NBTP_NTSEG2_MASK 0x0000007FU |
| #define MCAN_NBTP_NTSEG2_SHIFT 0U |
| #define MCAN_TSCC_TCP_WIDTH 4U |
| #define MCAN_TSCC_TCP_MASK 0x000F0000U |
| #define MCAN_TSCC_TCP_SHIFT 16U |
| #define MCAN_TSCC_TSS_WIDTH 2U |
| #define MCAN_TSCC_TSS_MASK 0x00000003U |
| #define MCAN_TSCC_TSS_SHIFT 0U |
| #define MCAN_TSCV_TSC_WIDTH 16U |
| #define MCAN_TSCV_TSC_MASK 0x0000FFFFU |
| #define MCAN_TSCV_TSC_SHIFT 0U |
| #define MCAN_TOCC_TOP_WIDTH 16U |
| #define MCAN_TOCC_TOP_MASK 0xFFFF0000U |
| #define MCAN_TOCC_TOP_SHIFT 16U |
| #define MCAN_TOCC_TOS_WIDTH 2U |
| #define MCAN_TOCC_TOS_MASK 0x00000006U |
| #define MCAN_TOCC_TOS_SHIFT 1U |
| #define MCAN_TOCC_ETOC 0x00000001U |
| #define MCAN_TOCC_ETOC_MASK 0x00000001U |
| #define MCAN_TOCC_ETOC_SHIFT 0U |
| #define MCAN_TOCV_TOC_WIDTH 16U |
| #define MCAN_TOCV_TOC_MASK 0x0000FFFFU |
| #define MCAN_TOCV_TOC_SHIFT 0U |
| #define MCAN_ECR_CEL_WIDTH 8U |
| #define MCAN_ECR_CEL_MASK 0x00FF0000U |
| #define MCAN_ECR_CEL_SHIFT 16U |
| #define MCAN_ECR_RP 0x00008000U |
| #define MCAN_ECR_RP_MASK 0x00008000U |
| #define MCAN_ECR_RP_SHIFT 15U |
| #define MCAN_ECR_REC_WIDTH 7U |
| #define MCAN_ECR_REC_MASK 0x00007F00U |
| #define MCAN_ECR_REC_SHIFT 8U |
| #define MCAN_ECR_TEC_WIDTH 8U |
| #define MCAN_ECR_TEC_MASK 0x000000FFU |
| #define MCAN_ECR_TEC_SHIFT 0U |
| #define MCAN_PSR_TDCV_WIDTH 7U |
| #define MCAN_PSR_TDCV_MASK 0x007F0000U |
| #define MCAN_PSR_TDCV_SHIFT 16U |
| #define MCAN_PSR_PXE 0x00004000U |
| #define MCAN_PSR_PXE_MASK 0x00004000U |
| #define MCAN_PSR_PXE_SHIFT 14U |
| #define MCAN_PSR_RFDF 0x00002000U |
| #define MCAN_PSR_RFDF_MASK 0x00002000U |
| #define MCAN_PSR_RFDF_SHIFT 13U |
| #define MCAN_PSR_RBRS 0x00001000U |
| #define MCAN_PSR_RBRS_MASK 0x00001000U |
| #define MCAN_PSR_RBRS_SHIFT 12U |
| #define MCAN_PSR_RESI 0x00000800U |
| #define MCAN_PSR_RESI_MASK 0x00000800U |
| #define MCAN_PSR_RESI_SHIFT 11U |
| #define MCAN_PSR_DLEC_WIDTH 3U |
| #define MCAN_PSR_DLEC_MASK 0x00000700U |
| #define MCAN_PSR_DLEC_SHIFT 8U |
| #define MCAN_PSR_BO 0x00000080U |
| #define MCAN_PSR_BO_MASK 0x00000080U |
| #define MCAN_PSR_BO_SHIFT 7U |
| #define MCAN_PSR_EW 0x00000040U |
| #define MCAN_PSR_EW_MASK 0x00000040U |
| #define MCAN_PSR_EW_SHIFT 6U |
| #define MCAN_PSR_EP 0x00000020U |
| #define MCAN_PSR_EP_MASK 0x00000020U |
| #define MCAN_PSR_EP_SHIFT 5U |
| #define MCAN_PSR_ACT_WIDTH 2U |
| #define MCAN_PSR_ACT_MASK 0x00000018U |
| #define MCAN_PSR_ACT_SHIFT 3U |
| #define MCAN_PSR_LEC_WIDTH 3U |
| #define MCAN_PSR_LEC_MASK 0x00000007U |
| #define MCAN_PSR_LEC_SHIFT 0U |
| #define MCAN_TDCR_TDCO_WIDTH 7U |
| #define MCAN_TDCR_TDCO_MASK 0x00007F00U |
| #define MCAN_TDCR_TDCO_SHIFT 8U |
| #define MCAN_TDCR_TDCF_WIDTH 7U |
| #define MCAN_TDCR_TDCF_MASK 0x0000007FU |
| #define MCAN_TDCR_TDCF_SHIFT 0U |
| #define MCAN_IR_ARA 0x20000000U |
| #define MCAN_IR_ARA_MASK 0x20000000U |
| #define MCAN_IR_ARA_SHIFT 29U |
| #define MCAN_IR_PED 0x10000000U |
| #define MCAN_IR_PED_MASK 0x10000000U |
| #define MCAN_IR_PED_SHIFT 28U |
| #define MCAN_IR_PEA 0x08000000U |
| #define MCAN_IR_PEA_MASK 0x08000000U |
| #define MCAN_IR_PEA_SHIFT 27U |
| #define MCAN_IR_WDI 0x04000000U |
| #define MCAN_IR_WDI_MASK 0x04000000U |
| #define MCAN_IR_WDI_SHIFT 26U |
| #define MCAN_IR_BO 0x02000000U |
| #define MCAN_IR_BO_MASK 0x02000000U |
| #define MCAN_IR_BO_SHIFT 25U |
| #define MCAN_IR_EW 0x01000000U |
| #define MCAN_IR_EW_MASK 0x01000000U |
| #define MCAN_IR_EW_SHIFT 24U |
| #define MCAN_IR_EP 0x00800000U |
| #define MCAN_IR_EP_MASK 0x00800000U |
| #define MCAN_IR_EP_SHIFT 23U |
| #define MCAN_IR_ELO 0x00400000U |
| #define MCAN_IR_ELO_MASK 0x00400000U |
| #define MCAN_IR_ELO_SHIFT 22U |
| #define MCAN_IR_BEU 0x00200000U |
| #define MCAN_IR_BEU_MASK 0x00200000U |
| #define MCAN_IR_BEU_SHIFT 21U |
| #define MCAN_IR_BEC 0x00100000U |
| #define MCAN_IR_BEC_MASK 0x00100000U |
| #define MCAN_IR_BEC_SHIFT 20U |
| #define MCAN_IR_DRX 0x00080000U |
| #define MCAN_IR_DRX_MASK 0x00080000U |
| #define MCAN_IR_DRX_SHIFT 19U |
| #define MCAN_IR_TOO 0x00040000U |
| #define MCAN_IR_TOO_MASK 0x00040000U |
| #define MCAN_IR_TOO_SHIFT 18U |
| #define MCAN_IR_MRAF 0x00020000U |
| #define MCAN_IR_MRAF_MASK 0x00020000U |
| #define MCAN_IR_MRAF_SHIFT 17U |
| #define MCAN_IR_TSW 0x00010000U |
| #define MCAN_IR_TSW_MASK 0x00010000U |
| #define MCAN_IR_TSW_SHIFT 16U |
| #define MCAN_IR_TEFL 0x00008000U |
| #define MCAN_IR_TEFL_MASK 0x00008000U |
| #define MCAN_IR_TEFL_SHIFT 15U |
| #define MCAN_IR_TEFF 0x00004000U |
| #define MCAN_IR_TEFF_MASK 0x00004000U |
| #define MCAN_IR_TEFF_SHIFT 14U |
| #define MCAN_IR_TEFW 0x00002000U |
| #define MCAN_IR_TEFW_MASK 0x00002000U |
| #define MCAN_IR_TEFW_SHIFT 13U |
| #define MCAN_IR_TEFN 0x00001000U |
| #define MCAN_IR_TEFN_MASK 0x00001000U |
| #define MCAN_IR_TEFN_SHIFT 12U |
| #define MCAN_IR_TFE 0x00000800U |
| #define MCAN_IR_TFE_MASK 0x00000800U |
| #define MCAN_IR_TFE_SHIFT 11U |
| #define MCAN_IR_TCF 0x00000400U |
| #define MCAN_IR_TCF_MASK 0x00000400U |
| #define MCAN_IR_TCF_SHIFT 10U |
| #define MCAN_IR_TC 0x00000200U |
| #define MCAN_IR_TC_MASK 0x00000200U |
| #define MCAN_IR_TC_SHIFT 9U |
| #define MCAN_IR_HPM 0x00000100U |
| #define MCAN_IR_HPM_MASK 0x00000100U |
| #define MCAN_IR_HPM_SHIFT 8U |
| #define MCAN_IR_RF1L 0x00000080U |
| #define MCAN_IR_RF1L_MASK 0x00000080U |
| #define MCAN_IR_RF1L_SHIFT 7U |
| #define MCAN_IR_RF1F 0x00000040U |
| #define MCAN_IR_RF1F_MASK 0x00000040U |
| #define MCAN_IR_RF1F_SHIFT 6U |
| #define MCAN_IR_RF1W 0x00000020U |
| #define MCAN_IR_RF1W_MASK 0x00000020U |
| #define MCAN_IR_RF1W_SHIFT 5U |
| #define MCAN_IR_RF1N 0x00000010U |
| #define MCAN_IR_RF1N_MASK 0x00000010U |
| #define MCAN_IR_RF1N_SHIFT 4U |
| #define MCAN_IR_RF0L 0x00000008U |
| #define MCAN_IR_RF0L_MASK 0x00000008U |
| #define MCAN_IR_RF0L_SHIFT 3U |
| #define MCAN_IR_RF0F 0x00000004U |
| #define MCAN_IR_RF0F_MASK 0x00000004U |
| #define MCAN_IR_RF0F_SHIFT 2U |
| #define MCAN_IR_RF0W 0x00000002U |
| #define MCAN_IR_RF0W_MASK 0x00000002U |
| #define MCAN_IR_RF0W_SHIFT 1U |
| #define MCAN_IR_RF0N 0x00000001U |
| #define MCAN_IR_RF0N_MASK 0x00000001U |
| #define MCAN_IR_RF0N_SHIFT 0U |
| #define MCAN_IE_ARAE 0x20000000U |
| #define MCAN_IE_ARAE_MASK 0x20000000U |
| #define MCAN_IE_ARAE_SHIFT 29U |
| #define MCAN_IE_PEDE 0x10000000U |
| #define MCAN_IE_PEDE_MASK 0x10000000U |
| #define MCAN_IE_PEDE_SHIFT 28U |
| #define MCAN_IE_PEAE 0x08000000U |
| #define MCAN_IE_PEAE_MASK 0x08000000U |
| #define MCAN_IE_PEAE_SHIFT 27U |
| #define MCAN_IE_WDIE 0x04000000U |
| #define MCAN_IE_WDIE_MASK 0x04000000U |
| #define MCAN_IE_WDIE_SHIFT 26U |
| #define MCAN_IE_BOE 0x02000000U |
| #define MCAN_IE_BOE_MASK 0x02000000U |
| #define MCAN_IE_BOE_SHIFT 25U |
| #define MCAN_IE_EWE 0x01000000U |
| #define MCAN_IE_EWE_MASK 0x01000000U |
| #define MCAN_IE_EWE_SHIFT 24U |
| #define MCAN_IE_EPE 0x00800000U |
| #define MCAN_IE_EPE_MASK 0x00800000U |
| #define MCAN_IE_EPE_SHIFT 23U |
| #define MCAN_IE_ELOE 0x00400000U |
| #define MCAN_IE_ELOE_MASK 0x00400000U |
| #define MCAN_IE_ELOE_SHIFT 22U |
| #define MCAN_IE_BEUE 0x00200000U |
| #define MCAN_IE_BEUE_MASK 0x00200000U |
| #define MCAN_IE_BEUE_SHIFT 21U |
| #define MCAN_IE_BECE 0x00100000U |
| #define MCAN_IE_BECE_MASK 0x00100000U |
| #define MCAN_IE_BECE_SHIFT 20U |
| #define MCAN_IE_DRXE 0x00080000U |
| #define MCAN_IE_DRXE_MASK 0x00080000U |
| #define MCAN_IE_DRXE_SHIFT 19U |
| #define MCAN_IE_TOOE 0x00040000U |
| #define MCAN_IE_TOOE_MASK 0x00040000U |
| #define MCAN_IE_TOOE_SHIFT 18U |
| #define MCAN_IE_MRAFE 0x00020000U |
| #define MCAN_IE_MRAFE_MASK 0x00020000U |
| #define MCAN_IE_MRAFE_SHIFT 17U |
| #define MCAN_IE_TSWE 0x00010000U |
| #define MCAN_IE_TSWE_MASK 0x00010000U |
| #define MCAN_IE_TSWE_SHIFT 16U |
| #define MCAN_IE_TEFLE 0x00008000U |
| #define MCAN_IE_TEFLE_MASK 0x00008000U |
| #define MCAN_IE_TEFLE_SHIFT 15U |
| #define MCAN_IE_TEFFE 0x00004000U |
| #define MCAN_IE_TEFFE_MASK 0x00004000U |
| #define MCAN_IE_TEFFE_SHIFT 14U |
| #define MCAN_IE_TEFWE 0x00002000U |
| #define MCAN_IE_TEFWE_MASK 0x00002000U |
| #define MCAN_IE_TEFWE_SHIFT 13U |
| #define MCAN_IE_TEFNE 0x00001000U |
| #define MCAN_IE_TEFNE_MASK 0x00001000U |
| #define MCAN_IE_TEFNE_SHIFT 12U |
| #define MCAN_IE_TFEE 0x00000800U |
| #define MCAN_IE_TFEE_MASK 0x00000800U |
| #define MCAN_IE_TFEE_SHIFT 11U |
| #define MCAN_IE_TCFE 0x00000400U |
| #define MCAN_IE_TCFE_MASK 0x00000400U |
| #define MCAN_IE_TCFE_SHIFT 10U |
| #define MCAN_IE_TCE 0x00000200U |
| #define MCAN_IE_TCE_MASK 0x00000200U |
| #define MCAN_IE_TCE_SHIFT 9U |
| #define MCAN_IE_HPME 0x00000100U |
| #define MCAN_IE_HPME_MASK 0x00000100U |
| #define MCAN_IE_HPME_SHIFT 8U |
| #define MCAN_IE_RF1LE 0x00000080U |
| #define MCAN_IE_RF1LE_MASK 0x00000080U |
| #define MCAN_IE_RF1LE_SHIFT 7U |
| #define MCAN_IE_RF1FE 0x00000040U |
| #define MCAN_IE_RF1FE_MASK 0x00000040U |
| #define MCAN_IE_RF1FE_SHIFT 6U |
| #define MCAN_IE_RF1WE 0x00000020U |
| #define MCAN_IE_RF1WE_MASK 0x00000020U |
| #define MCAN_IE_RF1WE_SHIFT 5U |
| #define MCAN_IE_RF1NE 0x00000010U |
| #define MCAN_IE_RF1NE_MASK 0x00000010U |
| #define MCAN_IE_RF1NE_SHIFT 4U |
| #define MCAN_IE_RF0LE 0x00000008U |
| #define MCAN_IE_RF0LE_MASK 0x00000008U |
| #define MCAN_IE_RF0LE_SHIFT 3U |
| #define MCAN_IE_RF0FE 0x00000004U |
| #define MCAN_IE_RF0FE_MASK 0x00000004U |
| #define MCAN_IE_RF0FE_SHIFT 2U |
| #define MCAN_IE_RF0WE 0x00000002U |
| #define MCAN_IE_RF0WE_MASK 0x00000002U |
| #define MCAN_IE_RF0WE_SHIFT 1U |
| #define MCAN_IE_RF0NE 0x00000001U |
| #define MCAN_IE_RF0NE_MASK 0x00000001U |
| #define MCAN_IE_RF0NE_SHIFT 0U |
| #define MCAN_ILS_ARAL 0x20000000U |
| #define MCAN_ILS_ARAL_MASK 0x20000000U |
| #define MCAN_ILS_ARAL_SHIFT 29U |
| #define MCAN_ILS_PEDL 0x10000000U |
| #define MCAN_ILS_PEDL_MASK 0x10000000U |
| #define MCAN_ILS_PEDL_SHIFT 28U |
| #define MCAN_ILS_PEAL 0x08000000U |
| #define MCAN_ILS_PEAL_MASK 0x08000000U |
| #define MCAN_ILS_PEAL_SHIFT 27U |
| #define MCAN_ILS_WDIL 0x04000000U |
| #define MCAN_ILS_WDIL_MASK 0x04000000U |
| #define MCAN_ILS_WDIL_SHIFT 26U |
| #define MCAN_ILS_BOL 0x02000000U |
| #define MCAN_ILS_BOL_MASK 0x02000000U |
| #define MCAN_ILS_BOL_SHIFT 25U |
| #define MCAN_ILS_EWL 0x01000000U |
| #define MCAN_ILS_EWL_MASK 0x01000000U |
| #define MCAN_ILS_EWL_SHIFT 24U |
| #define MCAN_ILS_EPL 0x00800000U |
| #define MCAN_ILS_EPL_MASK 0x00800000U |
| #define MCAN_ILS_EPL_SHIFT 23U |
| #define MCAN_ILS_ELOL 0x00400000U |
| #define MCAN_ILS_ELOL_MASK 0x00400000U |
| #define MCAN_ILS_ELOL_SHIFT 22U |
| #define MCAN_ILS_BEUL 0x00200000U |
| #define MCAN_ILS_BEUL_MASK 0x00200000U |
| #define MCAN_ILS_BEUL_SHIFT 21U |
| #define MCAN_ILS_BECL 0x00100000U |
| #define MCAN_ILS_BECL_MASK 0x00100000U |
| #define MCAN_ILS_BECL_SHIFT 20U |
| #define MCAN_ILS_DRXL 0x00080000U |
| #define MCAN_ILS_DRXL_MASK 0x00080000U |
| #define MCAN_ILS_DRXL_SHIFT 19U |
| #define MCAN_ILS_TOOL 0x00040000U |
| #define MCAN_ILS_TOOL_MASK 0x00040000U |
| #define MCAN_ILS_TOOL_SHIFT 18U |
| #define MCAN_ILS_MRAFL 0x00020000U |
| #define MCAN_ILS_MRAFL_MASK 0x00020000U |
| #define MCAN_ILS_MRAFL_SHIFT 17U |
| #define MCAN_ILS_TSWL 0x00010000U |
| #define MCAN_ILS_TSWL_MASK 0x00010000U |
| #define MCAN_ILS_TSWL_SHIFT 16U |
| #define MCAN_ILS_TEFLL 0x00008000U |
| #define MCAN_ILS_TEFLL_MASK 0x00008000U |
| #define MCAN_ILS_TEFLL_SHIFT 15U |
| #define MCAN_ILS_TEFFL 0x00004000U |
| #define MCAN_ILS_TEFFL_MASK 0x00004000U |
| #define MCAN_ILS_TEFFL_SHIFT 14U |
| #define MCAN_ILS_TEFWL 0x00002000U |
| #define MCAN_ILS_TEFWL_MASK 0x00002000U |
| #define MCAN_ILS_TEFWL_SHIFT 13U |
| #define MCAN_ILS_TEFNL 0x00001000U |
| #define MCAN_ILS_TEFNL_MASK 0x00001000U |
| #define MCAN_ILS_TEFNL_SHIFT 12U |
| #define MCAN_ILS_TFEL 0x00000800U |
| #define MCAN_ILS_TFEL_MASK 0x00000800U |
| #define MCAN_ILS_TFEL_SHIFT 11U |
| #define MCAN_ILS_TCFL 0x00000400U |
| #define MCAN_ILS_TCFL_MASK 0x00000400U |
| #define MCAN_ILS_TCFL_SHIFT 10U |
| #define MCAN_ILS_TCL 0x00000200U |
| #define MCAN_ILS_TCL_MASK 0x00000200U |
| #define MCAN_ILS_TCL_SHIFT 9U |
| #define MCAN_ILS_HPML 0x00000100U |
| #define MCAN_ILS_HPML_MASK 0x00000100U |
| #define MCAN_ILS_HPML_SHIFT 8U |
| #define MCAN_ILS_RF1LL 0x00000080U |
| #define MCAN_ILS_RF1LL_MASK 0x00000080U |
| #define MCAN_ILS_RF1LL_SHIFT 7U |
| #define MCAN_ILS_RF1FL 0x00000040U |
| #define MCAN_ILS_RF1FL_MASK 0x00000040U |
| #define MCAN_ILS_RF1FL_SHIFT 6U |
| #define MCAN_ILS_RF1WL 0x00000020U |
| #define MCAN_ILS_RF1WL_MASK 0x00000020U |
| #define MCAN_ILS_RF1WL_SHIFT 5U |
| #define MCAN_ILS_RF1NL 0x00000010U |
| #define MCAN_ILS_RF1NL_MASK 0x00000010U |
| #define MCAN_ILS_RF1NL_SHIFT 4U |
| #define MCAN_ILS_RF0LL 0x00000008U |
| #define MCAN_ILS_RF0LL_MASK 0x00000008U |
| #define MCAN_ILS_RF0LL_SHIFT 3U |
| #define MCAN_ILS_RF0FL 0x00000004U |
| #define MCAN_ILS_RF0FL_MASK 0x00000004U |
| #define MCAN_ILS_RF0FL_SHIFT 2U |
| #define MCAN_ILS_RF0WL 0x00000002U |
| #define MCAN_ILS_RF0WL_MASK 0x00000002U |
| #define MCAN_ILS_RF0WL_SHIFT 1U |
| #define MCAN_ILS_RF0NL 0x00000001U |
| #define MCAN_ILS_RF0NL_MASK 0x00000001U |
| #define MCAN_ILS_RF0NL_SHIFT 0U |
| #define MCAN_ILE_EINT1 0x00000002U |
| #define MCAN_ILE_EINT1_MASK 0x00000002U |
| #define MCAN_ILE_EINT1_SHIFT 1U |
| #define MCAN_ILE_EINT0 0x00000001U |
| #define MCAN_ILE_EINT0_MASK 0x00000001U |
| #define MCAN_ILE_EINT0_SHIFT 0U |
| #define MCAN_GFC_ANFS_WIDTH 2U |
| #define MCAN_GFC_ANFS_MASK 0x00000030U |
| #define MCAN_GFC_ANFS_SHIFT 4U |
| #define MCAN_GFC_ANFE_WIDTH 2U |
| #define MCAN_GFC_ANFE_MASK 0x0000000CU |
| #define MCAN_GFC_ANFE_SHIFT 2U |
| #define MCAN_GFC_RRFS 0x00000002U |
| #define MCAN_GFC_RRFS_MASK 0x00000002U |
| #define MCAN_GFC_RRFS_SHIFT 1U |
| #define MCAN_GFC_RRFE 0x00000001U |
| #define MCAN_GFC_RRFE_MASK 0x00000001U |
| #define MCAN_GFC_RRFE_SHIFT 0U |
| #define MCAN_SIDFC_LSS_WIDTH 8U |
| #define MCAN_SIDFC_LSS_MASK 0x00FF0000U |
| #define MCAN_SIDFC_LSS_SHIFT 16U |
| #define MCAN_SIDFC_FLSSA_WIDTH 14U |
| #define MCAN_SIDFC_FLSSA_MASK 0x0000FFFCU |
| #define MCAN_SIDFC_FLSSA_SHIFT 2U |
| #define MCAN_XIDFC_LSE_WIDTH 7U |
| #define MCAN_XIDFC_LSE_MASK 0x007F0000U |
| #define MCAN_XIDFC_LSE_SHIFT 16U |
| #define MCAN_XIDFC_FLESA_WIDTH 14U |
| #define MCAN_XIDFC_FLESA_MASK 0x0000FFFCU |
| #define MCAN_XIDFC_FLESA_SHIFT 2U |
| #define MCAN_XIDAM_EIDM_WIDTH 29U |
| #define MCAN_XIDAM_EIDM_MASK 0x1FFFFFFFU |
| #define MCAN_XIDAM_EIDM_SHIFT 0U |
| #define MCAN_HPMS_FLST 0x00008000U |
| #define MCAN_HPMS_FLST_MASK 0x00008000U |
| #define MCAN_HPMS_FLST_SHIFT 15U |
| #define MCAN_HPMS_FIDX_WIDTH 7U |
| #define MCAN_HPMS_FIDX_MASK 0x00007F00U |
| #define MCAN_HPMS_FIDX_SHIFT 8U |
| #define MCAN_HPMS_MSI_WIDTH 2U |
| #define MCAN_HPMS_MSI_MASK 0x000000C0U |
| #define MCAN_HPMS_MSI_SHIFT 6U |
| #define MCAN_HPMS_BIDX_WIDTH 6U |
| #define MCAN_HPMS_BIDX_MASK 0x0000003FU |
| #define MCAN_HPMS_BIDX_SHIFT 0U |
| #define MCAN_NDAT1_ND31 0x80000000U |
| #define MCAN_NDAT1_ND31_MASK 0x80000000U |
| #define MCAN_NDAT1_ND31_SHIFT 31U |
| #define MCAN_NDAT1_ND30 0x40000000U |
| #define MCAN_NDAT1_ND30_MASK 0x40000000U |
| #define MCAN_NDAT1_ND30_SHIFT 30U |
| #define MCAN_NDAT1_ND29 0x20000000U |
| #define MCAN_NDAT1_ND29_MASK 0x20000000U |
| #define MCAN_NDAT1_ND29_SHIFT 29U |
| #define MCAN_NDAT1_ND28 0x10000000U |
| #define MCAN_NDAT1_ND28_MASK 0x10000000U |
| #define MCAN_NDAT1_ND28_SHIFT 28U |
| #define MCAN_NDAT1_ND27 0x08000000U |
| #define MCAN_NDAT1_ND27_MASK 0x08000000U |
| #define MCAN_NDAT1_ND27_SHIFT 27U |
| #define MCAN_NDAT1_ND26 0x04000000U |
| #define MCAN_NDAT1_ND26_MASK 0x04000000U |
| #define MCAN_NDAT1_ND26_SHIFT 26U |
| #define MCAN_NDAT1_ND25 0x02000000U |
| #define MCAN_NDAT1_ND25_MASK 0x02000000U |
| #define MCAN_NDAT1_ND25_SHIFT 25U |
| #define MCAN_NDAT1_ND24 0x01000000U |
| #define MCAN_NDAT1_ND24_MASK 0x01000000U |
| #define MCAN_NDAT1_ND24_SHIFT 24U |
| #define MCAN_NDAT1_ND23 0x00800000U |
| #define MCAN_NDAT1_ND23_MASK 0x00800000U |
| #define MCAN_NDAT1_ND23_SHIFT 23U |
| #define MCAN_NDAT1_ND22 0x00400000U |
| #define MCAN_NDAT1_ND22_MASK 0x00400000U |
| #define MCAN_NDAT1_ND22_SHIFT 22U |
| #define MCAN_NDAT1_ND21 0x00200000U |
| #define MCAN_NDAT1_ND21_MASK 0x00200000U |
| #define MCAN_NDAT1_ND21_SHIFT 21U |
| #define MCAN_NDAT1_ND20 0x00100000U |
| #define MCAN_NDAT1_ND20_MASK 0x00100000U |
| #define MCAN_NDAT1_ND20_SHIFT 20U |
| #define MCAN_NDAT1_ND19 0x00080000U |
| #define MCAN_NDAT1_ND19_MASK 0x00080000U |
| #define MCAN_NDAT1_ND19_SHIFT 19U |
| #define MCAN_NDAT1_ND18 0x00040000U |
| #define MCAN_NDAT1_ND18_MASK 0x00040000U |
| #define MCAN_NDAT1_ND18_SHIFT 18U |
| #define MCAN_NDAT1_ND17 0x00020000U |
| #define MCAN_NDAT1_ND17_MASK 0x00020000U |
| #define MCAN_NDAT1_ND17_SHIFT 17U |
| #define MCAN_NDAT1_ND16 0x00010000U |
| #define MCAN_NDAT1_ND16_MASK 0x00010000U |
| #define MCAN_NDAT1_ND16_SHIFT 16U |
| #define MCAN_NDAT1_ND15 0x00008000U |
| #define MCAN_NDAT1_ND15_MASK 0x00008000U |
| #define MCAN_NDAT1_ND15_SHIFT 15U |
| #define MCAN_NDAT1_ND14 0x00004000U |
| #define MCAN_NDAT1_ND14_MASK 0x00004000U |
| #define MCAN_NDAT1_ND14_SHIFT 14U |
| #define MCAN_NDAT1_ND13 0x00002000U |
| #define MCAN_NDAT1_ND13_MASK 0x00002000U |
| #define MCAN_NDAT1_ND13_SHIFT 13U |
| #define MCAN_NDAT1_ND12 0x00001000U |
| #define MCAN_NDAT1_ND12_MASK 0x00001000U |
| #define MCAN_NDAT1_ND12_SHIFT 12U |
| #define MCAN_NDAT1_ND11 0x00000800U |
| #define MCAN_NDAT1_ND11_MASK 0x00000800U |
| #define MCAN_NDAT1_ND11_SHIFT 11U |
| #define MCAN_NDAT1_ND10 0x00000400U |
| #define MCAN_NDAT1_ND10_MASK 0x00000400U |
| #define MCAN_NDAT1_ND10_SHIFT 10U |
| #define MCAN_NDAT1_ND9 0x00000200U |
| #define MCAN_NDAT1_ND9_MASK 0x00000200U |
| #define MCAN_NDAT1_ND9_SHIFT 9U |
| #define MCAN_NDAT1_ND8 0x00000100U |
| #define MCAN_NDAT1_ND8_MASK 0x00000100U |
| #define MCAN_NDAT1_ND8_SHIFT 8U |
| #define MCAN_NDAT1_ND7 0x00000080U |
| #define MCAN_NDAT1_ND7_MASK 0x00000080U |
| #define MCAN_NDAT1_ND7_SHIFT 7U |
| #define MCAN_NDAT1_ND6 0x00000040U |
| #define MCAN_NDAT1_ND6_MASK 0x00000040U |
| #define MCAN_NDAT1_ND6_SHIFT 6U |
| #define MCAN_NDAT1_ND5 0x00000020U |
| #define MCAN_NDAT1_ND5_MASK 0x00000020U |
| #define MCAN_NDAT1_ND5_SHIFT 5U |
| #define MCAN_NDAT1_ND4 0x00000010U |
| #define MCAN_NDAT1_ND4_MASK 0x00000010U |
| #define MCAN_NDAT1_ND4_SHIFT 4U |
| #define MCAN_NDAT1_ND3 0x00000008U |
| #define MCAN_NDAT1_ND3_MASK 0x00000008U |
| #define MCAN_NDAT1_ND3_SHIFT 3U |
| #define MCAN_NDAT1_ND2 0x00000004U |
| #define MCAN_NDAT1_ND2_MASK 0x00000004U |
| #define MCAN_NDAT1_ND2_SHIFT 2U |
| #define MCAN_NDAT1_ND1 0x00000002U |
| #define MCAN_NDAT1_ND1_MASK 0x00000002U |
| #define MCAN_NDAT1_ND1_SHIFT 1U |
| #define MCAN_NDAT1_ND0 0x00000001U |
| #define MCAN_NDAT1_ND0_MASK 0x00000001U |
| #define MCAN_NDAT1_ND0_SHIFT 0U |
| #define MCAN_NDAT2_ND63 0x80000000U |
| #define MCAN_NDAT2_ND63_MASK 0x80000000U |
| #define MCAN_NDAT2_ND63_SHIFT 31U |
| #define MCAN_NDAT2_ND62 0x40000000U |
| #define MCAN_NDAT2_ND62_MASK 0x40000000U |
| #define MCAN_NDAT2_ND62_SHIFT 30U |
| #define MCAN_NDAT2_ND61 0x20000000U |
| #define MCAN_NDAT2_ND61_MASK 0x20000000U |
| #define MCAN_NDAT2_ND61_SHIFT 29U |
| #define MCAN_NDAT2_ND60 0x10000000U |
| #define MCAN_NDAT2_ND60_MASK 0x10000000U |
| #define MCAN_NDAT2_ND60_SHIFT 28U |
| #define MCAN_NDAT2_ND59 0x08000000U |
| #define MCAN_NDAT2_ND59_MASK 0x08000000U |
| #define MCAN_NDAT2_ND59_SHIFT 27U |
| #define MCAN_NDAT2_ND58 0x04000000U |
| #define MCAN_NDAT2_ND58_MASK 0x04000000U |
| #define MCAN_NDAT2_ND58_SHIFT 26U |
| #define MCAN_NDAT2_ND57 0x02000000U |
| #define MCAN_NDAT2_ND57_MASK 0x02000000U |
| #define MCAN_NDAT2_ND57_SHIFT 25U |
| #define MCAN_NDAT2_ND56 0x01000000U |
| #define MCAN_NDAT2_ND56_MASK 0x01000000U |
| #define MCAN_NDAT2_ND56_SHIFT 24U |
| #define MCAN_NDAT2_ND55 0x00800000U |
| #define MCAN_NDAT2_ND55_MASK 0x00800000U |
| #define MCAN_NDAT2_ND55_SHIFT 23U |
| #define MCAN_NDAT2_ND54 0x00400000U |
| #define MCAN_NDAT2_ND54_MASK 0x00400000U |
| #define MCAN_NDAT2_ND54_SHIFT 22U |
| #define MCAN_NDAT2_ND53 0x00200000U |
| #define MCAN_NDAT2_ND53_MASK 0x00200000U |
| #define MCAN_NDAT2_ND53_SHIFT 21U |
| #define MCAN_NDAT2_ND52 0x00100000U |
| #define MCAN_NDAT2_ND52_MASK 0x00100000U |
| #define MCAN_NDAT2_ND52_SHIFT 20U |
| #define MCAN_NDAT2_ND51 0x00080000U |
| #define MCAN_NDAT2_ND51_MASK 0x00080000U |
| #define MCAN_NDAT2_ND51_SHIFT 19U |
| #define MCAN_NDAT2_ND50 0x00040000U |
| #define MCAN_NDAT2_ND50_MASK 0x00040000U |
| #define MCAN_NDAT2_ND50_SHIFT 18U |
| #define MCAN_NDAT2_ND49 0x00020000U |
| #define MCAN_NDAT2_ND49_MASK 0x00020000U |
| #define MCAN_NDAT2_ND49_SHIFT 17U |
| #define MCAN_NDAT2_ND48 0x00010000U |
| #define MCAN_NDAT2_ND48_MASK 0x00010000U |
| #define MCAN_NDAT2_ND48_SHIFT 16U |
| #define MCAN_NDAT2_ND47 0x00008000U |
| #define MCAN_NDAT2_ND47_MASK 0x00008000U |
| #define MCAN_NDAT2_ND47_SHIFT 15U |
| #define MCAN_NDAT2_ND46 0x00004000U |
| #define MCAN_NDAT2_ND46_MASK 0x00004000U |
| #define MCAN_NDAT2_ND46_SHIFT 14U |
| #define MCAN_NDAT2_ND45 0x00002000U |
| #define MCAN_NDAT2_ND45_MASK 0x00002000U |
| #define MCAN_NDAT2_ND45_SHIFT 13U |
| #define MCAN_NDAT2_ND44 0x00001000U |
| #define MCAN_NDAT2_ND44_MASK 0x00001000U |
| #define MCAN_NDAT2_ND44_SHIFT 12U |
| #define MCAN_NDAT2_ND43 0x00000800U |
| #define MCAN_NDAT2_ND43_MASK 0x00000800U |
| #define MCAN_NDAT2_ND43_SHIFT 11U |
| #define MCAN_NDAT2_ND42 0x00000400U |
| #define MCAN_NDAT2_ND42_MASK 0x00000400U |
| #define MCAN_NDAT2_ND42_SHIFT 10U |
| #define MCAN_NDAT2_ND41 0x00000200U |
| #define MCAN_NDAT2_ND41_MASK 0x00000200U |
| #define MCAN_NDAT2_ND41_SHIFT 9U |
| #define MCAN_NDAT2_ND40 0x00000100U |
| #define MCAN_NDAT2_ND40_MASK 0x00000100U |
| #define MCAN_NDAT2_ND40_SHIFT 8U |
| #define MCAN_NDAT2_ND39 0x00000080U |
| #define MCAN_NDAT2_ND39_MASK 0x00000080U |
| #define MCAN_NDAT2_ND39_SHIFT 7U |
| #define MCAN_NDAT2_ND38 0x00000040U |
| #define MCAN_NDAT2_ND38_MASK 0x00000040U |
| #define MCAN_NDAT2_ND38_SHIFT 6U |
| #define MCAN_NDAT2_ND37 0x00000020U |
| #define MCAN_NDAT2_ND37_MASK 0x00000020U |
| #define MCAN_NDAT2_ND37_SHIFT 5U |
| #define MCAN_NDAT2_ND36 0x00000010U |
| #define MCAN_NDAT2_ND36_MASK 0x00000010U |
| #define MCAN_NDAT2_ND36_SHIFT 4U |
| #define MCAN_NDAT2_ND35 0x00000008U |
| #define MCAN_NDAT2_ND35_MASK 0x00000008U |
| #define MCAN_NDAT2_ND35_SHIFT 3U |
| #define MCAN_NDAT2_ND34 0x00000004U |
| #define MCAN_NDAT2_ND34_MASK 0x00000004U |
| #define MCAN_NDAT2_ND34_SHIFT 2U |
| #define MCAN_NDAT2_ND33 0x00000002U |
| #define MCAN_NDAT2_ND33_MASK 0x00000002U |
| #define MCAN_NDAT2_ND33_SHIFT 1U |
| #define MCAN_NDAT2_ND32 0x00000001U |
| #define MCAN_NDAT2_ND32_MASK 0x00000001U |
| #define MCAN_NDAT2_ND32_SHIFT 0U |
| #define MCAN_RXF0C_F0OM 0x80000000U |
| #define MCAN_RXF0C_F0OM_MASK 0x80000000U |
| #define MCAN_RXF0C_F0OM_SHIFT 31U |
| #define MCAN_RXF0C_F0WM_WIDTH 7U |
| #define MCAN_RXF0C_F0WM_MASK 0x7F000000U |
| #define MCAN_RXF0C_F0WM_SHIFT 24U |
| #define MCAN_RXF0C_F0S_WIDTH 7U |
| #define MCAN_RXF0C_F0S_MASK 0x007F0000U |
| #define MCAN_RXF0C_F0S_SHIFT 16U |
| #define MCAN_RXF0C_F0SA_WIDTH 14U |
| #define MCAN_RXF0C_F0SA_MASK 0x0000FFFCU |
| #define MCAN_RXF0C_F0SA_SHIFT 2U |
| #define MCAN_RXF0S_RF0L 0x02000000U |
| #define MCAN_RXF0S_RF0L_MASK 0x02000000U |
| #define MCAN_RXF0S_RF0L_SHIFT 25U |
| #define MCAN_RXF0S_F0F 0x01000000U |
| #define MCAN_RXF0S_F0F_MASK 0x01000000U |
| #define MCAN_RXF0S_F0F_SHIFT 24U |
| #define MCAN_RXF0S_F0PI_WIDTH 6U |
| #define MCAN_RXF0S_F0PI_MASK 0x003F0000U |
| #define MCAN_RXF0S_F0PI_SHIFT 16U |
| #define MCAN_RXF0S_F0GI_WIDTH 6U |
| #define MCAN_RXF0S_F0GI_MASK 0x00003F00U |
| #define MCAN_RXF0S_F0GI_SHIFT 8U |
| #define MCAN_RXF0S_F0FL_WIDTH 7U |
| #define MCAN_RXF0S_F0FL_MASK 0x0000007FU |
| #define MCAN_RXF0S_F0FL_SHIFT 0U |
| #define MCAN_RXF0A_F0AI_WIDTH 6U |
| #define MCAN_RXF0A_F0AI_MASK 0x0000003FU |
| #define MCAN_RXF0A_F0AI_SHIFT 0U |
| #define MCAN_RXBC_RBSA_WIDTH 14U |
| #define MCAN_RXBC_RBSA_MASK 0x0000FFFCU |
| #define MCAN_RXBC_RBSA_SHIFT 2U |
| #define MCAN_RXF1C_F1OM 0x80000000U |
| #define MCAN_RXF1C_F1OM_MASK 0x80000000U |
| #define MCAN_RXF1C_F1OM_SHIFT 31U |
| #define MCAN_RXF1C_F1WM_WIDTH 7U |
| #define MCAN_RXF1C_F1WM_MASK 0x7F000000U |
| #define MCAN_RXF1C_F1WM_SHIFT 24U |
| #define MCAN_RXF1C_F1S_WIDTH 7U |
| #define MCAN_RXF1C_F1S_MASK 0x007F0000U |
| #define MCAN_RXF1C_F1S_SHIFT 16U |
| #define MCAN_RXF1C_F1SA_WIDTH 14U |
| #define MCAN_RXF1C_F1SA_MASK 0x0000FFFCU |
| #define MCAN_RXF1C_F1SA_SHIFT 2U |
| #define MCAN_RXF1S_DMS_WIDTH 2U |
| #define MCAN_RXF1S_DMS_MASK 0xC0000000U |
| #define MCAN_RXF1S_DMS_SHIFT 30U |
| #define MCAN_RXF1S_RF1L 0x02000000U |
| #define MCAN_RXF1S_RF1L_MASK 0x02000000U |
| #define MCAN_RXF1S_RF1L_SHIFT 25U |
| #define MCAN_RXF1S_F1F 0x01000000U |
| #define MCAN_RXF1S_F1F_MASK 0x01000000U |
| #define MCAN_RXF1S_F1F_SHIFT 24U |
| #define MCAN_RXF1S_F1PI_WIDTH 6U |
| #define MCAN_RXF1S_F1PI_MASK 0x003F0000U |
| #define MCAN_RXF1S_F1PI_SHIFT 16U |
| #define MCAN_RXF1S_F1GI_WIDTH 6U |
| #define MCAN_RXF1S_F1GI_MASK 0x00003F00U |
| #define MCAN_RXF1S_F1GI_SHIFT 8U |
| #define MCAN_RXF1S_F1FL_WIDTH 7U |
| #define MCAN_RXF1S_F1FL_MASK 0x0000007FU |
| #define MCAN_RXF1S_F1FL_SHIFT 0U |
| #define MCAN_RXF1A_F1AI_WIDTH 6U |
| #define MCAN_RXF1A_F1AI_MASK 0x0000003FU |
| #define MCAN_RXF1A_F1AI_SHIFT 0U |
| #define MCAN_RXESC_RBDS_WIDTH 3U |
| #define MCAN_RXESC_RBDS_MASK 0x00000700U |
| #define MCAN_RXESC_RBDS_SHIFT 8U |
| #define MCAN_RXESC_F1DS_WIDTH 3U |
| #define MCAN_RXESC_F1DS_MASK 0x00000070U |
| #define MCAN_RXESC_F1DS_SHIFT 4U |
| #define MCAN_RXESC_F0DS_WIDTH 3U |
| #define MCAN_RXESC_F0DS_MASK 0x00000007U |
| #define MCAN_RXESC_F0DS_SHIFT 0U |
| #define MCAN_TXBC_TFQM 0x40000000U |
| #define MCAN_TXBC_TFQM_MASK 0x40000000U |
| #define MCAN_TXBC_TFQM_SHIFT 30U |
| #define MCAN_TXBC_TFQS_WIDTH 6U |
| #define MCAN_TXBC_TFQS_MASK 0x3F000000U |
| #define MCAN_TXBC_TFQS_SHIFT 24U |
| #define MCAN_TXBC_NDTB_WIDTH 6U |
| #define MCAN_TXBC_NDTB_MASK 0x003F0000U |
| #define MCAN_TXBC_NDTB_SHIFT 16U |
| #define MCAN_TXBC_TBSA_WIDTH 14U |
| #define MCAN_TXBC_TBSA_MASK 0x0000FFFCU |
| #define MCAN_TXBC_TBSA_SHIFT 2U |
| #define MCAN_TXFQS_TFQF 0x00200000U |
| #define MCAN_TXFQS_TFQF_MASK 0x00200000U |
| #define MCAN_TXFQS_TFQF_SHIFT 21U |
| #define MCAN_TXFQS_TFQPI_WIDTH 5U |
| #define MCAN_TXFQS_TFQPI_MASK 0x001F0000U |
| #define MCAN_TXFQS_TFQPI_SHIFT 16U |
| #define MCAN_TXFQS_TFGI_WIDTH 5U |
| #define MCAN_TXFQS_TFGI_MASK 0x00001F00U |
| #define MCAN_TXFQS_TFGI_SHIFT 8U |
| #define MCAN_TXFQS_TFFL_WIDTH 6U |
| #define MCAN_TXFQS_TFFL_MASK 0x0000003FU |
| #define MCAN_TXFQS_TFFL_SHIFT 0U |
| #define MCAN_TXESC_TBDS_WIDTH 3U |
| #define MCAN_TXESC_TBDS_MASK 0x00000007U |
| #define MCAN_TXESC_TBDS_SHIFT 0U |
| #define MCAN_TXBRP_TRP31 0x80000000U |
| #define MCAN_TXBRP_TRP31_MASK 0x80000000U |
| #define MCAN_TXBRP_TRP31_SHIFT 31U |
| #define MCAN_TXBRP_TRP30 0x40000000U |
| #define MCAN_TXBRP_TRP30_MASK 0x40000000U |
| #define MCAN_TXBRP_TRP30_SHIFT 30U |
| #define MCAN_TXBRP_TRP29 0x20000000U |
| #define MCAN_TXBRP_TRP29_MASK 0x20000000U |
| #define MCAN_TXBRP_TRP29_SHIFT 29U |
| #define MCAN_TXBRP_TRP28 0x10000000U |
| #define MCAN_TXBRP_TRP28_MASK 0x10000000U |
| #define MCAN_TXBRP_TRP28_SHIFT 28U |
| #define MCAN_TXBRP_TRP27 0x08000000U |
| #define MCAN_TXBRP_TRP27_MASK 0x08000000U |
| #define MCAN_TXBRP_TRP27_SHIFT 27U |
| #define MCAN_TXBRP_TRP26 0x04000000U |
| #define MCAN_TXBRP_TRP26_MASK 0x04000000U |
| #define MCAN_TXBRP_TRP26_SHIFT 26U |
| #define MCAN_TXBRP_TRP25 0x02000000U |
| #define MCAN_TXBRP_TRP25_MASK 0x02000000U |
| #define MCAN_TXBRP_TRP25_SHIFT 25U |
| #define MCAN_TXBRP_TRP24 0x01000000U |
| #define MCAN_TXBRP_TRP24_MASK 0x01000000U |
| #define MCAN_TXBRP_TRP24_SHIFT 24U |
| #define MCAN_TXBRP_TRP23 0x00800000U |
| #define MCAN_TXBRP_TRP23_MASK 0x00800000U |
| #define MCAN_TXBRP_TRP23_SHIFT 23U |
| #define MCAN_TXBRP_TRP22 0x00400000U |
| #define MCAN_TXBRP_TRP22_MASK 0x00400000U |
| #define MCAN_TXBRP_TRP22_SHIFT 22U |
| #define MCAN_TXBRP_TRP21 0x00200000U |
| #define MCAN_TXBRP_TRP21_MASK 0x00200000U |
| #define MCAN_TXBRP_TRP21_SHIFT 21U |
| #define MCAN_TXBRP_TRP20 0x00100000U |
| #define MCAN_TXBRP_TRP20_MASK 0x00100000U |
| #define MCAN_TXBRP_TRP20_SHIFT 20U |
| #define MCAN_TXBRP_TRP19 0x00080000U |
| #define MCAN_TXBRP_TRP19_MASK 0x00080000U |
| #define MCAN_TXBRP_TRP19_SHIFT 19U |
| #define MCAN_TXBRP_TRP18 0x00040000U |
| #define MCAN_TXBRP_TRP18_MASK 0x00040000U |
| #define MCAN_TXBRP_TRP18_SHIFT 18U |
| #define MCAN_TXBRP_TRP17 0x00020000U |
| #define MCAN_TXBRP_TRP17_MASK 0x00020000U |
| #define MCAN_TXBRP_TRP17_SHIFT 17U |
| #define MCAN_TXBRP_TRP16 0x00010000U |
| #define MCAN_TXBRP_TRP16_MASK 0x00010000U |
| #define MCAN_TXBRP_TRP16_SHIFT 16U |
| #define MCAN_TXBRP_TRP15 0x00008000U |
| #define MCAN_TXBRP_TRP15_MASK 0x00008000U |
| #define MCAN_TXBRP_TRP15_SHIFT 15U |
| #define MCAN_TXBRP_TRP14 0x00004000U |
| #define MCAN_TXBRP_TRP14_MASK 0x00004000U |
| #define MCAN_TXBRP_TRP14_SHIFT 14U |
| #define MCAN_TXBRP_TRP13 0x00002000U |
| #define MCAN_TXBRP_TRP13_MASK 0x00002000U |
| #define MCAN_TXBRP_TRP13_SHIFT 13U |
| #define MCAN_TXBRP_TRP12 0x00001000U |
| #define MCAN_TXBRP_TRP12_MASK 0x00001000U |
| #define MCAN_TXBRP_TRP12_SHIFT 12U |
| #define MCAN_TXBRP_TRP11 0x00000800U |
| #define MCAN_TXBRP_TRP11_MASK 0x00000800U |
| #define MCAN_TXBRP_TRP11_SHIFT 11U |
| #define MCAN_TXBRP_TRP10 0x00000400U |
| #define MCAN_TXBRP_TRP10_MASK 0x00000400U |
| #define MCAN_TXBRP_TRP10_SHIFT 10U |
| #define MCAN_TXBRP_TRP9 0x00000200U |
| #define MCAN_TXBRP_TRP9_MASK 0x00000200U |
| #define MCAN_TXBRP_TRP9_SHIFT 9U |
| #define MCAN_TXBRP_TRP8 0x00000100U |
| #define MCAN_TXBRP_TRP8_MASK 0x00000100U |
| #define MCAN_TXBRP_TRP8_SHIFT 8U |
| #define MCAN_TXBRP_TRP7 0x00000080U |
| #define MCAN_TXBRP_TRP7_MASK 0x00000080U |
| #define MCAN_TXBRP_TRP7_SHIFT 7U |
| #define MCAN_TXBRP_TRP6 0x00000040U |
| #define MCAN_TXBRP_TRP6_MASK 0x00000040U |
| #define MCAN_TXBRP_TRP6_SHIFT 6U |
| #define MCAN_TXBRP_TRP5 0x00000020U |
| #define MCAN_TXBRP_TRP5_MASK 0x00000020U |
| #define MCAN_TXBRP_TRP5_SHIFT 5U |
| #define MCAN_TXBRP_TRP4 0x00000010U |
| #define MCAN_TXBRP_TRP4_MASK 0x00000010U |
| #define MCAN_TXBRP_TRP4_SHIFT 4U |
| #define MCAN_TXBRP_TRP3 0x00000008U |
| #define MCAN_TXBRP_TRP3_MASK 0x00000008U |
| #define MCAN_TXBRP_TRP3_SHIFT 3U |
| #define MCAN_TXBRP_TRP2 0x00000004U |
| #define MCAN_TXBRP_TRP2_MASK 0x00000004U |
| #define MCAN_TXBRP_TRP2_SHIFT 2U |
| #define MCAN_TXBRP_TRP1 0x00000002U |
| #define MCAN_TXBRP_TRP1_MASK 0x00000002U |
| #define MCAN_TXBRP_TRP1_SHIFT 1U |
| #define MCAN_TXBRP_TRP0 0x00000001U |
| #define MCAN_TXBRP_TRP0_MASK 0x00000001U |
| #define MCAN_TXBRP_TRP0_SHIFT 0U |
| #define MCAN_TXBAR_AR31 0x80000000U |
| #define MCAN_TXBAR_AR31_MASK 0x80000000U |
| #define MCAN_TXBAR_AR31_SHIFT 31U |
| #define MCAN_TXBAR_AR30 0x40000000U |
| #define MCAN_TXBAR_AR30_MASK 0x40000000U |
| #define MCAN_TXBAR_AR30_SHIFT 30U |
| #define MCAN_TXBAR_AR29 0x20000000U |
| #define MCAN_TXBAR_AR29_MASK 0x20000000U |
| #define MCAN_TXBAR_AR29_SHIFT 29U |
| #define MCAN_TXBAR_AR28 0x10000000U |
| #define MCAN_TXBAR_AR28_MASK 0x10000000U |
| #define MCAN_TXBAR_AR28_SHIFT 28U |
| #define MCAN_TXBAR_AR27 0x08000000U |
| #define MCAN_TXBAR_AR27_MASK 0x08000000U |
| #define MCAN_TXBAR_AR27_SHIFT 27U |
| #define MCAN_TXBAR_AR26 0x04000000U |
| #define MCAN_TXBAR_AR26_MASK 0x04000000U |
| #define MCAN_TXBAR_AR26_SHIFT 26U |
| #define MCAN_TXBAR_AR25 0x02000000U |
| #define MCAN_TXBAR_AR25_MASK 0x02000000U |
| #define MCAN_TXBAR_AR25_SHIFT 25U |
| #define MCAN_TXBAR_AR24 0x01000000U |
| #define MCAN_TXBAR_AR24_MASK 0x01000000U |
| #define MCAN_TXBAR_AR24_SHIFT 24U |
| #define MCAN_TXBAR_AR23 0x00800000U |
| #define MCAN_TXBAR_AR23_MASK 0x00800000U |
| #define MCAN_TXBAR_AR23_SHIFT 23U |
| #define MCAN_TXBAR_AR22 0x00400000U |
| #define MCAN_TXBAR_AR22_MASK 0x00400000U |
| #define MCAN_TXBAR_AR22_SHIFT 22U |
| #define MCAN_TXBAR_AR21 0x00200000U |
| #define MCAN_TXBAR_AR21_MASK 0x00200000U |
| #define MCAN_TXBAR_AR21_SHIFT 21U |
| #define MCAN_TXBAR_AR20 0x00100000U |
| #define MCAN_TXBAR_AR20_MASK 0x00100000U |
| #define MCAN_TXBAR_AR20_SHIFT 20U |
| #define MCAN_TXBAR_AR19 0x00080000U |
| #define MCAN_TXBAR_AR19_MASK 0x00080000U |
| #define MCAN_TXBAR_AR19_SHIFT 19U |
| #define MCAN_TXBAR_AR18 0x00040000U |
| #define MCAN_TXBAR_AR18_MASK 0x00040000U |
| #define MCAN_TXBAR_AR18_SHIFT 18U |
| #define MCAN_TXBAR_AR17 0x00020000U |
| #define MCAN_TXBAR_AR17_MASK 0x00020000U |
| #define MCAN_TXBAR_AR17_SHIFT 17U |
| #define MCAN_TXBAR_AR16 0x00010000U |
| #define MCAN_TXBAR_AR16_MASK 0x00010000U |
| #define MCAN_TXBAR_AR16_SHIFT 16U |
| #define MCAN_TXBAR_AR15 0x00008000U |
| #define MCAN_TXBAR_AR15_MASK 0x00008000U |
| #define MCAN_TXBAR_AR15_SHIFT 15U |
| #define MCAN_TXBAR_AR14 0x00004000U |
| #define MCAN_TXBAR_AR14_MASK 0x00004000U |
| #define MCAN_TXBAR_AR14_SHIFT 14U |
| #define MCAN_TXBAR_AR13 0x00002000U |
| #define MCAN_TXBAR_AR13_MASK 0x00002000U |
| #define MCAN_TXBAR_AR13_SHIFT 13U |
| #define MCAN_TXBAR_AR12 0x00001000U |
| #define MCAN_TXBAR_AR12_MASK 0x00001000U |
| #define MCAN_TXBAR_AR12_SHIFT 12U |
| #define MCAN_TXBAR_AR11 0x00000800U |
| #define MCAN_TXBAR_AR11_MASK 0x00000800U |
| #define MCAN_TXBAR_AR11_SHIFT 11U |
| #define MCAN_TXBAR_AR10 0x00000400U |
| #define MCAN_TXBAR_AR10_MASK 0x00000400U |
| #define MCAN_TXBAR_AR10_SHIFT 10U |
| #define MCAN_TXBAR_AR9 0x00000200U |
| #define MCAN_TXBAR_AR9_MASK 0x00000200U |
| #define MCAN_TXBAR_AR9_SHIFT 9U |
| #define MCAN_TXBAR_AR8 0x00000100U |
| #define MCAN_TXBAR_AR8_MASK 0x00000100U |
| #define MCAN_TXBAR_AR8_SHIFT 8U |
| #define MCAN_TXBAR_AR7 0x00000080U |
| #define MCAN_TXBAR_AR7_MASK 0x00000080U |
| #define MCAN_TXBAR_AR7_SHIFT 7U |
| #define MCAN_TXBAR_AR6 0x00000040U |
| #define MCAN_TXBAR_AR6_MASK 0x00000040U |
| #define MCAN_TXBAR_AR6_SHIFT 6U |
| #define MCAN_TXBAR_AR5 0x00000020U |
| #define MCAN_TXBAR_AR5_MASK 0x00000020U |
| #define MCAN_TXBAR_AR5_SHIFT 5U |
| #define MCAN_TXBAR_AR4 0x00000010U |
| #define MCAN_TXBAR_AR4_MASK 0x00000010U |
| #define MCAN_TXBAR_AR4_SHIFT 4U |
| #define MCAN_TXBAR_AR3 0x00000008U |
| #define MCAN_TXBAR_AR3_MASK 0x00000008U |
| #define MCAN_TXBAR_AR3_SHIFT 3U |
| #define MCAN_TXBAR_AR2 0x00000004U |
| #define MCAN_TXBAR_AR2_MASK 0x00000004U |
| #define MCAN_TXBAR_AR2_SHIFT 2U |
| #define MCAN_TXBAR_AR1 0x00000002U |
| #define MCAN_TXBAR_AR1_MASK 0x00000002U |
| #define MCAN_TXBAR_AR1_SHIFT 1U |
| #define MCAN_TXBAR_AR0 0x00000001U |
| #define MCAN_TXBAR_AR0_MASK 0x00000001U |
| #define MCAN_TXBAR_AR0_SHIFT 0U |
| #define MCAN_TXBCR_CR31 0x80000000U |
| #define MCAN_TXBCR_CR31_MASK 0x80000000U |
| #define MCAN_TXBCR_CR31_SHIFT 31U |
| #define MCAN_TXBCR_CR30 0x40000000U |
| #define MCAN_TXBCR_CR30_MASK 0x40000000U |
| #define MCAN_TXBCR_CR30_SHIFT 30U |
| #define MCAN_TXBCR_CR29 0x20000000U |
| #define MCAN_TXBCR_CR29_MASK 0x20000000U |
| #define MCAN_TXBCR_CR29_SHIFT 29U |
| #define MCAN_TXBCR_CR28 0x10000000U |
| #define MCAN_TXBCR_CR28_MASK 0x10000000U |
| #define MCAN_TXBCR_CR28_SHIFT 28U |
| #define MCAN_TXBCR_CR27 0x08000000U |
| #define MCAN_TXBCR_CR27_MASK 0x08000000U |
| #define MCAN_TXBCR_CR27_SHIFT 27U |
| #define MCAN_TXBCR_CR26 0x04000000U |
| #define MCAN_TXBCR_CR26_MASK 0x04000000U |
| #define MCAN_TXBCR_CR26_SHIFT 26U |
| #define MCAN_TXBCR_CR25 0x02000000U |
| #define MCAN_TXBCR_CR25_MASK 0x02000000U |
| #define MCAN_TXBCR_CR25_SHIFT 25U |
| #define MCAN_TXBCR_CR24 0x01000000U |
| #define MCAN_TXBCR_CR24_MASK 0x01000000U |
| #define MCAN_TXBCR_CR24_SHIFT 24U |
| #define MCAN_TXBCR_CR23 0x00800000U |
| #define MCAN_TXBCR_CR23_MASK 0x00800000U |
| #define MCAN_TXBCR_CR23_SHIFT 23U |
| #define MCAN_TXBCR_CR22 0x00400000U |
| #define MCAN_TXBCR_CR22_MASK 0x00400000U |
| #define MCAN_TXBCR_CR22_SHIFT 22U |
| #define MCAN_TXBCR_CR21 0x00200000U |
| #define MCAN_TXBCR_CR21_MASK 0x00200000U |
| #define MCAN_TXBCR_CR21_SHIFT 21U |
| #define MCAN_TXBCR_CR20 0x00100000U |
| #define MCAN_TXBCR_CR20_MASK 0x00100000U |
| #define MCAN_TXBCR_CR20_SHIFT 20U |
| #define MCAN_TXBCR_CR19 0x00080000U |
| #define MCAN_TXBCR_CR19_MASK 0x00080000U |
| #define MCAN_TXBCR_CR19_SHIFT 19U |
| #define MCAN_TXBCR_CR18 0x00040000U |
| #define MCAN_TXBCR_CR18_MASK 0x00040000U |
| #define MCAN_TXBCR_CR18_SHIFT 18U |
| #define MCAN_TXBCR_CR17 0x00020000U |
| #define MCAN_TXBCR_CR17_MASK 0x00020000U |
| #define MCAN_TXBCR_CR17_SHIFT 17U |
| #define MCAN_TXBCR_CR16 0x00010000U |
| #define MCAN_TXBCR_CR16_MASK 0x00010000U |
| #define MCAN_TXBCR_CR16_SHIFT 16U |
| #define MCAN_TXBCR_CR15 0x00008000U |
| #define MCAN_TXBCR_CR15_MASK 0x00008000U |
| #define MCAN_TXBCR_CR15_SHIFT 15U |
| #define MCAN_TXBCR_CR14 0x00004000U |
| #define MCAN_TXBCR_CR14_MASK 0x00004000U |
| #define MCAN_TXBCR_CR14_SHIFT 14U |
| #define MCAN_TXBCR_CR13 0x00002000U |
| #define MCAN_TXBCR_CR13_MASK 0x00002000U |
| #define MCAN_TXBCR_CR13_SHIFT 13U |
| #define MCAN_TXBCR_CR12 0x00001000U |
| #define MCAN_TXBCR_CR12_MASK 0x00001000U |
| #define MCAN_TXBCR_CR12_SHIFT 12U |
| #define MCAN_TXBCR_CR11 0x00000800U |
| #define MCAN_TXBCR_CR11_MASK 0x00000800U |
| #define MCAN_TXBCR_CR11_SHIFT 11U |
| #define MCAN_TXBCR_CR10 0x00000400U |
| #define MCAN_TXBCR_CR10_MASK 0x00000400U |
| #define MCAN_TXBCR_CR10_SHIFT 10U |
| #define MCAN_TXBCR_CR9 0x00000200U |
| #define MCAN_TXBCR_CR9_MASK 0x00000200U |
| #define MCAN_TXBCR_CR9_SHIFT 9U |
| #define MCAN_TXBCR_CR8 0x00000100U |
| #define MCAN_TXBCR_CR8_MASK 0x00000100U |
| #define MCAN_TXBCR_CR8_SHIFT 8U |
| #define MCAN_TXBCR_CR7 0x00000080U |
| #define MCAN_TXBCR_CR7_MASK 0x00000080U |
| #define MCAN_TXBCR_CR7_SHIFT 7U |
| #define MCAN_TXBCR_CR6 0x00000040U |
| #define MCAN_TXBCR_CR6_MASK 0x00000040U |
| #define MCAN_TXBCR_CR6_SHIFT 6U |
| #define MCAN_TXBCR_CR5 0x00000020U |
| #define MCAN_TXBCR_CR5_MASK 0x00000020U |
| #define MCAN_TXBCR_CR5_SHIFT 5U |
| #define MCAN_TXBCR_CR4 0x00000010U |
| #define MCAN_TXBCR_CR4_MASK 0x00000010U |
| #define MCAN_TXBCR_CR4_SHIFT 4U |
| #define MCAN_TXBCR_CR3 0x00000008U |
| #define MCAN_TXBCR_CR3_MASK 0x00000008U |
| #define MCAN_TXBCR_CR3_SHIFT 3U |
| #define MCAN_TXBCR_CR2 0x00000004U |
| #define MCAN_TXBCR_CR2_MASK 0x00000004U |
| #define MCAN_TXBCR_CR2_SHIFT 2U |
| #define MCAN_TXBCR_CR1 0x00000002U |
| #define MCAN_TXBCR_CR1_MASK 0x00000002U |
| #define MCAN_TXBCR_CR1_SHIFT 1U |
| #define MCAN_TXBCR_CR0 0x00000001U |
| #define MCAN_TXBCR_CR0_MASK 0x00000001U |
| #define MCAN_TXBCR_CR0_SHIFT 0U |
| #define MCAN_TXBTO_TO31 0x80000000U |
| #define MCAN_TXBTO_TO31_MASK 0x80000000U |
| #define MCAN_TXBTO_TO31_SHIFT 31U |
| #define MCAN_TXBTO_TO30 0x40000000U |
| #define MCAN_TXBTO_TO30_MASK 0x40000000U |
| #define MCAN_TXBTO_TO30_SHIFT 30U |
| #define MCAN_TXBTO_TO29 0x20000000U |
| #define MCAN_TXBTO_TO29_MASK 0x20000000U |
| #define MCAN_TXBTO_TO29_SHIFT 29U |
| #define MCAN_TXBTO_TO28 0x10000000U |
| #define MCAN_TXBTO_TO28_MASK 0x10000000U |
| #define MCAN_TXBTO_TO28_SHIFT 28U |
| #define MCAN_TXBTO_TO27 0x08000000U |
| #define MCAN_TXBTO_TO27_MASK 0x08000000U |
| #define MCAN_TXBTO_TO27_SHIFT 27U |
| #define MCAN_TXBTO_TO26 0x04000000U |
| #define MCAN_TXBTO_TO26_MASK 0x04000000U |
| #define MCAN_TXBTO_TO26_SHIFT 26U |
| #define MCAN_TXBTO_TO25 0x02000000U |
| #define MCAN_TXBTO_TO25_MASK 0x02000000U |
| #define MCAN_TXBTO_TO25_SHIFT 25U |
| #define MCAN_TXBTO_TO24 0x01000000U |
| #define MCAN_TXBTO_TO24_MASK 0x01000000U |
| #define MCAN_TXBTO_TO24_SHIFT 24U |
| #define MCAN_TXBTO_TO23 0x00800000U |
| #define MCAN_TXBTO_TO23_MASK 0x00800000U |
| #define MCAN_TXBTO_TO23_SHIFT 23U |
| #define MCAN_TXBTO_TO22 0x00400000U |
| #define MCAN_TXBTO_TO22_MASK 0x00400000U |
| #define MCAN_TXBTO_TO22_SHIFT 22U |
| #define MCAN_TXBTO_TO21 0x00200000U |
| #define MCAN_TXBTO_TO21_MASK 0x00200000U |
| #define MCAN_TXBTO_TO21_SHIFT 21U |
| #define MCAN_TXBTO_TO20 0x00100000U |
| #define MCAN_TXBTO_TO20_MASK 0x00100000U |
| #define MCAN_TXBTO_TO20_SHIFT 20U |
| #define MCAN_TXBTO_TO19 0x00080000U |
| #define MCAN_TXBTO_TO19_MASK 0x00080000U |
| #define MCAN_TXBTO_TO19_SHIFT 19U |
| #define MCAN_TXBTO_TO18 0x00040000U |
| #define MCAN_TXBTO_TO18_MASK 0x00040000U |
| #define MCAN_TXBTO_TO18_SHIFT 18U |
| #define MCAN_TXBTO_TO17 0x00020000U |
| #define MCAN_TXBTO_TO17_MASK 0x00020000U |
| #define MCAN_TXBTO_TO17_SHIFT 17U |
| #define MCAN_TXBTO_TO16 0x00010000U |
| #define MCAN_TXBTO_TO16_MASK 0x00010000U |
| #define MCAN_TXBTO_TO16_SHIFT 16U |
| #define MCAN_TXBTO_TO15 0x00008000U |
| #define MCAN_TXBTO_TO15_MASK 0x00008000U |
| #define MCAN_TXBTO_TO15_SHIFT 15U |
| #define MCAN_TXBTO_TO14 0x00004000U |
| #define MCAN_TXBTO_TO14_MASK 0x00004000U |
| #define MCAN_TXBTO_TO14_SHIFT 14U |
| #define MCAN_TXBTO_TO13 0x00002000U |
| #define MCAN_TXBTO_TO13_MASK 0x00002000U |
| #define MCAN_TXBTO_TO13_SHIFT 13U |
| #define MCAN_TXBTO_TO12 0x00001000U |
| #define MCAN_TXBTO_TO12_MASK 0x00001000U |
| #define MCAN_TXBTO_TO12_SHIFT 12U |
| #define MCAN_TXBTO_TO11 0x00000800U |
| #define MCAN_TXBTO_TO11_MASK 0x00000800U |
| #define MCAN_TXBTO_TO11_SHIFT 11U |
| #define MCAN_TXBTO_TO10 0x00000400U |
| #define MCAN_TXBTO_TO10_MASK 0x00000400U |
| #define MCAN_TXBTO_TO10_SHIFT 10U |
| #define MCAN_TXBTO_TO9 0x00000200U |
| #define MCAN_TXBTO_TO9_MASK 0x00000200U |
| #define MCAN_TXBTO_TO9_SHIFT 9U |
| #define MCAN_TXBTO_TO8 0x00000100U |
| #define MCAN_TXBTO_TO8_MASK 0x00000100U |
| #define MCAN_TXBTO_TO8_SHIFT 8U |
| #define MCAN_TXBTO_TO7 0x00000080U |
| #define MCAN_TXBTO_TO7_MASK 0x00000080U |
| #define MCAN_TXBTO_TO7_SHIFT 7U |
| #define MCAN_TXBTO_TO6 0x00000040U |
| #define MCAN_TXBTO_TO6_MASK 0x00000040U |
| #define MCAN_TXBTO_TO6_SHIFT 6U |
| #define MCAN_TXBTO_TO5 0x00000020U |
| #define MCAN_TXBTO_TO5_MASK 0x00000020U |
| #define MCAN_TXBTO_TO5_SHIFT 5U |
| #define MCAN_TXBTO_TO4 0x00000010U |
| #define MCAN_TXBTO_TO4_MASK 0x00000010U |
| #define MCAN_TXBTO_TO4_SHIFT 4U |
| #define MCAN_TXBTO_TO3 0x00000008U |
| #define MCAN_TXBTO_TO3_MASK 0x00000008U |
| #define MCAN_TXBTO_TO3_SHIFT 3U |
| #define MCAN_TXBTO_TO2 0x00000004U |
| #define MCAN_TXBTO_TO2_MASK 0x00000004U |
| #define MCAN_TXBTO_TO2_SHIFT 2U |
| #define MCAN_TXBTO_TO1 0x00000002U |
| #define MCAN_TXBTO_TO1_MASK 0x00000002U |
| #define MCAN_TXBTO_TO1_SHIFT 1U |
| #define MCAN_TXBTO_TO0 0x00000001U |
| #define MCAN_TXBTO_TO0_MASK 0x00000001U |
| #define MCAN_TXBTO_TO0_SHIFT 0U |
| #define MCAN_TXBCF_CF31 0x80000000U |
| #define MCAN_TXBCF_CF31_MASK 0x80000000U |
| #define MCAN_TXBCF_CF31_SHIFT 31U |
| #define MCAN_TXBCF_CF30 0x40000000U |
| #define MCAN_TXBCF_CF30_MASK 0x40000000U |
| #define MCAN_TXBCF_CF30_SHIFT 30U |
| #define MCAN_TXBCF_CF29 0x20000000U |
| #define MCAN_TXBCF_CF29_MASK 0x20000000U |
| #define MCAN_TXBCF_CF29_SHIFT 29U |
| #define MCAN_TXBCF_CF28 0x10000000U |
| #define MCAN_TXBCF_CF28_MASK 0x10000000U |
| #define MCAN_TXBCF_CF28_SHIFT 28U |
| #define MCAN_TXBCF_CF27 0x08000000U |
| #define MCAN_TXBCF_CF27_MASK 0x08000000U |
| #define MCAN_TXBCF_CF27_SHIFT 27U |
| #define MCAN_TXBCF_CF26 0x04000000U |
| #define MCAN_TXBCF_CF26_MASK 0x04000000U |
| #define MCAN_TXBCF_CF26_SHIFT 26U |
| #define MCAN_TXBCF_CF25 0x02000000U |
| #define MCAN_TXBCF_CF25_MASK 0x02000000U |
| #define MCAN_TXBCF_CF25_SHIFT 25U |
| #define MCAN_TXBCF_CF24 0x01000000U |
| #define MCAN_TXBCF_CF24_MASK 0x01000000U |
| #define MCAN_TXBCF_CF24_SHIFT 24U |
| #define MCAN_TXBCF_CF23 0x00800000U |
| #define MCAN_TXBCF_CF23_MASK 0x00800000U |
| #define MCAN_TXBCF_CF23_SHIFT 23U |
| #define MCAN_TXBCF_CF22 0x00400000U |
| #define MCAN_TXBCF_CF22_MASK 0x00400000U |
| #define MCAN_TXBCF_CF22_SHIFT 22U |
| #define MCAN_TXBCF_CF21 0x00200000U |
| #define MCAN_TXBCF_CF21_MASK 0x00200000U |
| #define MCAN_TXBCF_CF21_SHIFT 21U |
| #define MCAN_TXBCF_CF20 0x00100000U |
| #define MCAN_TXBCF_CF20_MASK 0x00100000U |
| #define MCAN_TXBCF_CF20_SHIFT 20U |
| #define MCAN_TXBCF_CF19 0x00080000U |
| #define MCAN_TXBCF_CF19_MASK 0x00080000U |
| #define MCAN_TXBCF_CF19_SHIFT 19U |
| #define MCAN_TXBCF_CF18 0x00040000U |
| #define MCAN_TXBCF_CF18_MASK 0x00040000U |
| #define MCAN_TXBCF_CF18_SHIFT 18U |
| #define MCAN_TXBCF_CF17 0x00020000U |
| #define MCAN_TXBCF_CF17_MASK 0x00020000U |
| #define MCAN_TXBCF_CF17_SHIFT 17U |
| #define MCAN_TXBCF_CF16 0x00010000U |
| #define MCAN_TXBCF_CF16_MASK 0x00010000U |
| #define MCAN_TXBCF_CF16_SHIFT 16U |
| #define MCAN_TXBCF_CF15 0x00008000U |
| #define MCAN_TXBCF_CF15_MASK 0x00008000U |
| #define MCAN_TXBCF_CF15_SHIFT 15U |
| #define MCAN_TXBCF_CF14 0x00004000U |
| #define MCAN_TXBCF_CF14_MASK 0x00004000U |
| #define MCAN_TXBCF_CF14_SHIFT 14U |
| #define MCAN_TXBCF_CF13 0x00002000U |
| #define MCAN_TXBCF_CF13_MASK 0x00002000U |
| #define MCAN_TXBCF_CF13_SHIFT 13U |
| #define MCAN_TXBCF_CF12 0x00001000U |
| #define MCAN_TXBCF_CF12_MASK 0x00001000U |
| #define MCAN_TXBCF_CF12_SHIFT 12U |
| #define MCAN_TXBCF_CF11 0x00000800U |
| #define MCAN_TXBCF_CF11_MASK 0x00000800U |
| #define MCAN_TXBCF_CF11_SHIFT 11U |
| #define MCAN_TXBCF_CF10 0x00000400U |
| #define MCAN_TXBCF_CF10_MASK 0x00000400U |
| #define MCAN_TXBCF_CF10_SHIFT 10U |
| #define MCAN_TXBCF_CF9 0x00000200U |
| #define MCAN_TXBCF_CF9_MASK 0x00000200U |
| #define MCAN_TXBCF_CF9_SHIFT 9U |
| #define MCAN_TXBCF_CF8 0x00000100U |
| #define MCAN_TXBCF_CF8_MASK 0x00000100U |
| #define MCAN_TXBCF_CF8_SHIFT 8U |
| #define MCAN_TXBCF_CF7 0x00000080U |
| #define MCAN_TXBCF_CF7_MASK 0x00000080U |
| #define MCAN_TXBCF_CF7_SHIFT 7U |
| #define MCAN_TXBCF_CF6 0x00000040U |
| #define MCAN_TXBCF_CF6_MASK 0x00000040U |
| #define MCAN_TXBCF_CF6_SHIFT 6U |
| #define MCAN_TXBCF_CF5 0x00000020U |
| #define MCAN_TXBCF_CF5_MASK 0x00000020U |
| #define MCAN_TXBCF_CF5_SHIFT 5U |
| #define MCAN_TXBCF_CF4 0x00000010U |
| #define MCAN_TXBCF_CF4_MASK 0x00000010U |
| #define MCAN_TXBCF_CF4_SHIFT 4U |
| #define MCAN_TXBCF_CF3 0x00000008U |
| #define MCAN_TXBCF_CF3_MASK 0x00000008U |
| #define MCAN_TXBCF_CF3_SHIFT 3U |
| #define MCAN_TXBCF_CF2 0x00000004U |
| #define MCAN_TXBCF_CF2_MASK 0x00000004U |
| #define MCAN_TXBCF_CF2_SHIFT 2U |
| #define MCAN_TXBCF_CF1 0x00000002U |
| #define MCAN_TXBCF_CF1_MASK 0x00000002U |
| #define MCAN_TXBCF_CF1_SHIFT 1U |
| #define MCAN_TXBCF_CF0 0x00000001U |
| #define MCAN_TXBCF_CF0_MASK 0x00000001U |
| #define MCAN_TXBCF_CF0_SHIFT 0U |
| #define MCAN_TXBTIE_TIE31 0x80000000U |
| #define MCAN_TXBTIE_TIE31_MASK 0x80000000U |
| #define MCAN_TXBTIE_TIE31_SHIFT 31U |
| #define MCAN_TXBTIE_TIE30 0x40000000U |
| #define MCAN_TXBTIE_TIE30_MASK 0x40000000U |
| #define MCAN_TXBTIE_TIE30_SHIFT 30U |
| #define MCAN_TXBTIE_TIE29 0x20000000U |
| #define MCAN_TXBTIE_TIE29_MASK 0x20000000U |
| #define MCAN_TXBTIE_TIE29_SHIFT 29U |
| #define MCAN_TXBTIE_TIE28 0x10000000U |
| #define MCAN_TXBTIE_TIE28_MASK 0x10000000U |
| #define MCAN_TXBTIE_TIE28_SHIFT 28U |
| #define MCAN_TXBTIE_TIE27 0x08000000U |
| #define MCAN_TXBTIE_TIE27_MASK 0x08000000U |
| #define MCAN_TXBTIE_TIE27_SHIFT 27U |
| #define MCAN_TXBTIE_TIE26 0x04000000U |
| #define MCAN_TXBTIE_TIE26_MASK 0x04000000U |
| #define MCAN_TXBTIE_TIE26_SHIFT 26U |
| #define MCAN_TXBTIE_TIE25 0x02000000U |
| #define MCAN_TXBTIE_TIE25_MASK 0x02000000U |
| #define MCAN_TXBTIE_TIE25_SHIFT 25U |
| #define MCAN_TXBTIE_TIE24 0x01000000U |
| #define MCAN_TXBTIE_TIE24_MASK 0x01000000U |
| #define MCAN_TXBTIE_TIE24_SHIFT 24U |
| #define MCAN_TXBTIE_TIE23 0x00800000U |
| #define MCAN_TXBTIE_TIE23_MASK 0x00800000U |
| #define MCAN_TXBTIE_TIE23_SHIFT 23U |
| #define MCAN_TXBTIE_TIE22 0x00400000U |
| #define MCAN_TXBTIE_TIE22_MASK 0x00400000U |
| #define MCAN_TXBTIE_TIE22_SHIFT 22U |
| #define MCAN_TXBTIE_TIE21 0x00200000U |
| #define MCAN_TXBTIE_TIE21_MASK 0x00200000U |
| #define MCAN_TXBTIE_TIE21_SHIFT 21U |
| #define MCAN_TXBTIE_TIE20 0x00100000U |
| #define MCAN_TXBTIE_TIE20_MASK 0x00100000U |
| #define MCAN_TXBTIE_TIE20_SHIFT 20U |
| #define MCAN_TXBTIE_TIE19 0x00080000U |
| #define MCAN_TXBTIE_TIE19_MASK 0x00080000U |
| #define MCAN_TXBTIE_TIE19_SHIFT 19U |
| #define MCAN_TXBTIE_TIE18 0x00040000U |
| #define MCAN_TXBTIE_TIE18_MASK 0x00040000U |
| #define MCAN_TXBTIE_TIE18_SHIFT 18U |
| #define MCAN_TXBTIE_TIE17 0x00020000U |
| #define MCAN_TXBTIE_TIE17_MASK 0x00020000U |
| #define MCAN_TXBTIE_TIE17_SHIFT 17U |
| #define MCAN_TXBTIE_TIE16 0x00010000U |
| #define MCAN_TXBTIE_TIE16_MASK 0x00010000U |
| #define MCAN_TXBTIE_TIE16_SHIFT 16U |
| #define MCAN_TXBTIE_TIE15 0x00008000U |
| #define MCAN_TXBTIE_TIE15_MASK 0x00008000U |
| #define MCAN_TXBTIE_TIE15_SHIFT 15U |
| #define MCAN_TXBTIE_TIE14 0x00004000U |
| #define MCAN_TXBTIE_TIE14_MASK 0x00004000U |
| #define MCAN_TXBTIE_TIE14_SHIFT 14U |
| #define MCAN_TXBTIE_TIE13 0x00002000U |
| #define MCAN_TXBTIE_TIE13_MASK 0x00002000U |
| #define MCAN_TXBTIE_TIE13_SHIFT 13U |
| #define MCAN_TXBTIE_TIE12 0x00001000U |
| #define MCAN_TXBTIE_TIE12_MASK 0x00001000U |
| #define MCAN_TXBTIE_TIE12_SHIFT 12U |
| #define MCAN_TXBTIE_TIE11 0x00000800U |
| #define MCAN_TXBTIE_TIE11_MASK 0x00000800U |
| #define MCAN_TXBTIE_TIE11_SHIFT 11U |
| #define MCAN_TXBTIE_TIE10 0x00000400U |
| #define MCAN_TXBTIE_TIE10_MASK 0x00000400U |
| #define MCAN_TXBTIE_TIE10_SHIFT 10U |
| #define MCAN_TXBTIE_TIE9 0x00000200U |
| #define MCAN_TXBTIE_TIE9_MASK 0x00000200U |
| #define MCAN_TXBTIE_TIE9_SHIFT 9U |
| #define MCAN_TXBTIE_TIE8 0x00000100U |
| #define MCAN_TXBTIE_TIE8_MASK 0x00000100U |
| #define MCAN_TXBTIE_TIE8_SHIFT 8U |
| #define MCAN_TXBTIE_TIE7 0x00000080U |
| #define MCAN_TXBTIE_TIE7_MASK 0x00000080U |
| #define MCAN_TXBTIE_TIE7_SHIFT 7U |
| #define MCAN_TXBTIE_TIE6 0x00000040U |
| #define MCAN_TXBTIE_TIE6_MASK 0x00000040U |
| #define MCAN_TXBTIE_TIE6_SHIFT 6U |
| #define MCAN_TXBTIE_TIE5 0x00000020U |
| #define MCAN_TXBTIE_TIE5_MASK 0x00000020U |
| #define MCAN_TXBTIE_TIE5_SHIFT 5U |
| #define MCAN_TXBTIE_TIE4 0x00000010U |
| #define MCAN_TXBTIE_TIE4_MASK 0x00000010U |
| #define MCAN_TXBTIE_TIE4_SHIFT 4U |
| #define MCAN_TXBTIE_TIE3 0x00000008U |
| #define MCAN_TXBTIE_TIE3_MASK 0x00000008U |
| #define MCAN_TXBTIE_TIE3_SHIFT 3U |
| #define MCAN_TXBTIE_TIE2 0x00000004U |
| #define MCAN_TXBTIE_TIE2_MASK 0x00000004U |
| #define MCAN_TXBTIE_TIE2_SHIFT 2U |
| #define MCAN_TXBTIE_TIE1 0x00000002U |
| #define MCAN_TXBTIE_TIE1_MASK 0x00000002U |
| #define MCAN_TXBTIE_TIE1_SHIFT 1U |
| #define MCAN_TXBTIE_TIE0 0x00000001U |
| #define MCAN_TXBTIE_TIE0_MASK 0x00000001U |
| #define MCAN_TXBTIE_TIE0_SHIFT 0U |
| #define MCAN_TXBCIE_CFIE31 0x80000000U |
| #define MCAN_TXBCIE_CFIE31_MASK 0x80000000U |
| #define MCAN_TXBCIE_CFIE31_SHIFT 31U |
| #define MCAN_TXBCIE_CFIE30 0x40000000U |
| #define MCAN_TXBCIE_CFIE30_MASK 0x40000000U |
| #define MCAN_TXBCIE_CFIE30_SHIFT 30U |
| #define MCAN_TXBCIE_CFIE29 0x20000000U |
| #define MCAN_TXBCIE_CFIE29_MASK 0x20000000U |
| #define MCAN_TXBCIE_CFIE29_SHIFT 29U |
| #define MCAN_TXBCIE_CFIE28 0x10000000U |
| #define MCAN_TXBCIE_CFIE28_MASK 0x10000000U |
| #define MCAN_TXBCIE_CFIE28_SHIFT 28U |
| #define MCAN_TXBCIE_CFIE27 0x08000000U |
| #define MCAN_TXBCIE_CFIE27_MASK 0x08000000U |
| #define MCAN_TXBCIE_CFIE27_SHIFT 27U |
| #define MCAN_TXBCIE_CFIE26 0x04000000U |
| #define MCAN_TXBCIE_CFIE26_MASK 0x04000000U |
| #define MCAN_TXBCIE_CFIE26_SHIFT 26U |
| #define MCAN_TXBCIE_CFIE25 0x02000000U |
| #define MCAN_TXBCIE_CFIE25_MASK 0x02000000U |
| #define MCAN_TXBCIE_CFIE25_SHIFT 25U |
| #define MCAN_TXBCIE_CFIE24 0x01000000U |
| #define MCAN_TXBCIE_CFIE24_MASK 0x01000000U |
| #define MCAN_TXBCIE_CFIE24_SHIFT 24U |
| #define MCAN_TXBCIE_CFIE23 0x00800000U |
| #define MCAN_TXBCIE_CFIE23_MASK 0x00800000U |
| #define MCAN_TXBCIE_CFIE23_SHIFT 23U |
| #define MCAN_TXBCIE_CFIE22 0x00400000U |
| #define MCAN_TXBCIE_CFIE22_MASK 0x00400000U |
| #define MCAN_TXBCIE_CFIE22_SHIFT 22U |
| #define MCAN_TXBCIE_CFIE21 0x00200000U |
| #define MCAN_TXBCIE_CFIE21_MASK 0x00200000U |
| #define MCAN_TXBCIE_CFIE21_SHIFT 21U |
| #define MCAN_TXBCIE_CFIE20 0x00100000U |
| #define MCAN_TXBCIE_CFIE20_MASK 0x00100000U |
| #define MCAN_TXBCIE_CFIE20_SHIFT 20U |
| #define MCAN_TXBCIE_CFIE19 0x00080000U |
| #define MCAN_TXBCIE_CFIE19_MASK 0x00080000U |
| #define MCAN_TXBCIE_CFIE19_SHIFT 19U |
| #define MCAN_TXBCIE_CFIE18 0x00040000U |
| #define MCAN_TXBCIE_CFIE18_MASK 0x00040000U |
| #define MCAN_TXBCIE_CFIE18_SHIFT 18U |
| #define MCAN_TXBCIE_CFIE17 0x00020000U |
| #define MCAN_TXBCIE_CFIE17_MASK 0x00020000U |
| #define MCAN_TXBCIE_CFIE17_SHIFT 17U |
| #define MCAN_TXBCIE_CFIE16 0x00010000U |
| #define MCAN_TXBCIE_CFIE16_MASK 0x00010000U |
| #define MCAN_TXBCIE_CFIE16_SHIFT 16U |
| #define MCAN_TXBCIE_CFIE15 0x00008000U |
| #define MCAN_TXBCIE_CFIE15_MASK 0x00008000U |
| #define MCAN_TXBCIE_CFIE15_SHIFT 15U |
| #define MCAN_TXBCIE_CFIE14 0x00004000U |
| #define MCAN_TXBCIE_CFIE14_MASK 0x00004000U |
| #define MCAN_TXBCIE_CFIE14_SHIFT 14U |
| #define MCAN_TXBCIE_CFIE13 0x00002000U |
| #define MCAN_TXBCIE_CFIE13_MASK 0x00002000U |
| #define MCAN_TXBCIE_CFIE13_SHIFT 13U |
| #define MCAN_TXBCIE_CFIE12 0x00001000U |
| #define MCAN_TXBCIE_CFIE12_MASK 0x00001000U |
| #define MCAN_TXBCIE_CFIE12_SHIFT 12U |
| #define MCAN_TXBCIE_CFIE11 0x00000800U |
| #define MCAN_TXBCIE_CFIE11_MASK 0x00000800U |
| #define MCAN_TXBCIE_CFIE11_SHIFT 11U |
| #define MCAN_TXBCIE_CFIE10 0x00000400U |
| #define MCAN_TXBCIE_CFIE10_MASK 0x00000400U |
| #define MCAN_TXBCIE_CFIE10_SHIFT 10U |
| #define MCAN_TXBCIE_CFIE9 0x00000200U |
| #define MCAN_TXBCIE_CFIE9_MASK 0x00000200U |
| #define MCAN_TXBCIE_CFIE9_SHIFT 9U |
| #define MCAN_TXBCIE_CFIE8 0x00000100U |
| #define MCAN_TXBCIE_CFIE8_MASK 0x00000100U |
| #define MCAN_TXBCIE_CFIE8_SHIFT 8U |
| #define MCAN_TXBCIE_CFIE7 0x00000080U |
| #define MCAN_TXBCIE_CFIE7_MASK 0x00000080U |
| #define MCAN_TXBCIE_CFIE7_SHIFT 7U |
| #define MCAN_TXBCIE_CFIE6 0x00000040U |
| #define MCAN_TXBCIE_CFIE6_MASK 0x00000040U |
| #define MCAN_TXBCIE_CFIE6_SHIFT 6U |
| #define MCAN_TXBCIE_CFIE5 0x00000020U |
| #define MCAN_TXBCIE_CFIE5_MASK 0x00000020U |
| #define MCAN_TXBCIE_CFIE5_SHIFT 5U |
| #define MCAN_TXBCIE_CFIE4 0x00000010U |
| #define MCAN_TXBCIE_CFIE4_MASK 0x00000010U |
| #define MCAN_TXBCIE_CFIE4_SHIFT 4U |
| #define MCAN_TXBCIE_CFIE3 0x00000008U |
| #define MCAN_TXBCIE_CFIE3_MASK 0x00000008U |
| #define MCAN_TXBCIE_CFIE3_SHIFT 3U |
| #define MCAN_TXBCIE_CFIE2 0x00000004U |
| #define MCAN_TXBCIE_CFIE2_MASK 0x00000004U |
| #define MCAN_TXBCIE_CFIE2_SHIFT 2U |
| #define MCAN_TXBCIE_CFIE1 0x00000002U |
| #define MCAN_TXBCIE_CFIE1_MASK 0x00000002U |
| #define MCAN_TXBCIE_CFIE1_SHIFT 1U |
| #define MCAN_TXBCIE_CFIE0 0x00000001U |
| #define MCAN_TXBCIE_CFIE0_MASK 0x00000001U |
| #define MCAN_TXBCIE_CFIE0_SHIFT 0U |
| #define MCAN_TXEFC_EFWM_WIDTH 6U |
| #define MCAN_TXEFC_EFWM_MASK 0x3F000000U |
| #define MCAN_TXEFC_EFWM_SHIFT 24U |
| #define MCAN_TXEFC_EFS_WIDTH 6U |
| #define MCAN_TXEFC_EFS_MASK 0x003F0000U |
| #define MCAN_TXEFC_EFS_SHIFT 16U |
| #define MCAN_TXEFC_EFSA_WIDTH 14U |
| #define MCAN_TXEFC_EFSA_MASK 0x0000FFFCU |
| #define MCAN_TXEFC_EFSA_SHIFT 2U |
| #define MCAN_TXEFS_TEFL 0x02000000U |
| #define MCAN_TXEFS_TEFL_MASK 0x02000000U |
| #define MCAN_TXEFS_TEFL_SHIFT 25U |
| #define MCAN_TXEFS_EFF 0x01000000U |
| #define MCAN_TXEFS_EFF_MASK 0x01000000U |
| #define MCAN_TXEFS_EFF_SHIFT 24U |
| #define MCAN_TXEFS_EFPI_WIDTH 5U |
| #define MCAN_TXEFS_EFPI_MASK 0x001F0000U |
| #define MCAN_TXEFS_EFPI_SHIFT 16U |
| #define MCAN_TXEFS_EFGI_WIDTH 5U |
| #define MCAN_TXEFS_EFGI_MASK 0x00001F00U |
| #define MCAN_TXEFS_EFGI_SHIFT 8U |
| #define MCAN_TXEFS_EFFL_WIDTH 6U |
| #define MCAN_TXEFS_EFFL_MASK 0x0000003FU |
| #define MCAN_TXEFS_EFFL_SHIFT 0U |
| #define MCAN_TXEFA_EFAI_WIDTH 5U |
| #define MCAN_TXEFA_EFAI_MASK 0x0000001FU |
| #define MCAN_TXEFA_EFAI_SHIFT 0U |