CC27xxDriverLibrary
Macros
hw_scb.h File Reference

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Macros

#define SCB_O_REVIDR   0x00000000U
 
#define SCB_O_CPUID   0x00000004U
 
#define SCB_O_ICSR   0x00000008U
 
#define SCB_O_VTOR   0x0000000CU
 
#define SCB_O_AIRCR   0x00000010U
 
#define SCB_O_SCR   0x00000014U
 
#define SCB_O_CCR   0x00000018U
 
#define SCB_O_SHPR1   0x0000001CU
 
#define SCB_O_SHPR2   0x00000020U
 
#define SCB_O_SHPR3   0x00000024U
 
#define SCB_O_SHCSR   0x00000028U
 
#define SCB_O_CFSR   0x0000002CU
 
#define SCB_O_HFSR   0x00000030U
 
#define SCB_O_DFSR   0x00000034U
 
#define SCB_O_MMFAR   0x00000038U
 
#define SCB_O_BFAR   0x0000003CU
 
#define SCB_O_AFSR   0x00000040U
 
#define SCB_O_ID_PFR0   0x00000044U
 
#define SCB_O_ID_PFR1   0x00000048U
 
#define SCB_O_ID_DFR0   0x0000004CU
 
#define SCB_O_ID_AFR0   0x00000050U
 
#define SCB_O_ID_MMFR0   0x00000054U
 
#define SCB_O_ID_MMFR1   0x00000058U
 
#define SCB_O_ID_MMFR2   0x0000005CU
 
#define SCB_O_ID_MMFR3   0x00000060U
 
#define SCB_O_ID_ISAR0   0x00000064U
 
#define SCB_O_ID_ISAR1   0x00000068U
 
#define SCB_O_ID_ISAR2   0x0000006CU
 
#define SCB_O_ID_ISAR3   0x00000070U
 
#define SCB_O_ID_ISAR4   0x00000074U
 
#define SCB_O_ID_ISAR5   0x00000078U
 
#define SCB_O_CLIDR   0x0000007CU
 
#define SCB_O_CTR   0x00000080U
 
#define SCB_O_CCSIDR   0x00000084U
 
#define SCB_O_CSSELR   0x00000088U
 
#define SCB_O_CPACR   0x0000008CU
 
#define SCB_O_NSACR   0x00000090U
 
#define SCB_REVIDR_IMPLEMENTAION_DEFINED_W   32U
 
#define SCB_REVIDR_IMPLEMENTAION_DEFINED_M   0xFFFFFFFFU
 
#define SCB_REVIDR_IMPLEMENTAION_DEFINED_S   0U
 
#define SCB_CPUID_IMPLEMENTER_W   8U
 
#define SCB_CPUID_IMPLEMENTER_M   0xFF000000U
 
#define SCB_CPUID_IMPLEMENTER_S   24U
 
#define SCB_CPUID_VARIANT_W   4U
 
#define SCB_CPUID_VARIANT_M   0x00F00000U
 
#define SCB_CPUID_VARIANT_S   20U
 
#define SCB_CPUID_ARCHITECTURE_W   4U
 
#define SCB_CPUID_ARCHITECTURE_M   0x000F0000U
 
#define SCB_CPUID_ARCHITECTURE_S   16U
 
#define SCB_CPUID_PARTNO_W   12U
 
#define SCB_CPUID_PARTNO_M   0x0000FFF0U
 
#define SCB_CPUID_PARTNO_S   4U
 
#define SCB_CPUID_REVISION_W   4U
 
#define SCB_CPUID_REVISION_M   0x0000000FU
 
#define SCB_CPUID_REVISION_S   0U
 
#define SCB_ICSR_PENDNMISET   0x80000000U
 
#define SCB_ICSR_PENDNMISET_M   0x80000000U
 
#define SCB_ICSR_PENDNMISET_S   31U
 
#define SCB_ICSR_PENDNMICLR   0x40000000U
 
#define SCB_ICSR_PENDNMICLR_M   0x40000000U
 
#define SCB_ICSR_PENDNMICLR_S   30U
 
#define SCB_ICSR_RES0   0x20000000U
 
#define SCB_ICSR_RES0_M   0x20000000U
 
#define SCB_ICSR_RES0_S   29U
 
#define SCB_ICSR_PENDSVSET   0x10000000U
 
#define SCB_ICSR_PENDSVSET_M   0x10000000U
 
#define SCB_ICSR_PENDSVSET_S   28U
 
#define SCB_ICSR_PENDSVCLR   0x08000000U
 
#define SCB_ICSR_PENDSVCLR_M   0x08000000U
 
#define SCB_ICSR_PENDSVCLR_S   27U
 
#define SCB_ICSR_PENDSTSET   0x04000000U
 
#define SCB_ICSR_PENDSTSET_M   0x04000000U
 
#define SCB_ICSR_PENDSTSET_S   26U
 
#define SCB_ICSR_PENDSTCLR   0x02000000U
 
#define SCB_ICSR_PENDSTCLR_M   0x02000000U
 
#define SCB_ICSR_PENDSTCLR_S   25U
 
#define SCB_ICSR_STTNS   0x01000000U
 
#define SCB_ICSR_STTNS_M   0x01000000U
 
#define SCB_ICSR_STTNS_S   24U
 
#define SCB_ICSR_ISRPREEMPT   0x00800000U
 
#define SCB_ICSR_ISRPREEMPT_M   0x00800000U
 
#define SCB_ICSR_ISRPREEMPT_S   23U
 
#define SCB_ICSR_ISRPENDING   0x00400000U
 
#define SCB_ICSR_ISRPENDING_M   0x00400000U
 
#define SCB_ICSR_ISRPENDING_S   22U
 
#define SCB_ICSR_RES0_1   0x00200000U
 
#define SCB_ICSR_RES0_1_M   0x00200000U
 
#define SCB_ICSR_RES0_1_S   21U
 
#define SCB_ICSR_VECTPENDING_W   9U
 
#define SCB_ICSR_VECTPENDING_M   0x001FF000U
 
#define SCB_ICSR_VECTPENDING_S   12U
 
#define SCB_ICSR_RETTOBASE   0x00000800U
 
#define SCB_ICSR_RETTOBASE_M   0x00000800U
 
#define SCB_ICSR_RETTOBASE_S   11U
 
#define SCB_ICSR_RES0_2_W   2U
 
#define SCB_ICSR_RES0_2_M   0x00000600U
 
#define SCB_ICSR_RES0_2_S   9U
 
#define SCB_ICSR_VECTACTIVE_W   9U
 
#define SCB_ICSR_VECTACTIVE_M   0x000001FFU
 
#define SCB_ICSR_VECTACTIVE_S   0U
 
#define SCB_VTOR_TBLOFF_W   25U
 
#define SCB_VTOR_TBLOFF_M   0xFFFFFF80U
 
#define SCB_VTOR_TBLOFF_S   7U
 
#define SCB_VTOR_RES0_W   7U
 
#define SCB_VTOR_RES0_M   0x0000007FU
 
#define SCB_VTOR_RES0_S   0U
 
#define SCB_AIRCR_VECTKEY_W   16U
 
#define SCB_AIRCR_VECTKEY_M   0xFFFF0000U
 
#define SCB_AIRCR_VECTKEY_S   16U
 
#define SCB_AIRCR_ENDIANESS   0x00008000U
 
#define SCB_AIRCR_ENDIANESS_M   0x00008000U
 
#define SCB_AIRCR_ENDIANESS_S   15U
 
#define SCB_AIRCR_PRIS   0x00004000U
 
#define SCB_AIRCR_PRIS_M   0x00004000U
 
#define SCB_AIRCR_PRIS_S   14U
 
#define SCB_AIRCR_BFHFNMINS   0x00002000U
 
#define SCB_AIRCR_BFHFNMINS_M   0x00002000U
 
#define SCB_AIRCR_BFHFNMINS_S   13U
 
#define SCB_AIRCR_PRIGROUP_W   3U
 
#define SCB_AIRCR_PRIGROUP_M   0x00000700U
 
#define SCB_AIRCR_PRIGROUP_S   8U
 
#define SCB_AIRCR_RES4_W   4U
 
#define SCB_AIRCR_RES4_M   0x000000F0U
 
#define SCB_AIRCR_RES4_S   4U
 
#define SCB_AIRCR_SYSRESETREQS   0x00000008U
 
#define SCB_AIRCR_SYSRESETREQS_M   0x00000008U
 
#define SCB_AIRCR_SYSRESETREQS_S   3U
 
#define SCB_AIRCR_SYSRESETREQ   0x00000004U
 
#define SCB_AIRCR_SYSRESETREQ_M   0x00000004U
 
#define SCB_AIRCR_SYSRESETREQ_S   2U
 
#define SCB_AIRCR_VECTCLRACTIVE   0x00000002U
 
#define SCB_AIRCR_VECTCLRACTIVE_M   0x00000002U
 
#define SCB_AIRCR_VECTCLRACTIVE_S   1U
 
#define SCB_AIRCR_RES0   0x00000001U
 
#define SCB_AIRCR_RES0_M   0x00000001U
 
#define SCB_AIRCR_RES0_S   0U
 
#define SCB_SCR_SEVONPEND   0x00000010U
 
#define SCB_SCR_SEVONPEND_M   0x00000010U
 
#define SCB_SCR_SEVONPEND_S   4U
 
#define SCB_SCR_SLEEPDEEPS   0x00000008U
 
#define SCB_SCR_SLEEPDEEPS_M   0x00000008U
 
#define SCB_SCR_SLEEPDEEPS_S   3U
 
#define SCB_SCR_SLEEPDEEP   0x00000004U
 
#define SCB_SCR_SLEEPDEEP_M   0x00000004U
 
#define SCB_SCR_SLEEPDEEP_S   2U
 
#define SCB_SCR_SLEEPONEXIT   0x00000002U
 
#define SCB_SCR_SLEEPONEXIT_M   0x00000002U
 
#define SCB_SCR_SLEEPONEXIT_S   1U
 
#define SCB_CCR_RES0_W   13U
 
#define SCB_CCR_RES0_M   0xFFF80000U
 
#define SCB_CCR_RES0_S   19U
 
#define SCB_CCR_BP   0x00040000U
 
#define SCB_CCR_BP_M   0x00040000U
 
#define SCB_CCR_BP_S   18U
 
#define SCB_CCR_IC   0x00020000U
 
#define SCB_CCR_IC_M   0x00020000U
 
#define SCB_CCR_IC_S   17U
 
#define SCB_CCR_DC   0x00010000U
 
#define SCB_CCR_DC_M   0x00010000U
 
#define SCB_CCR_DC_S   16U
 
#define SCB_CCR_RES0_1_W   5U
 
#define SCB_CCR_RES0_1_M   0x0000F800U
 
#define SCB_CCR_RES0_1_S   11U
 
#define SCB_CCR_STKOFHFNMIGN   0x00000400U
 
#define SCB_CCR_STKOFHFNMIGN_M   0x00000400U
 
#define SCB_CCR_STKOFHFNMIGN_S   10U
 
#define SCB_CCR_RES1   0x00000200U
 
#define SCB_CCR_RES1_M   0x00000200U
 
#define SCB_CCR_RES1_S   9U
 
#define SCB_CCR_BFHFNMIGN   0x00000100U
 
#define SCB_CCR_BFHFNMIGN_M   0x00000100U
 
#define SCB_CCR_BFHFNMIGN_S   8U
 
#define SCB_CCR_RES0_2_W   3U
 
#define SCB_CCR_RES0_2_M   0x000000E0U
 
#define SCB_CCR_RES0_2_S   5U
 
#define SCB_CCR_DIV_0_TRP   0x00000010U
 
#define SCB_CCR_DIV_0_TRP_M   0x00000010U
 
#define SCB_CCR_DIV_0_TRP_S   4U
 
#define SCB_CCR_UNALIGN_TRP   0x00000008U
 
#define SCB_CCR_UNALIGN_TRP_M   0x00000008U
 
#define SCB_CCR_UNALIGN_TRP_S   3U
 
#define SCB_CCR_RES0_3   0x00000004U
 
#define SCB_CCR_RES0_3_M   0x00000004U
 
#define SCB_CCR_RES0_3_S   2U
 
#define SCB_CCR_USERSETMPEND   0x00000002U
 
#define SCB_CCR_USERSETMPEND_M   0x00000002U
 
#define SCB_CCR_USERSETMPEND_S   1U
 
#define SCB_CCR_RES1_1   0x00000001U
 
#define SCB_CCR_RES1_1_M   0x00000001U
 
#define SCB_CCR_RES1_1_S   0U
 
#define SCB_SHPR1_PRI_7_W   8U
 
#define SCB_SHPR1_PRI_7_M   0xFF000000U
 
#define SCB_SHPR1_PRI_7_S   24U
 
#define SCB_SHPR1_PRI_6_W   8U
 
#define SCB_SHPR1_PRI_6_M   0x00FF0000U
 
#define SCB_SHPR1_PRI_6_S   16U
 
#define SCB_SHPR1_PRI_5_W   8U
 
#define SCB_SHPR1_PRI_5_M   0x0000FF00U
 
#define SCB_SHPR1_PRI_5_S   8U
 
#define SCB_SHPR1_PRI_4_W   8U
 
#define SCB_SHPR1_PRI_4_M   0x000000FFU
 
#define SCB_SHPR1_PRI_4_S   0U
 
#define SCB_SHPR2_PRI_11_W   8U
 
#define SCB_SHPR2_PRI_11_M   0xFF000000U
 
#define SCB_SHPR2_PRI_11_S   24U
 
#define SCB_SHPR2_RES0_W   24U
 
#define SCB_SHPR2_RES0_M   0x00FFFFFFU
 
#define SCB_SHPR2_RES0_S   0U
 
#define SCB_SHPR3_PRI_15_W   8U
 
#define SCB_SHPR3_PRI_15_M   0xFF000000U
 
#define SCB_SHPR3_PRI_15_S   24U
 
#define SCB_SHPR3_PRI_14_W   8U
 
#define SCB_SHPR3_PRI_14_M   0x00FF0000U
 
#define SCB_SHPR3_PRI_14_S   16U
 
#define SCB_SHPR3_RES0_0_W   16U
 
#define SCB_SHPR3_RES0_0_M   0x0000FFFFU
 
#define SCB_SHPR3_RES0_0_S   0U
 
#define SCB_SHCSR_RES0_W   10U
 
#define SCB_SHCSR_RES0_M   0xFFC00000U
 
#define SCB_SHCSR_RES0_S   22U
 
#define SCB_SHCSR_HARDFAULTPENDED   0x00200000U
 
#define SCB_SHCSR_HARDFAULTPENDED_M   0x00200000U
 
#define SCB_SHCSR_HARDFAULTPENDED_S   21U
 
#define SCB_SHCSR_SECUREFAULTPENDED   0x00100000U
 
#define SCB_SHCSR_SECUREFAULTPENDED_M   0x00100000U
 
#define SCB_SHCSR_SECUREFAULTPENDED_S   20U
 
#define SCB_SHCSR_SECUREFAULTENA   0x00080000U
 
#define SCB_SHCSR_SECUREFAULTENA_M   0x00080000U
 
#define SCB_SHCSR_SECUREFAULTENA_S   19U
 
#define SCB_SHCSR_USGFAULTENA   0x00040000U
 
#define SCB_SHCSR_USGFAULTENA_M   0x00040000U
 
#define SCB_SHCSR_USGFAULTENA_S   18U
 
#define SCB_SHCSR_BUSFAULTENA   0x00020000U
 
#define SCB_SHCSR_BUSFAULTENA_M   0x00020000U
 
#define SCB_SHCSR_BUSFAULTENA_S   17U
 
#define SCB_SHCSR_MEMFAULTENA   0x00010000U
 
#define SCB_SHCSR_MEMFAULTENA_M   0x00010000U
 
#define SCB_SHCSR_MEMFAULTENA_S   16U
 
#define SCB_SHCSR_SVCALLPENDED   0x00008000U
 
#define SCB_SHCSR_SVCALLPENDED_M   0x00008000U
 
#define SCB_SHCSR_SVCALLPENDED_S   15U
 
#define SCB_SHCSR_BUSFAULTPENDED   0x00004000U
 
#define SCB_SHCSR_BUSFAULTPENDED_M   0x00004000U
 
#define SCB_SHCSR_BUSFAULTPENDED_S   14U
 
#define SCB_SHCSR_MEMFAULTPENDED   0x00002000U
 
#define SCB_SHCSR_MEMFAULTPENDED_M   0x00002000U
 
#define SCB_SHCSR_MEMFAULTPENDED_S   13U
 
#define SCB_SHCSR_USGFAULTPENDED   0x00001000U
 
#define SCB_SHCSR_USGFAULTPENDED_M   0x00001000U
 
#define SCB_SHCSR_USGFAULTPENDED_S   12U
 
#define SCB_SHCSR_SYSTICKACT   0x00000800U
 
#define SCB_SHCSR_SYSTICKACT_M   0x00000800U
 
#define SCB_SHCSR_SYSTICKACT_S   11U
 
#define SCB_SHCSR_PENDSVACT   0x00000400U
 
#define SCB_SHCSR_PENDSVACT_M   0x00000400U
 
#define SCB_SHCSR_PENDSVACT_S   10U
 
#define SCB_SHCSR_RES0_1   0x00000200U
 
#define SCB_SHCSR_RES0_1_M   0x00000200U
 
#define SCB_SHCSR_RES0_1_S   9U
 
#define SCB_SHCSR_MONITORACT   0x00000100U
 
#define SCB_SHCSR_MONITORACT_M   0x00000100U
 
#define SCB_SHCSR_MONITORACT_S   8U
 
#define SCB_SHCSR_SVCALLACT   0x00000080U
 
#define SCB_SHCSR_SVCALLACT_M   0x00000080U
 
#define SCB_SHCSR_SVCALLACT_S   7U
 
#define SCB_SHCSR_RES0_2   0x00000040U
 
#define SCB_SHCSR_RES0_2_M   0x00000040U
 
#define SCB_SHCSR_RES0_2_S   6U
 
#define SCB_SHCSR_NMIACT   0x00000020U
 
#define SCB_SHCSR_NMIACT_M   0x00000020U
 
#define SCB_SHCSR_NMIACT_S   5U
 
#define SCB_SHCSR_SECUREFAULTACT   0x00000010U
 
#define SCB_SHCSR_SECUREFAULTACT_M   0x00000010U
 
#define SCB_SHCSR_SECUREFAULTACT_S   4U
 
#define SCB_SHCSR_USGFAULTACT   0x00000008U
 
#define SCB_SHCSR_USGFAULTACT_M   0x00000008U
 
#define SCB_SHCSR_USGFAULTACT_S   3U
 
#define SCB_SHCSR_HARDFAULTACT   0x00000004U
 
#define SCB_SHCSR_HARDFAULTACT_M   0x00000004U
 
#define SCB_SHCSR_HARDFAULTACT_S   2U
 
#define SCB_SHCSR_BUSFAULTACT   0x00000002U
 
#define SCB_SHCSR_BUSFAULTACT_M   0x00000002U
 
#define SCB_SHCSR_BUSFAULTACT_S   1U
 
#define SCB_SHCSR_MEMFAULTACT   0x00000001U
 
#define SCB_SHCSR_MEMFAULTACT_M   0x00000001U
 
#define SCB_SHCSR_MEMFAULTACT_S   0U
 
#define SCB_CFSR_RES0_3_W   6U
 
#define SCB_CFSR_RES0_3_M   0xFC000000U
 
#define SCB_CFSR_RES0_3_S   26U
 
#define SCB_CFSR_DIVBYZERO   0x02000000U
 
#define SCB_CFSR_DIVBYZERO_M   0x02000000U
 
#define SCB_CFSR_DIVBYZERO_S   25U
 
#define SCB_CFSR_UNALIGNED   0x01000000U
 
#define SCB_CFSR_UNALIGNED_M   0x01000000U
 
#define SCB_CFSR_UNALIGNED_S   24U
 
#define SCB_CFSR_RES0_1_2_W   3U
 
#define SCB_CFSR_RES0_1_2_M   0x00E00000U
 
#define SCB_CFSR_RES0_1_2_S   21U
 
#define SCB_CFSR_STKOF   0x00100000U
 
#define SCB_CFSR_STKOF_M   0x00100000U
 
#define SCB_CFSR_STKOF_S   20U
 
#define SCB_CFSR_NOCP   0x00080000U
 
#define SCB_CFSR_NOCP_M   0x00080000U
 
#define SCB_CFSR_NOCP_S   19U
 
#define SCB_CFSR_INVPC   0x00040000U
 
#define SCB_CFSR_INVPC_M   0x00040000U
 
#define SCB_CFSR_INVPC_S   18U
 
#define SCB_CFSR_INVSTATE   0x00020000U
 
#define SCB_CFSR_INVSTATE_M   0x00020000U
 
#define SCB_CFSR_INVSTATE_S   17U
 
#define SCB_CFSR_UNDEFINSTR   0x00010000U
 
#define SCB_CFSR_UNDEFINSTR_M   0x00010000U
 
#define SCB_CFSR_UNDEFINSTR_S   16U
 
#define SCB_CFSR_BFARVALID   0x00008000U
 
#define SCB_CFSR_BFARVALID_M   0x00008000U
 
#define SCB_CFSR_BFARVALID_S   15U
 
#define SCB_CFSR_RES0_2   0x00004000U
 
#define SCB_CFSR_RES0_2_M   0x00004000U
 
#define SCB_CFSR_RES0_2_S   14U
 
#define SCB_CFSR_LSPERR   0x00002000U
 
#define SCB_CFSR_LSPERR_M   0x00002000U
 
#define SCB_CFSR_LSPERR_S   13U
 
#define SCB_CFSR_STKERR   0x00001000U
 
#define SCB_CFSR_STKERR_M   0x00001000U
 
#define SCB_CFSR_STKERR_S   12U
 
#define SCB_CFSR_UNSTKERR   0x00000800U
 
#define SCB_CFSR_UNSTKERR_M   0x00000800U
 
#define SCB_CFSR_UNSTKERR_S   11U
 
#define SCB_CFSR_IMPRECISERR   0x00000400U
 
#define SCB_CFSR_IMPRECISERR_M   0x00000400U
 
#define SCB_CFSR_IMPRECISERR_S   10U
 
#define SCB_CFSR_PRECISERR   0x00000200U
 
#define SCB_CFSR_PRECISERR_M   0x00000200U
 
#define SCB_CFSR_PRECISERR_S   9U
 
#define SCB_CFSR_IBUSERR   0x00000100U
 
#define SCB_CFSR_IBUSERR_M   0x00000100U
 
#define SCB_CFSR_IBUSERR_S   8U
 
#define SCB_CFSR_MMARVALID   0x00000080U
 
#define SCB_CFSR_MMARVALID_M   0x00000080U
 
#define SCB_CFSR_MMARVALID_S   7U
 
#define SCB_CFSR_RES0   0x00000040U
 
#define SCB_CFSR_RES0_M   0x00000040U
 
#define SCB_CFSR_RES0_S   6U
 
#define SCB_CFSR_MLSPERR   0x00000020U
 
#define SCB_CFSR_MLSPERR_M   0x00000020U
 
#define SCB_CFSR_MLSPERR_S   5U
 
#define SCB_CFSR_MSTKERR   0x00000010U
 
#define SCB_CFSR_MSTKERR_M   0x00000010U
 
#define SCB_CFSR_MSTKERR_S   4U
 
#define SCB_CFSR_MUNSTKERR   0x00000008U
 
#define SCB_CFSR_MUNSTKERR_M   0x00000008U
 
#define SCB_CFSR_MUNSTKERR_S   3U
 
#define SCB_CFSR_RES0_1   0x00000004U
 
#define SCB_CFSR_RES0_1_M   0x00000004U
 
#define SCB_CFSR_RES0_1_S   2U
 
#define SCB_CFSR_DACCVIOL   0x00000002U
 
#define SCB_CFSR_DACCVIOL_M   0x00000002U
 
#define SCB_CFSR_DACCVIOL_S   1U
 
#define SCB_CFSR_IACCVIOL   0x00000001U
 
#define SCB_CFSR_IACCVIOL_M   0x00000001U
 
#define SCB_CFSR_IACCVIOL_S   0U
 
#define SCB_HFSR_DEBUGEVT   0x80000000U
 
#define SCB_HFSR_DEBUGEVT_M   0x80000000U
 
#define SCB_HFSR_DEBUGEVT_S   31U
 
#define SCB_HFSR_FORCED   0x40000000U
 
#define SCB_HFSR_FORCED_M   0x40000000U
 
#define SCB_HFSR_FORCED_S   30U
 
#define SCB_HFSR_RES0_W   28U
 
#define SCB_HFSR_RES0_M   0x3FFFFFFCU
 
#define SCB_HFSR_RES0_S   2U
 
#define SCB_HFSR_VECTTBL   0x00000002U
 
#define SCB_HFSR_VECTTBL_M   0x00000002U
 
#define SCB_HFSR_VECTTBL_S   1U
 
#define SCB_HFSR_RES0_1   0x00000001U
 
#define SCB_HFSR_RES0_1_M   0x00000001U
 
#define SCB_HFSR_RES0_1_S   0U
 
#define SCB_DFSR_RES0_W   27U
 
#define SCB_DFSR_RES0_M   0xFFFFFFE0U
 
#define SCB_DFSR_RES0_S   5U
 
#define SCB_DFSR_EXTERNAL   0x00000010U
 
#define SCB_DFSR_EXTERNAL_M   0x00000010U
 
#define SCB_DFSR_EXTERNAL_S   4U
 
#define SCB_DFSR_VCATCH   0x00000008U
 
#define SCB_DFSR_VCATCH_M   0x00000008U
 
#define SCB_DFSR_VCATCH_S   3U
 
#define SCB_DFSR_DWTTRAP   0x00000004U
 
#define SCB_DFSR_DWTTRAP_M   0x00000004U
 
#define SCB_DFSR_DWTTRAP_S   2U
 
#define SCB_DFSR_BKPT   0x00000002U
 
#define SCB_DFSR_BKPT_M   0x00000002U
 
#define SCB_DFSR_BKPT_S   1U
 
#define SCB_DFSR_HALTED   0x00000001U
 
#define SCB_DFSR_HALTED_M   0x00000001U
 
#define SCB_DFSR_HALTED_S   0U
 
#define SCB_MMFAR_ADDRESS_W   32U
 
#define SCB_MMFAR_ADDRESS_M   0xFFFFFFFFU
 
#define SCB_MMFAR_ADDRESS_S   0U
 
#define SCB_BFAR_ADDRESS_W   32U
 
#define SCB_BFAR_ADDRESS_M   0xFFFFFFFFU
 
#define SCB_BFAR_ADDRESS_S   0U
 
#define SCB_AFSR_IMPDEF   0x00000001U
 
#define SCB_AFSR_IMPDEF_M   0x00000001U
 
#define SCB_AFSR_IMPDEF_S   0U
 
#define SCB_ID_PFR0_RES0_W   24U
 
#define SCB_ID_PFR0_RES0_M   0xFFFFFF00U
 
#define SCB_ID_PFR0_RES0_S   8U
 
#define SCB_ID_PFR0_STATE1_W   4U
 
#define SCB_ID_PFR0_STATE1_M   0x000000F0U
 
#define SCB_ID_PFR0_STATE1_S   4U
 
#define SCB_ID_PFR0_STATE0_W   4U
 
#define SCB_ID_PFR0_STATE0_M   0x0000000FU
 
#define SCB_ID_PFR0_STATE0_S   0U
 
#define SCB_ID_PFR1_RES0_W   20U
 
#define SCB_ID_PFR1_RES0_M   0xFFFFF000U
 
#define SCB_ID_PFR1_RES0_S   12U
 
#define SCB_ID_PFR1_MPROGMOD_W   4U
 
#define SCB_ID_PFR1_MPROGMOD_M   0x00000F00U
 
#define SCB_ID_PFR1_MPROGMOD_S   8U
 
#define SCB_ID_PFR1_SECURITY_W   4U
 
#define SCB_ID_PFR1_SECURITY_M   0x000000F0U
 
#define SCB_ID_PFR1_SECURITY_S   4U
 
#define SCB_ID_PFR1_RES0_1_W   4U
 
#define SCB_ID_PFR1_RES0_1_M   0x0000000FU
 
#define SCB_ID_PFR1_RES0_1_S   0U
 
#define SCB_ID_DFR0_RES0_W   8U
 
#define SCB_ID_DFR0_RES0_M   0xFF000000U
 
#define SCB_ID_DFR0_RES0_S   24U
 
#define SCB_ID_DFR0_MPROFDBG_W   4U
 
#define SCB_ID_DFR0_MPROFDBG_M   0x00F00000U
 
#define SCB_ID_DFR0_MPROFDBG_S   20U
 
#define SCB_ID_DFR0_RES0_1_W   20U
 
#define SCB_ID_DFR0_RES0_1_M   0x000FFFFFU
 
#define SCB_ID_DFR0_RES0_1_S   0U
 
#define SCB_ID_AFR0_RES0_W   16U
 
#define SCB_ID_AFR0_RES0_M   0xFFFF0000U
 
#define SCB_ID_AFR0_RES0_S   16U
 
#define SCB_ID_AFR0_IMPDEF3_W   4U
 
#define SCB_ID_AFR0_IMPDEF3_M   0x0000F000U
 
#define SCB_ID_AFR0_IMPDEF3_S   12U
 
#define SCB_ID_AFR0_IMPDEF2_W   4U
 
#define SCB_ID_AFR0_IMPDEF2_M   0x00000F00U
 
#define SCB_ID_AFR0_IMPDEF2_S   8U
 
#define SCB_ID_AFR0_IMPDEF1_W   4U
 
#define SCB_ID_AFR0_IMPDEF1_M   0x000000F0U
 
#define SCB_ID_AFR0_IMPDEF1_S   4U
 
#define SCB_ID_AFR0_IMPDEF0_W   4U
 
#define SCB_ID_AFR0_IMPDEF0_M   0x0000000FU
 
#define SCB_ID_AFR0_IMPDEF0_S   0U
 
#define SCB_ID_MMFR0_RES0_W   8U
 
#define SCB_ID_MMFR0_RES0_M   0xFF000000U
 
#define SCB_ID_MMFR0_RES0_S   24U
 
#define SCB_ID_MMFR0_AUXREG_W   4U
 
#define SCB_ID_MMFR0_AUXREG_M   0x00F00000U
 
#define SCB_ID_MMFR0_AUXREG_S   20U
 
#define SCB_ID_MMFR0_TCM_W   4U
 
#define SCB_ID_MMFR0_TCM_M   0x000F0000U
 
#define SCB_ID_MMFR0_TCM_S   16U
 
#define SCB_ID_MMFR0_SHARELVL_W   4U
 
#define SCB_ID_MMFR0_SHARELVL_M   0x0000F000U
 
#define SCB_ID_MMFR0_SHARELVL_S   12U
 
#define SCB_ID_MMFR0_OUTERSHR_W   4U
 
#define SCB_ID_MMFR0_OUTERSHR_M   0x00000F00U
 
#define SCB_ID_MMFR0_OUTERSHR_S   8U
 
#define SCB_ID_MMFR0_PMSA_W   4U
 
#define SCB_ID_MMFR0_PMSA_M   0x000000F0U
 
#define SCB_ID_MMFR0_PMSA_S   4U
 
#define SCB_ID_MMFR0_RES0_1_W   4U
 
#define SCB_ID_MMFR0_RES0_1_M   0x0000000FU
 
#define SCB_ID_MMFR0_RES0_1_S   0U
 
#define SCB_ID_MMFR1_RES0_W   32U
 
#define SCB_ID_MMFR1_RES0_M   0xFFFFFFFFU
 
#define SCB_ID_MMFR1_RES0_S   0U
 
#define SCB_ID_MMFR2_RES0_W   4U
 
#define SCB_ID_MMFR2_RES0_M   0xF0000000U
 
#define SCB_ID_MMFR2_RES0_S   28U
 
#define SCB_ID_MMFR2_WFISTALL_W   4U
 
#define SCB_ID_MMFR2_WFISTALL_M   0x0F000000U
 
#define SCB_ID_MMFR2_WFISTALL_S   24U
 
#define SCB_ID_MMFR2_RES0_1_W   24U
 
#define SCB_ID_MMFR2_RES0_1_M   0x00FFFFFFU
 
#define SCB_ID_MMFR2_RES0_1_S   0U
 
#define SCB_ID_MMFR3_RES0_W   20U
 
#define SCB_ID_MMFR3_RES0_M   0xFFFFF000U
 
#define SCB_ID_MMFR3_RES0_S   12U
 
#define SCB_ID_MMFR3_BPMAINT_W   4U
 
#define SCB_ID_MMFR3_BPMAINT_M   0x00000F00U
 
#define SCB_ID_MMFR3_BPMAINT_S   8U
 
#define SCB_ID_MMFR3_CMAINTSW_W   4U
 
#define SCB_ID_MMFR3_CMAINTSW_M   0x000000F0U
 
#define SCB_ID_MMFR3_CMAINTSW_S   4U
 
#define SCB_ID_MMFR3_CMAINTVA_W   4U
 
#define SCB_ID_MMFR3_CMAINTVA_M   0x0000000FU
 
#define SCB_ID_MMFR3_CMAINTVA_S   0U
 
#define SCB_ID_ISAR0_RES0_W   4U
 
#define SCB_ID_ISAR0_RES0_M   0xF0000000U
 
#define SCB_ID_ISAR0_RES0_S   28U
 
#define SCB_ID_ISAR0_DIVIDE_W   4U
 
#define SCB_ID_ISAR0_DIVIDE_M   0x0F000000U
 
#define SCB_ID_ISAR0_DIVIDE_S   24U
 
#define SCB_ID_ISAR0_DEBUG_W   4U
 
#define SCB_ID_ISAR0_DEBUG_M   0x00F00000U
 
#define SCB_ID_ISAR0_DEBUG_S   20U
 
#define SCB_ID_ISAR0_COPROC_W   4U
 
#define SCB_ID_ISAR0_COPROC_M   0x000F0000U
 
#define SCB_ID_ISAR0_COPROC_S   16U
 
#define SCB_ID_ISAR0_CMPBRANCH_W   4U
 
#define SCB_ID_ISAR0_CMPBRANCH_M   0x0000F000U
 
#define SCB_ID_ISAR0_CMPBRANCH_S   12U
 
#define SCB_ID_ISAR0_BITFIELD_W   4U
 
#define SCB_ID_ISAR0_BITFIELD_M   0x00000F00U
 
#define SCB_ID_ISAR0_BITFIELD_S   8U
 
#define SCB_ID_ISAR0_BITCOUNT_W   4U
 
#define SCB_ID_ISAR0_BITCOUNT_M   0x000000F0U
 
#define SCB_ID_ISAR0_BITCOUNT_S   4U
 
#define SCB_ID_ISAR0_RES0_1_W   4U
 
#define SCB_ID_ISAR0_RES0_1_M   0x0000000FU
 
#define SCB_ID_ISAR0_RES0_1_S   0U
 
#define SCB_ID_ISAR1_RES0_W   4U
 
#define SCB_ID_ISAR1_RES0_M   0xF0000000U
 
#define SCB_ID_ISAR1_RES0_S   28U
 
#define SCB_ID_ISAR1_INTERWORK_W   4U
 
#define SCB_ID_ISAR1_INTERWORK_M   0x0F000000U
 
#define SCB_ID_ISAR1_INTERWORK_S   24U
 
#define SCB_ID_ISAR1_IMMEDIATE_W   4U
 
#define SCB_ID_ISAR1_IMMEDIATE_M   0x00F00000U
 
#define SCB_ID_ISAR1_IMMEDIATE_S   20U
 
#define SCB_ID_ISAR1_IFTHEN_W   4U
 
#define SCB_ID_ISAR1_IFTHEN_M   0x000F0000U
 
#define SCB_ID_ISAR1_IFTHEN_S   16U
 
#define SCB_ID_ISAR1_EXTEND_W   4U
 
#define SCB_ID_ISAR1_EXTEND_M   0x0000F000U
 
#define SCB_ID_ISAR1_EXTEND_S   12U
 
#define SCB_ID_ISAR1_RES0_1_W   12U
 
#define SCB_ID_ISAR1_RES0_1_M   0x00000FFFU
 
#define SCB_ID_ISAR1_RES0_1_S   0U
 
#define SCB_ID_ISAR2_REVERSAL_W   4U
 
#define SCB_ID_ISAR2_REVERSAL_M   0xF0000000U
 
#define SCB_ID_ISAR2_REVERSAL_S   28U
 
#define SCB_ID_ISAR2_RES0_W   4U
 
#define SCB_ID_ISAR2_RES0_M   0x0F000000U
 
#define SCB_ID_ISAR2_RES0_S   24U
 
#define SCB_ID_ISAR2_MULTU_W   4U
 
#define SCB_ID_ISAR2_MULTU_M   0x00F00000U
 
#define SCB_ID_ISAR2_MULTU_S   20U
 
#define SCB_ID_ISAR2_MULTS_W   4U
 
#define SCB_ID_ISAR2_MULTS_M   0x000F0000U
 
#define SCB_ID_ISAR2_MULTS_S   16U
 
#define SCB_ID_ISAR2_MULT_W   4U
 
#define SCB_ID_ISAR2_MULT_M   0x0000F000U
 
#define SCB_ID_ISAR2_MULT_S   12U
 
#define SCB_ID_ISAR2_MULTIACCESSINT_W   4U
 
#define SCB_ID_ISAR2_MULTIACCESSINT_M   0x00000F00U
 
#define SCB_ID_ISAR2_MULTIACCESSINT_S   8U
 
#define SCB_ID_ISAR2_MEMHINT_W   4U
 
#define SCB_ID_ISAR2_MEMHINT_M   0x000000F0U
 
#define SCB_ID_ISAR2_MEMHINT_S   4U
 
#define SCB_ID_ISAR2_LOADSTORE_W   4U
 
#define SCB_ID_ISAR2_LOADSTORE_M   0x0000000FU
 
#define SCB_ID_ISAR2_LOADSTORE_S   0U
 
#define SCB_ID_ISAR3_RES0_W   4U
 
#define SCB_ID_ISAR3_RES0_M   0xF0000000U
 
#define SCB_ID_ISAR3_RES0_S   28U
 
#define SCB_ID_ISAR3_TRUENOP_W   4U
 
#define SCB_ID_ISAR3_TRUENOP_M   0x0F000000U
 
#define SCB_ID_ISAR3_TRUENOP_S   24U
 
#define SCB_ID_ISAR3_T32COPY_W   4U
 
#define SCB_ID_ISAR3_T32COPY_M   0x00F00000U
 
#define SCB_ID_ISAR3_T32COPY_S   20U
 
#define SCB_ID_ISAR3_TABBRANCH_W   4U
 
#define SCB_ID_ISAR3_TABBRANCH_M   0x000F0000U
 
#define SCB_ID_ISAR3_TABBRANCH_S   16U
 
#define SCB_ID_ISAR3_SYNCHPRIM_W   4U
 
#define SCB_ID_ISAR3_SYNCHPRIM_M   0x0000F000U
 
#define SCB_ID_ISAR3_SYNCHPRIM_S   12U
 
#define SCB_ID_ISAR3_SVC_W   4U
 
#define SCB_ID_ISAR3_SVC_M   0x00000F00U
 
#define SCB_ID_ISAR3_SVC_S   8U
 
#define SCB_ID_ISAR3_SIMD_W   4U
 
#define SCB_ID_ISAR3_SIMD_M   0x000000F0U
 
#define SCB_ID_ISAR3_SIMD_S   4U
 
#define SCB_ID_ISAR3_SATURATE_W   4U
 
#define SCB_ID_ISAR3_SATURATE_M   0x0000000FU
 
#define SCB_ID_ISAR3_SATURATE_S   0U
 
#define SCB_ID_ISAR4_RES0_W   4U
 
#define SCB_ID_ISAR4_RES0_M   0xF0000000U
 
#define SCB_ID_ISAR4_RES0_S   28U
 
#define SCB_ID_ISAR4_PSR_M_W   4U
 
#define SCB_ID_ISAR4_PSR_M_M   0x0F000000U
 
#define SCB_ID_ISAR4_PSR_M_S   24U
 
#define SCB_ID_ISAR4_SYNCPRIM_FRAC_W   4U
 
#define SCB_ID_ISAR4_SYNCPRIM_FRAC_M   0x00F00000U
 
#define SCB_ID_ISAR4_SYNCPRIM_FRAC_S   20U
 
#define SCB_ID_ISAR4_BARRIER_W   4U
 
#define SCB_ID_ISAR4_BARRIER_M   0x000F0000U
 
#define SCB_ID_ISAR4_BARRIER_S   16U
 
#define SCB_ID_ISAR4_RES0_1_W   4U
 
#define SCB_ID_ISAR4_RES0_1_M   0x0000F000U
 
#define SCB_ID_ISAR4_RES0_1_S   12U
 
#define SCB_ID_ISAR4_WRITEBACK_W   4U
 
#define SCB_ID_ISAR4_WRITEBACK_M   0x00000F00U
 
#define SCB_ID_ISAR4_WRITEBACK_S   8U
 
#define SCB_ID_ISAR4_WITHSHIFTS_W   4U
 
#define SCB_ID_ISAR4_WITHSHIFTS_M   0x000000F0U
 
#define SCB_ID_ISAR4_WITHSHIFTS_S   4U
 
#define SCB_ID_ISAR4_UNPRIV_W   4U
 
#define SCB_ID_ISAR4_UNPRIV_M   0x0000000FU
 
#define SCB_ID_ISAR4_UNPRIV_S   0U
 
#define SCB_ID_ISAR5_RES0_W   32U
 
#define SCB_ID_ISAR5_RES0_M   0xFFFFFFFFU
 
#define SCB_ID_ISAR5_RES0_S   0U
 
#define SCB_CLIDR_ICB_W   2U
 
#define SCB_CLIDR_ICB_M   0xC0000000U
 
#define SCB_CLIDR_ICB_S   30U
 
#define SCB_CLIDR_ICB_L3   0xC0000000U
 
#define SCB_CLIDR_ICB_L2   0x80000000U
 
#define SCB_CLIDR_ICB_L1   0x40000000U
 
#define SCB_CLIDR_ICB_NA   0x00000000U
 
#define SCB_CLIDR_LOUU_W   3U
 
#define SCB_CLIDR_LOUU_M   0x38000000U
 
#define SCB_CLIDR_LOUU_S   27U
 
#define SCB_CLIDR_LOC_W   3U
 
#define SCB_CLIDR_LOC_M   0x07000000U
 
#define SCB_CLIDR_LOC_S   24U
 
#define SCB_CLIDR_LOUIS_W   3U
 
#define SCB_CLIDR_LOUIS_M   0x00E00000U
 
#define SCB_CLIDR_LOUIS_S   21U
 
#define SCB_CLIDR_CTYPE7_W   3U
 
#define SCB_CLIDR_CTYPE7_M   0x001C0000U
 
#define SCB_CLIDR_CTYPE7_S   18U
 
#define SCB_CLIDR_CTYPE7_BOTH_UNIFIED   0x00100000U
 
#define SCB_CLIDR_CTYPE7_BOTH_SEP   0x000C0000U
 
#define SCB_CLIDR_CTYPE7_DATA   0x00080000U
 
#define SCB_CLIDR_CTYPE7_INSTR   0x00040000U
 
#define SCB_CLIDR_CTYPE7_NO_CACHE   0x00000000U
 
#define SCB_CLIDR_CTYPE6_W   3U
 
#define SCB_CLIDR_CTYPE6_M   0x00038000U
 
#define SCB_CLIDR_CTYPE6_S   15U
 
#define SCB_CLIDR_CTYPE6_BOTH_UNIFIED   0x00020000U
 
#define SCB_CLIDR_CTYPE6_BOTH_SEP   0x00018000U
 
#define SCB_CLIDR_CTYPE6_DATA   0x00010000U
 
#define SCB_CLIDR_CTYPE6_INSTR   0x00008000U
 
#define SCB_CLIDR_CTYPE6_NO_CACHE   0x00000000U
 
#define SCB_CLIDR_CTYPE5_W   3U
 
#define SCB_CLIDR_CTYPE5_M   0x00007000U
 
#define SCB_CLIDR_CTYPE5_S   12U
 
#define SCB_CLIDR_CTYPE5_BOTH_UNIFIED   0x00004000U
 
#define SCB_CLIDR_CTYPE5_BOTH_SEP   0x00003000U
 
#define SCB_CLIDR_CTYPE5_DATA   0x00002000U
 
#define SCB_CLIDR_CTYPE5_INSTR   0x00001000U
 
#define SCB_CLIDR_CTYPE5_NO_CACHE   0x00000000U
 
#define SCB_CLIDR_CTYPE4_W   3U
 
#define SCB_CLIDR_CTYPE4_M   0x00000E00U
 
#define SCB_CLIDR_CTYPE4_S   9U
 
#define SCB_CLIDR_CTYPE4_BOTH_UNIFIED   0x00000800U
 
#define SCB_CLIDR_CTYPE4_BOTH_SEP   0x00000600U
 
#define SCB_CLIDR_CTYPE4_DATA   0x00000400U
 
#define SCB_CLIDR_CTYPE4_INSTR   0x00000200U
 
#define SCB_CLIDR_CTYPE4_NO_CACHE   0x00000000U
 
#define SCB_CLIDR_CTYPE3_W   3U
 
#define SCB_CLIDR_CTYPE3_M   0x000001C0U
 
#define SCB_CLIDR_CTYPE3_S   6U
 
#define SCB_CLIDR_CTYPE3_BOTH_UNIFIED   0x00000100U
 
#define SCB_CLIDR_CTYPE3_BOTH_SEP   0x000000C0U
 
#define SCB_CLIDR_CTYPE3_DATA   0x00000080U
 
#define SCB_CLIDR_CTYPE3_INSTR   0x00000040U
 
#define SCB_CLIDR_CTYPE3_NO_CACHE   0x00000000U
 
#define SCB_CLIDR_CTYPE2_W   3U
 
#define SCB_CLIDR_CTYPE2_M   0x00000038U
 
#define SCB_CLIDR_CTYPE2_S   3U
 
#define SCB_CLIDR_CTYPE2_BOTH_UNIFIED   0x00000020U
 
#define SCB_CLIDR_CTYPE2_BOTH_SEP   0x00000018U
 
#define SCB_CLIDR_CTYPE2_DATA   0x00000010U
 
#define SCB_CLIDR_CTYPE2_INSTR   0x00000008U
 
#define SCB_CLIDR_CTYPE2_NO_CACHE   0x00000000U
 
#define SCB_CLIDR_CTYPE1_W   3U
 
#define SCB_CLIDR_CTYPE1_M   0x00000007U
 
#define SCB_CLIDR_CTYPE1_S   0U
 
#define SCB_CLIDR_CTYPE1_BOTH_UNIFIED   0x00000004U
 
#define SCB_CLIDR_CTYPE1_BOTH_SEP   0x00000003U
 
#define SCB_CLIDR_CTYPE1_DATA   0x00000002U
 
#define SCB_CLIDR_CTYPE1_INSTR   0x00000001U
 
#define SCB_CLIDR_CTYPE1_NO_CACHE   0x00000000U
 
#define SCB_CTR_RES1   0x80000000U
 
#define SCB_CTR_RES1_M   0x80000000U
 
#define SCB_CTR_RES1_S   31U
 
#define SCB_CTR_RES0_W   3U
 
#define SCB_CTR_RES0_M   0x70000000U
 
#define SCB_CTR_RES0_S   28U
 
#define SCB_CTR_CWG_W   4U
 
#define SCB_CTR_CWG_M   0x0F000000U
 
#define SCB_CTR_CWG_S   24U
 
#define SCB_CTR_ERG_W   4U
 
#define SCB_CTR_ERG_M   0x00F00000U
 
#define SCB_CTR_ERG_S   20U
 
#define SCB_CTR_DMINLINE_W   4U
 
#define SCB_CTR_DMINLINE_M   0x000F0000U
 
#define SCB_CTR_DMINLINE_S   16U
 
#define SCB_CTR_RES1_1_W   2U
 
#define SCB_CTR_RES1_1_M   0x0000C000U
 
#define SCB_CTR_RES1_1_S   14U
 
#define SCB_CTR_RES0_1_W   10U
 
#define SCB_CTR_RES0_1_M   0x00003FF0U
 
#define SCB_CTR_RES0_1_S   4U
 
#define SCB_CTR_IMINLINE_W   4U
 
#define SCB_CTR_IMINLINE_M   0x0000000FU
 
#define SCB_CTR_IMINLINE_S   0U
 
#define SCB_CCSIDR_WT   0x80000000U
 
#define SCB_CCSIDR_WT_M   0x80000000U
 
#define SCB_CCSIDR_WT_S   31U
 
#define SCB_CCSIDR_WT_SUPPORTED   0x80000000U
 
#define SCB_CCSIDR_WT_NOT_SUPPORTED   0x00000000U
 
#define SCB_CCSIDR_WB   0x40000000U
 
#define SCB_CCSIDR_WB_M   0x40000000U
 
#define SCB_CCSIDR_WB_S   30U
 
#define SCB_CCSIDR_WB_SUPPORTED   0x40000000U
 
#define SCB_CCSIDR_WB_NOT_SUPPORTED   0x00000000U
 
#define SCB_CCSIDR_RA   0x20000000U
 
#define SCB_CCSIDR_RA_M   0x20000000U
 
#define SCB_CCSIDR_RA_S   29U
 
#define SCB_CCSIDR_RA_SUPPORTED   0x20000000U
 
#define SCB_CCSIDR_RA_NOT_SUPPORTED   0x00000000U
 
#define SCB_CCSIDR_WA   0x10000000U
 
#define SCB_CCSIDR_WA_M   0x10000000U
 
#define SCB_CCSIDR_WA_S   28U
 
#define SCB_CCSIDR_WA_SUPPORTED   0x10000000U
 
#define SCB_CCSIDR_WA_NOT_SUPPORTED   0x00000000U
 
#define SCB_CCSIDR_NUMSETS_W   15U
 
#define SCB_CCSIDR_NUMSETS_M   0x0FFFE000U
 
#define SCB_CCSIDR_NUMSETS_S   13U
 
#define SCB_CCSIDR_ASSOCIATIVITY_W   10U
 
#define SCB_CCSIDR_ASSOCIATIVITY_M   0x00001FF8U
 
#define SCB_CCSIDR_ASSOCIATIVITY_S   3U
 
#define SCB_CCSIDR_LINESIZE_W   3U
 
#define SCB_CCSIDR_LINESIZE_M   0x00000007U
 
#define SCB_CCSIDR_LINESIZE_S   0U
 
#define SCB_CSSELR_RES0_W   28U
 
#define SCB_CSSELR_RES0_M   0xFFFFFFF0U
 
#define SCB_CSSELR_RES0_S   4U
 
#define SCB_CSSELR_LEVEL_W   3U
 
#define SCB_CSSELR_LEVEL_M   0x0000000EU
 
#define SCB_CSSELR_LEVEL_S   1U
 
#define SCB_CSSELR_LEVEL_L7   0x0000000CU
 
#define SCB_CSSELR_LEVEL_L6   0x0000000AU
 
#define SCB_CSSELR_LEVEL_L5   0x00000008U
 
#define SCB_CSSELR_LEVEL_L4   0x00000006U
 
#define SCB_CSSELR_LEVEL_L3   0x00000004U
 
#define SCB_CSSELR_LEVEL_L2   0x00000002U
 
#define SCB_CSSELR_LEVEL_L1   0x00000000U
 
#define SCB_CSSELR_IND   0x00000001U
 
#define SCB_CSSELR_IND_M   0x00000001U
 
#define SCB_CSSELR_IND_S   0U
 
#define SCB_CSSELR_IND_INSTR   0x00000001U
 
#define SCB_CSSELR_IND_DATA   0x00000000U
 
#define SCB_CPACR_RES0_W   8U
 
#define SCB_CPACR_RES0_M   0xFF000000U
 
#define SCB_CPACR_RES0_S   24U
 
#define SCB_CPACR_CP11_W   2U
 
#define SCB_CPACR_CP11_M   0x00C00000U
 
#define SCB_CPACR_CP11_S   22U
 
#define SCB_CPACR_CP10_W   2U
 
#define SCB_CPACR_CP10_M   0x00300000U
 
#define SCB_CPACR_CP10_S   20U
 
#define SCB_CPACR_RES0_1_W   4U
 
#define SCB_CPACR_RES0_1_M   0x000F0000U
 
#define SCB_CPACR_RES0_1_S   16U
 
#define SCB_CPACR_CP7_W   2U
 
#define SCB_CPACR_CP7_M   0x0000C000U
 
#define SCB_CPACR_CP7_S   14U
 
#define SCB_CPACR_CP6_W   2U
 
#define SCB_CPACR_CP6_M   0x00003000U
 
#define SCB_CPACR_CP6_S   12U
 
#define SCB_CPACR_CP5_W   2U
 
#define SCB_CPACR_CP5_M   0x00000C00U
 
#define SCB_CPACR_CP5_S   10U
 
#define SCB_CPACR_CP4_W   2U
 
#define SCB_CPACR_CP4_M   0x00000300U
 
#define SCB_CPACR_CP4_S   8U
 
#define SCB_CPACR_CP3_W   2U
 
#define SCB_CPACR_CP3_M   0x000000C0U
 
#define SCB_CPACR_CP3_S   6U
 
#define SCB_CPACR_CP2_W   2U
 
#define SCB_CPACR_CP2_M   0x00000030U
 
#define SCB_CPACR_CP2_S   4U
 
#define SCB_CPACR_CP1_W   2U
 
#define SCB_CPACR_CP1_M   0x0000000CU
 
#define SCB_CPACR_CP1_S   2U
 
#define SCB_CPACR_CP0_W   2U
 
#define SCB_CPACR_CP0_M   0x00000003U
 
#define SCB_CPACR_CP0_S   0U
 
#define SCB_NSACR_RES0_W   20U
 
#define SCB_NSACR_RES0_M   0xFFFFF000U
 
#define SCB_NSACR_RES0_S   12U
 
#define SCB_NSACR_CP11   0x00000800U
 
#define SCB_NSACR_CP11_M   0x00000800U
 
#define SCB_NSACR_CP11_S   11U
 
#define SCB_NSACR_CP10   0x00000400U
 
#define SCB_NSACR_CP10_M   0x00000400U
 
#define SCB_NSACR_CP10_S   10U
 
#define SCB_NSACR_RES0_1_W   2U
 
#define SCB_NSACR_RES0_1_M   0x00000300U
 
#define SCB_NSACR_RES0_1_S   8U
 
#define SCB_NSACR_CP7   0x00000080U
 
#define SCB_NSACR_CP7_M   0x00000080U
 
#define SCB_NSACR_CP7_S   7U
 
#define SCB_NSACR_CP6   0x00000040U
 
#define SCB_NSACR_CP6_M   0x00000040U
 
#define SCB_NSACR_CP6_S   6U
 
#define SCB_NSACR_CP5   0x00000020U
 
#define SCB_NSACR_CP5_M   0x00000020U
 
#define SCB_NSACR_CP5_S   5U
 
#define SCB_NSACR_CP4   0x00000010U
 
#define SCB_NSACR_CP4_M   0x00000010U
 
#define SCB_NSACR_CP4_S   4U
 
#define SCB_NSACR_CP3   0x00000008U
 
#define SCB_NSACR_CP3_M   0x00000008U
 
#define SCB_NSACR_CP3_S   3U
 
#define SCB_NSACR_CP2   0x00000004U
 
#define SCB_NSACR_CP2_M   0x00000004U
 
#define SCB_NSACR_CP2_S   2U
 
#define SCB_NSACR_CP1   0x00000002U
 
#define SCB_NSACR_CP1_M   0x00000002U
 
#define SCB_NSACR_CP1_S   1U
 
#define SCB_NSACR_CP0   0x00000001U
 
#define SCB_NSACR_CP0_M   0x00000001U
 
#define SCB_NSACR_CP0_S   0U
 

Macro Definition Documentation

§ SCB_O_REVIDR

#define SCB_O_REVIDR   0x00000000U

§ SCB_O_CPUID

#define SCB_O_CPUID   0x00000004U

§ SCB_O_ICSR

#define SCB_O_ICSR   0x00000008U

§ SCB_O_VTOR

#define SCB_O_VTOR   0x0000000CU

§ SCB_O_AIRCR

#define SCB_O_AIRCR   0x00000010U

§ SCB_O_SCR

#define SCB_O_SCR   0x00000014U

§ SCB_O_CCR

#define SCB_O_CCR   0x00000018U

§ SCB_O_SHPR1

#define SCB_O_SHPR1   0x0000001CU

§ SCB_O_SHPR2

#define SCB_O_SHPR2   0x00000020U

§ SCB_O_SHPR3

#define SCB_O_SHPR3   0x00000024U

§ SCB_O_SHCSR

#define SCB_O_SHCSR   0x00000028U

§ SCB_O_CFSR

#define SCB_O_CFSR   0x0000002CU

§ SCB_O_HFSR

#define SCB_O_HFSR   0x00000030U

§ SCB_O_DFSR

#define SCB_O_DFSR   0x00000034U

§ SCB_O_MMFAR

#define SCB_O_MMFAR   0x00000038U

§ SCB_O_BFAR

#define SCB_O_BFAR   0x0000003CU

§ SCB_O_AFSR

#define SCB_O_AFSR   0x00000040U

§ SCB_O_ID_PFR0

#define SCB_O_ID_PFR0   0x00000044U

§ SCB_O_ID_PFR1

#define SCB_O_ID_PFR1   0x00000048U

§ SCB_O_ID_DFR0

#define SCB_O_ID_DFR0   0x0000004CU

§ SCB_O_ID_AFR0

#define SCB_O_ID_AFR0   0x00000050U

§ SCB_O_ID_MMFR0

#define SCB_O_ID_MMFR0   0x00000054U

§ SCB_O_ID_MMFR1

#define SCB_O_ID_MMFR1   0x00000058U

§ SCB_O_ID_MMFR2

#define SCB_O_ID_MMFR2   0x0000005CU

§ SCB_O_ID_MMFR3

#define SCB_O_ID_MMFR3   0x00000060U

§ SCB_O_ID_ISAR0

#define SCB_O_ID_ISAR0   0x00000064U

§ SCB_O_ID_ISAR1

#define SCB_O_ID_ISAR1   0x00000068U

§ SCB_O_ID_ISAR2

#define SCB_O_ID_ISAR2   0x0000006CU

§ SCB_O_ID_ISAR3

#define SCB_O_ID_ISAR3   0x00000070U

§ SCB_O_ID_ISAR4

#define SCB_O_ID_ISAR4   0x00000074U

§ SCB_O_ID_ISAR5

#define SCB_O_ID_ISAR5   0x00000078U

§ SCB_O_CLIDR

#define SCB_O_CLIDR   0x0000007CU

§ SCB_O_CTR

#define SCB_O_CTR   0x00000080U

§ SCB_O_CCSIDR

#define SCB_O_CCSIDR   0x00000084U

§ SCB_O_CSSELR

#define SCB_O_CSSELR   0x00000088U

§ SCB_O_CPACR

#define SCB_O_CPACR   0x0000008CU

§ SCB_O_NSACR

#define SCB_O_NSACR   0x00000090U

§ SCB_REVIDR_IMPLEMENTAION_DEFINED_W

#define SCB_REVIDR_IMPLEMENTAION_DEFINED_W   32U

§ SCB_REVIDR_IMPLEMENTAION_DEFINED_M

#define SCB_REVIDR_IMPLEMENTAION_DEFINED_M   0xFFFFFFFFU

§ SCB_REVIDR_IMPLEMENTAION_DEFINED_S

#define SCB_REVIDR_IMPLEMENTAION_DEFINED_S   0U

§ SCB_CPUID_IMPLEMENTER_W

#define SCB_CPUID_IMPLEMENTER_W   8U

§ SCB_CPUID_IMPLEMENTER_M

#define SCB_CPUID_IMPLEMENTER_M   0xFF000000U

§ SCB_CPUID_IMPLEMENTER_S

#define SCB_CPUID_IMPLEMENTER_S   24U

§ SCB_CPUID_VARIANT_W

#define SCB_CPUID_VARIANT_W   4U

§ SCB_CPUID_VARIANT_M

#define SCB_CPUID_VARIANT_M   0x00F00000U

§ SCB_CPUID_VARIANT_S

#define SCB_CPUID_VARIANT_S   20U

§ SCB_CPUID_ARCHITECTURE_W

#define SCB_CPUID_ARCHITECTURE_W   4U

§ SCB_CPUID_ARCHITECTURE_M

#define SCB_CPUID_ARCHITECTURE_M   0x000F0000U

§ SCB_CPUID_ARCHITECTURE_S

#define SCB_CPUID_ARCHITECTURE_S   16U

§ SCB_CPUID_PARTNO_W

#define SCB_CPUID_PARTNO_W   12U

§ SCB_CPUID_PARTNO_M

#define SCB_CPUID_PARTNO_M   0x0000FFF0U

§ SCB_CPUID_PARTNO_S

#define SCB_CPUID_PARTNO_S   4U

§ SCB_CPUID_REVISION_W

#define SCB_CPUID_REVISION_W   4U

§ SCB_CPUID_REVISION_M

#define SCB_CPUID_REVISION_M   0x0000000FU

§ SCB_CPUID_REVISION_S

#define SCB_CPUID_REVISION_S   0U

§ SCB_ICSR_PENDNMISET

#define SCB_ICSR_PENDNMISET   0x80000000U

§ SCB_ICSR_PENDNMISET_M

#define SCB_ICSR_PENDNMISET_M   0x80000000U

§ SCB_ICSR_PENDNMISET_S

#define SCB_ICSR_PENDNMISET_S   31U

§ SCB_ICSR_PENDNMICLR

#define SCB_ICSR_PENDNMICLR   0x40000000U

§ SCB_ICSR_PENDNMICLR_M

#define SCB_ICSR_PENDNMICLR_M   0x40000000U

§ SCB_ICSR_PENDNMICLR_S

#define SCB_ICSR_PENDNMICLR_S   30U

§ SCB_ICSR_RES0

#define SCB_ICSR_RES0   0x20000000U

§ SCB_ICSR_RES0_M

#define SCB_ICSR_RES0_M   0x20000000U

§ SCB_ICSR_RES0_S

#define SCB_ICSR_RES0_S   29U

§ SCB_ICSR_PENDSVSET

#define SCB_ICSR_PENDSVSET   0x10000000U

§ SCB_ICSR_PENDSVSET_M

#define SCB_ICSR_PENDSVSET_M   0x10000000U

§ SCB_ICSR_PENDSVSET_S

#define SCB_ICSR_PENDSVSET_S   28U

§ SCB_ICSR_PENDSVCLR

#define SCB_ICSR_PENDSVCLR   0x08000000U

§ SCB_ICSR_PENDSVCLR_M

#define SCB_ICSR_PENDSVCLR_M   0x08000000U

§ SCB_ICSR_PENDSVCLR_S

#define SCB_ICSR_PENDSVCLR_S   27U

§ SCB_ICSR_PENDSTSET

#define SCB_ICSR_PENDSTSET   0x04000000U

§ SCB_ICSR_PENDSTSET_M

#define SCB_ICSR_PENDSTSET_M   0x04000000U

§ SCB_ICSR_PENDSTSET_S

#define SCB_ICSR_PENDSTSET_S   26U

§ SCB_ICSR_PENDSTCLR

#define SCB_ICSR_PENDSTCLR   0x02000000U

§ SCB_ICSR_PENDSTCLR_M

#define SCB_ICSR_PENDSTCLR_M   0x02000000U

§ SCB_ICSR_PENDSTCLR_S

#define SCB_ICSR_PENDSTCLR_S   25U

§ SCB_ICSR_STTNS

#define SCB_ICSR_STTNS   0x01000000U

§ SCB_ICSR_STTNS_M

#define SCB_ICSR_STTNS_M   0x01000000U

§ SCB_ICSR_STTNS_S

#define SCB_ICSR_STTNS_S   24U

§ SCB_ICSR_ISRPREEMPT

#define SCB_ICSR_ISRPREEMPT   0x00800000U

§ SCB_ICSR_ISRPREEMPT_M

#define SCB_ICSR_ISRPREEMPT_M   0x00800000U

§ SCB_ICSR_ISRPREEMPT_S

#define SCB_ICSR_ISRPREEMPT_S   23U

§ SCB_ICSR_ISRPENDING

#define SCB_ICSR_ISRPENDING   0x00400000U

§ SCB_ICSR_ISRPENDING_M

#define SCB_ICSR_ISRPENDING_M   0x00400000U

§ SCB_ICSR_ISRPENDING_S

#define SCB_ICSR_ISRPENDING_S   22U

§ SCB_ICSR_RES0_1

#define SCB_ICSR_RES0_1   0x00200000U

§ SCB_ICSR_RES0_1_M

#define SCB_ICSR_RES0_1_M   0x00200000U

§ SCB_ICSR_RES0_1_S

#define SCB_ICSR_RES0_1_S   21U

§ SCB_ICSR_VECTPENDING_W

#define SCB_ICSR_VECTPENDING_W   9U

§ SCB_ICSR_VECTPENDING_M

#define SCB_ICSR_VECTPENDING_M   0x001FF000U

§ SCB_ICSR_VECTPENDING_S

#define SCB_ICSR_VECTPENDING_S   12U

§ SCB_ICSR_RETTOBASE

#define SCB_ICSR_RETTOBASE   0x00000800U

§ SCB_ICSR_RETTOBASE_M

#define SCB_ICSR_RETTOBASE_M   0x00000800U

§ SCB_ICSR_RETTOBASE_S

#define SCB_ICSR_RETTOBASE_S   11U

§ SCB_ICSR_RES0_2_W

#define SCB_ICSR_RES0_2_W   2U

§ SCB_ICSR_RES0_2_M

#define SCB_ICSR_RES0_2_M   0x00000600U

§ SCB_ICSR_RES0_2_S

#define SCB_ICSR_RES0_2_S   9U

§ SCB_ICSR_VECTACTIVE_W

#define SCB_ICSR_VECTACTIVE_W   9U

§ SCB_ICSR_VECTACTIVE_M

#define SCB_ICSR_VECTACTIVE_M   0x000001FFU

§ SCB_ICSR_VECTACTIVE_S

#define SCB_ICSR_VECTACTIVE_S   0U

§ SCB_VTOR_TBLOFF_W

#define SCB_VTOR_TBLOFF_W   25U

§ SCB_VTOR_TBLOFF_M

#define SCB_VTOR_TBLOFF_M   0xFFFFFF80U

§ SCB_VTOR_TBLOFF_S

#define SCB_VTOR_TBLOFF_S   7U

§ SCB_VTOR_RES0_W

#define SCB_VTOR_RES0_W   7U

§ SCB_VTOR_RES0_M

#define SCB_VTOR_RES0_M   0x0000007FU

§ SCB_VTOR_RES0_S

#define SCB_VTOR_RES0_S   0U

§ SCB_AIRCR_VECTKEY_W

#define SCB_AIRCR_VECTKEY_W   16U

§ SCB_AIRCR_VECTKEY_M

#define SCB_AIRCR_VECTKEY_M   0xFFFF0000U

§ SCB_AIRCR_VECTKEY_S

#define SCB_AIRCR_VECTKEY_S   16U

§ SCB_AIRCR_ENDIANESS

#define SCB_AIRCR_ENDIANESS   0x00008000U

§ SCB_AIRCR_ENDIANESS_M

#define SCB_AIRCR_ENDIANESS_M   0x00008000U

§ SCB_AIRCR_ENDIANESS_S

#define SCB_AIRCR_ENDIANESS_S   15U

§ SCB_AIRCR_PRIS

#define SCB_AIRCR_PRIS   0x00004000U

§ SCB_AIRCR_PRIS_M

#define SCB_AIRCR_PRIS_M   0x00004000U

§ SCB_AIRCR_PRIS_S

#define SCB_AIRCR_PRIS_S   14U

§ SCB_AIRCR_BFHFNMINS

#define SCB_AIRCR_BFHFNMINS   0x00002000U

§ SCB_AIRCR_BFHFNMINS_M

#define SCB_AIRCR_BFHFNMINS_M   0x00002000U

§ SCB_AIRCR_BFHFNMINS_S

#define SCB_AIRCR_BFHFNMINS_S   13U

§ SCB_AIRCR_PRIGROUP_W

#define SCB_AIRCR_PRIGROUP_W   3U

§ SCB_AIRCR_PRIGROUP_M

#define SCB_AIRCR_PRIGROUP_M   0x00000700U

§ SCB_AIRCR_PRIGROUP_S

#define SCB_AIRCR_PRIGROUP_S   8U

§ SCB_AIRCR_RES4_W

#define SCB_AIRCR_RES4_W   4U

§ SCB_AIRCR_RES4_M

#define SCB_AIRCR_RES4_M   0x000000F0U

§ SCB_AIRCR_RES4_S

#define SCB_AIRCR_RES4_S   4U

§ SCB_AIRCR_SYSRESETREQS

#define SCB_AIRCR_SYSRESETREQS   0x00000008U

§ SCB_AIRCR_SYSRESETREQS_M

#define SCB_AIRCR_SYSRESETREQS_M   0x00000008U

§ SCB_AIRCR_SYSRESETREQS_S

#define SCB_AIRCR_SYSRESETREQS_S   3U

§ SCB_AIRCR_SYSRESETREQ

#define SCB_AIRCR_SYSRESETREQ   0x00000004U

§ SCB_AIRCR_SYSRESETREQ_M

#define SCB_AIRCR_SYSRESETREQ_M   0x00000004U

§ SCB_AIRCR_SYSRESETREQ_S

#define SCB_AIRCR_SYSRESETREQ_S   2U

§ SCB_AIRCR_VECTCLRACTIVE

#define SCB_AIRCR_VECTCLRACTIVE   0x00000002U

§ SCB_AIRCR_VECTCLRACTIVE_M

#define SCB_AIRCR_VECTCLRACTIVE_M   0x00000002U

§ SCB_AIRCR_VECTCLRACTIVE_S

#define SCB_AIRCR_VECTCLRACTIVE_S   1U

§ SCB_AIRCR_RES0

#define SCB_AIRCR_RES0   0x00000001U

§ SCB_AIRCR_RES0_M

#define SCB_AIRCR_RES0_M   0x00000001U

§ SCB_AIRCR_RES0_S

#define SCB_AIRCR_RES0_S   0U

§ SCB_SCR_SEVONPEND

#define SCB_SCR_SEVONPEND   0x00000010U

§ SCB_SCR_SEVONPEND_M

#define SCB_SCR_SEVONPEND_M   0x00000010U

§ SCB_SCR_SEVONPEND_S

#define SCB_SCR_SEVONPEND_S   4U

§ SCB_SCR_SLEEPDEEPS

#define SCB_SCR_SLEEPDEEPS   0x00000008U

§ SCB_SCR_SLEEPDEEPS_M

#define SCB_SCR_SLEEPDEEPS_M   0x00000008U

§ SCB_SCR_SLEEPDEEPS_S

#define SCB_SCR_SLEEPDEEPS_S   3U

§ SCB_SCR_SLEEPDEEP

#define SCB_SCR_SLEEPDEEP   0x00000004U

§ SCB_SCR_SLEEPDEEP_M

#define SCB_SCR_SLEEPDEEP_M   0x00000004U

§ SCB_SCR_SLEEPDEEP_S

#define SCB_SCR_SLEEPDEEP_S   2U

§ SCB_SCR_SLEEPONEXIT

#define SCB_SCR_SLEEPONEXIT   0x00000002U

§ SCB_SCR_SLEEPONEXIT_M

#define SCB_SCR_SLEEPONEXIT_M   0x00000002U

§ SCB_SCR_SLEEPONEXIT_S

#define SCB_SCR_SLEEPONEXIT_S   1U

§ SCB_CCR_RES0_W

#define SCB_CCR_RES0_W   13U

§ SCB_CCR_RES0_M

#define SCB_CCR_RES0_M   0xFFF80000U

§ SCB_CCR_RES0_S

#define SCB_CCR_RES0_S   19U

§ SCB_CCR_BP

#define SCB_CCR_BP   0x00040000U

§ SCB_CCR_BP_M

#define SCB_CCR_BP_M   0x00040000U

§ SCB_CCR_BP_S

#define SCB_CCR_BP_S   18U

§ SCB_CCR_IC

#define SCB_CCR_IC   0x00020000U

§ SCB_CCR_IC_M

#define SCB_CCR_IC_M   0x00020000U

§ SCB_CCR_IC_S

#define SCB_CCR_IC_S   17U

§ SCB_CCR_DC

#define SCB_CCR_DC   0x00010000U

§ SCB_CCR_DC_M

#define SCB_CCR_DC_M   0x00010000U

§ SCB_CCR_DC_S

#define SCB_CCR_DC_S   16U

§ SCB_CCR_RES0_1_W

#define SCB_CCR_RES0_1_W   5U

§ SCB_CCR_RES0_1_M

#define SCB_CCR_RES0_1_M   0x0000F800U

§ SCB_CCR_RES0_1_S

#define SCB_CCR_RES0_1_S   11U

§ SCB_CCR_STKOFHFNMIGN

#define SCB_CCR_STKOFHFNMIGN   0x00000400U

§ SCB_CCR_STKOFHFNMIGN_M

#define SCB_CCR_STKOFHFNMIGN_M   0x00000400U

§ SCB_CCR_STKOFHFNMIGN_S

#define SCB_CCR_STKOFHFNMIGN_S   10U

§ SCB_CCR_RES1

#define SCB_CCR_RES1   0x00000200U

§ SCB_CCR_RES1_M

#define SCB_CCR_RES1_M   0x00000200U

§ SCB_CCR_RES1_S

#define SCB_CCR_RES1_S   9U

§ SCB_CCR_BFHFNMIGN

#define SCB_CCR_BFHFNMIGN   0x00000100U

§ SCB_CCR_BFHFNMIGN_M

#define SCB_CCR_BFHFNMIGN_M   0x00000100U

§ SCB_CCR_BFHFNMIGN_S

#define SCB_CCR_BFHFNMIGN_S   8U

§ SCB_CCR_RES0_2_W

#define SCB_CCR_RES0_2_W   3U

§ SCB_CCR_RES0_2_M

#define SCB_CCR_RES0_2_M   0x000000E0U

§ SCB_CCR_RES0_2_S

#define SCB_CCR_RES0_2_S   5U

§ SCB_CCR_DIV_0_TRP

#define SCB_CCR_DIV_0_TRP   0x00000010U

§ SCB_CCR_DIV_0_TRP_M

#define SCB_CCR_DIV_0_TRP_M   0x00000010U

§ SCB_CCR_DIV_0_TRP_S

#define SCB_CCR_DIV_0_TRP_S   4U

§ SCB_CCR_UNALIGN_TRP

#define SCB_CCR_UNALIGN_TRP   0x00000008U

§ SCB_CCR_UNALIGN_TRP_M

#define SCB_CCR_UNALIGN_TRP_M   0x00000008U

§ SCB_CCR_UNALIGN_TRP_S

#define SCB_CCR_UNALIGN_TRP_S   3U

§ SCB_CCR_RES0_3

#define SCB_CCR_RES0_3   0x00000004U

§ SCB_CCR_RES0_3_M

#define SCB_CCR_RES0_3_M   0x00000004U

§ SCB_CCR_RES0_3_S

#define SCB_CCR_RES0_3_S   2U

§ SCB_CCR_USERSETMPEND

#define SCB_CCR_USERSETMPEND   0x00000002U

§ SCB_CCR_USERSETMPEND_M

#define SCB_CCR_USERSETMPEND_M   0x00000002U

§ SCB_CCR_USERSETMPEND_S

#define SCB_CCR_USERSETMPEND_S   1U

§ SCB_CCR_RES1_1

#define SCB_CCR_RES1_1   0x00000001U

§ SCB_CCR_RES1_1_M

#define SCB_CCR_RES1_1_M   0x00000001U

§ SCB_CCR_RES1_1_S

#define SCB_CCR_RES1_1_S   0U

§ SCB_SHPR1_PRI_7_W

#define SCB_SHPR1_PRI_7_W   8U

§ SCB_SHPR1_PRI_7_M

#define SCB_SHPR1_PRI_7_M   0xFF000000U

§ SCB_SHPR1_PRI_7_S

#define SCB_SHPR1_PRI_7_S   24U

§ SCB_SHPR1_PRI_6_W

#define SCB_SHPR1_PRI_6_W   8U

§ SCB_SHPR1_PRI_6_M

#define SCB_SHPR1_PRI_6_M   0x00FF0000U

§ SCB_SHPR1_PRI_6_S

#define SCB_SHPR1_PRI_6_S   16U

§ SCB_SHPR1_PRI_5_W

#define SCB_SHPR1_PRI_5_W   8U

§ SCB_SHPR1_PRI_5_M

#define SCB_SHPR1_PRI_5_M   0x0000FF00U

§ SCB_SHPR1_PRI_5_S

#define SCB_SHPR1_PRI_5_S   8U

§ SCB_SHPR1_PRI_4_W

#define SCB_SHPR1_PRI_4_W   8U

§ SCB_SHPR1_PRI_4_M

#define SCB_SHPR1_PRI_4_M   0x000000FFU

§ SCB_SHPR1_PRI_4_S

#define SCB_SHPR1_PRI_4_S   0U

§ SCB_SHPR2_PRI_11_W

#define SCB_SHPR2_PRI_11_W   8U

§ SCB_SHPR2_PRI_11_M

#define SCB_SHPR2_PRI_11_M   0xFF000000U

§ SCB_SHPR2_PRI_11_S

#define SCB_SHPR2_PRI_11_S   24U

§ SCB_SHPR2_RES0_W

#define SCB_SHPR2_RES0_W   24U

§ SCB_SHPR2_RES0_M

#define SCB_SHPR2_RES0_M   0x00FFFFFFU

§ SCB_SHPR2_RES0_S

#define SCB_SHPR2_RES0_S   0U

§ SCB_SHPR3_PRI_15_W

#define SCB_SHPR3_PRI_15_W   8U

§ SCB_SHPR3_PRI_15_M

#define SCB_SHPR3_PRI_15_M   0xFF000000U

§ SCB_SHPR3_PRI_15_S

#define SCB_SHPR3_PRI_15_S   24U

§ SCB_SHPR3_PRI_14_W

#define SCB_SHPR3_PRI_14_W   8U

§ SCB_SHPR3_PRI_14_M

#define SCB_SHPR3_PRI_14_M   0x00FF0000U

§ SCB_SHPR3_PRI_14_S

#define SCB_SHPR3_PRI_14_S   16U

§ SCB_SHPR3_RES0_0_W

#define SCB_SHPR3_RES0_0_W   16U

§ SCB_SHPR3_RES0_0_M

#define SCB_SHPR3_RES0_0_M   0x0000FFFFU

§ SCB_SHPR3_RES0_0_S

#define SCB_SHPR3_RES0_0_S   0U

§ SCB_SHCSR_RES0_W

#define SCB_SHCSR_RES0_W   10U

§ SCB_SHCSR_RES0_M

#define SCB_SHCSR_RES0_M   0xFFC00000U

§ SCB_SHCSR_RES0_S

#define SCB_SHCSR_RES0_S   22U

§ SCB_SHCSR_HARDFAULTPENDED

#define SCB_SHCSR_HARDFAULTPENDED   0x00200000U

§ SCB_SHCSR_HARDFAULTPENDED_M

#define SCB_SHCSR_HARDFAULTPENDED_M   0x00200000U

§ SCB_SHCSR_HARDFAULTPENDED_S

#define SCB_SHCSR_HARDFAULTPENDED_S   21U

§ SCB_SHCSR_SECUREFAULTPENDED

#define SCB_SHCSR_SECUREFAULTPENDED   0x00100000U

§ SCB_SHCSR_SECUREFAULTPENDED_M

#define SCB_SHCSR_SECUREFAULTPENDED_M   0x00100000U

§ SCB_SHCSR_SECUREFAULTPENDED_S

#define SCB_SHCSR_SECUREFAULTPENDED_S   20U

§ SCB_SHCSR_SECUREFAULTENA

#define SCB_SHCSR_SECUREFAULTENA   0x00080000U

§ SCB_SHCSR_SECUREFAULTENA_M

#define SCB_SHCSR_SECUREFAULTENA_M   0x00080000U

§ SCB_SHCSR_SECUREFAULTENA_S

#define SCB_SHCSR_SECUREFAULTENA_S   19U

§ SCB_SHCSR_USGFAULTENA

#define SCB_SHCSR_USGFAULTENA   0x00040000U

§ SCB_SHCSR_USGFAULTENA_M

#define SCB_SHCSR_USGFAULTENA_M   0x00040000U

§ SCB_SHCSR_USGFAULTENA_S

#define SCB_SHCSR_USGFAULTENA_S   18U

§ SCB_SHCSR_BUSFAULTENA

#define SCB_SHCSR_BUSFAULTENA   0x00020000U

§ SCB_SHCSR_BUSFAULTENA_M

#define SCB_SHCSR_BUSFAULTENA_M   0x00020000U

§ SCB_SHCSR_BUSFAULTENA_S

#define SCB_SHCSR_BUSFAULTENA_S   17U

§ SCB_SHCSR_MEMFAULTENA

#define SCB_SHCSR_MEMFAULTENA   0x00010000U

§ SCB_SHCSR_MEMFAULTENA_M

#define SCB_SHCSR_MEMFAULTENA_M   0x00010000U

§ SCB_SHCSR_MEMFAULTENA_S

#define SCB_SHCSR_MEMFAULTENA_S   16U

§ SCB_SHCSR_SVCALLPENDED

#define SCB_SHCSR_SVCALLPENDED   0x00008000U

§ SCB_SHCSR_SVCALLPENDED_M

#define SCB_SHCSR_SVCALLPENDED_M   0x00008000U

§ SCB_SHCSR_SVCALLPENDED_S

#define SCB_SHCSR_SVCALLPENDED_S   15U

§ SCB_SHCSR_BUSFAULTPENDED

#define SCB_SHCSR_BUSFAULTPENDED   0x00004000U

§ SCB_SHCSR_BUSFAULTPENDED_M

#define SCB_SHCSR_BUSFAULTPENDED_M   0x00004000U

§ SCB_SHCSR_BUSFAULTPENDED_S

#define SCB_SHCSR_BUSFAULTPENDED_S   14U

§ SCB_SHCSR_MEMFAULTPENDED

#define SCB_SHCSR_MEMFAULTPENDED   0x00002000U

§ SCB_SHCSR_MEMFAULTPENDED_M

#define SCB_SHCSR_MEMFAULTPENDED_M   0x00002000U

§ SCB_SHCSR_MEMFAULTPENDED_S

#define SCB_SHCSR_MEMFAULTPENDED_S   13U

§ SCB_SHCSR_USGFAULTPENDED

#define SCB_SHCSR_USGFAULTPENDED   0x00001000U

§ SCB_SHCSR_USGFAULTPENDED_M

#define SCB_SHCSR_USGFAULTPENDED_M   0x00001000U

§ SCB_SHCSR_USGFAULTPENDED_S

#define SCB_SHCSR_USGFAULTPENDED_S   12U

§ SCB_SHCSR_SYSTICKACT

#define SCB_SHCSR_SYSTICKACT   0x00000800U

§ SCB_SHCSR_SYSTICKACT_M

#define SCB_SHCSR_SYSTICKACT_M   0x00000800U

§ SCB_SHCSR_SYSTICKACT_S

#define SCB_SHCSR_SYSTICKACT_S   11U

§ SCB_SHCSR_PENDSVACT

#define SCB_SHCSR_PENDSVACT   0x00000400U

§ SCB_SHCSR_PENDSVACT_M

#define SCB_SHCSR_PENDSVACT_M   0x00000400U

§ SCB_SHCSR_PENDSVACT_S

#define SCB_SHCSR_PENDSVACT_S   10U

§ SCB_SHCSR_RES0_1

#define SCB_SHCSR_RES0_1   0x00000200U

§ SCB_SHCSR_RES0_1_M

#define SCB_SHCSR_RES0_1_M   0x00000200U

§ SCB_SHCSR_RES0_1_S

#define SCB_SHCSR_RES0_1_S   9U

§ SCB_SHCSR_MONITORACT

#define SCB_SHCSR_MONITORACT   0x00000100U

§ SCB_SHCSR_MONITORACT_M

#define SCB_SHCSR_MONITORACT_M   0x00000100U

§ SCB_SHCSR_MONITORACT_S

#define SCB_SHCSR_MONITORACT_S   8U

§ SCB_SHCSR_SVCALLACT

#define SCB_SHCSR_SVCALLACT   0x00000080U

§ SCB_SHCSR_SVCALLACT_M

#define SCB_SHCSR_SVCALLACT_M   0x00000080U

§ SCB_SHCSR_SVCALLACT_S

#define SCB_SHCSR_SVCALLACT_S   7U

§ SCB_SHCSR_RES0_2

#define SCB_SHCSR_RES0_2   0x00000040U

§ SCB_SHCSR_RES0_2_M

#define SCB_SHCSR_RES0_2_M   0x00000040U

§ SCB_SHCSR_RES0_2_S

#define SCB_SHCSR_RES0_2_S   6U

§ SCB_SHCSR_NMIACT

#define SCB_SHCSR_NMIACT   0x00000020U

§ SCB_SHCSR_NMIACT_M

#define SCB_SHCSR_NMIACT_M   0x00000020U

§ SCB_SHCSR_NMIACT_S

#define SCB_SHCSR_NMIACT_S   5U

§ SCB_SHCSR_SECUREFAULTACT

#define SCB_SHCSR_SECUREFAULTACT   0x00000010U

§ SCB_SHCSR_SECUREFAULTACT_M

#define SCB_SHCSR_SECUREFAULTACT_M   0x00000010U

§ SCB_SHCSR_SECUREFAULTACT_S

#define SCB_SHCSR_SECUREFAULTACT_S   4U

§ SCB_SHCSR_USGFAULTACT

#define SCB_SHCSR_USGFAULTACT   0x00000008U

§ SCB_SHCSR_USGFAULTACT_M

#define SCB_SHCSR_USGFAULTACT_M   0x00000008U

§ SCB_SHCSR_USGFAULTACT_S

#define SCB_SHCSR_USGFAULTACT_S   3U

§ SCB_SHCSR_HARDFAULTACT

#define SCB_SHCSR_HARDFAULTACT   0x00000004U

§ SCB_SHCSR_HARDFAULTACT_M

#define SCB_SHCSR_HARDFAULTACT_M   0x00000004U

§ SCB_SHCSR_HARDFAULTACT_S

#define SCB_SHCSR_HARDFAULTACT_S   2U

§ SCB_SHCSR_BUSFAULTACT

#define SCB_SHCSR_BUSFAULTACT   0x00000002U

§ SCB_SHCSR_BUSFAULTACT_M

#define SCB_SHCSR_BUSFAULTACT_M   0x00000002U

§ SCB_SHCSR_BUSFAULTACT_S

#define SCB_SHCSR_BUSFAULTACT_S   1U

§ SCB_SHCSR_MEMFAULTACT

#define SCB_SHCSR_MEMFAULTACT   0x00000001U

§ SCB_SHCSR_MEMFAULTACT_M

#define SCB_SHCSR_MEMFAULTACT_M   0x00000001U

§ SCB_SHCSR_MEMFAULTACT_S

#define SCB_SHCSR_MEMFAULTACT_S   0U

§ SCB_CFSR_RES0_3_W

#define SCB_CFSR_RES0_3_W   6U

§ SCB_CFSR_RES0_3_M

#define SCB_CFSR_RES0_3_M   0xFC000000U

§ SCB_CFSR_RES0_3_S

#define SCB_CFSR_RES0_3_S   26U

§ SCB_CFSR_DIVBYZERO

#define SCB_CFSR_DIVBYZERO   0x02000000U

§ SCB_CFSR_DIVBYZERO_M

#define SCB_CFSR_DIVBYZERO_M   0x02000000U

§ SCB_CFSR_DIVBYZERO_S

#define SCB_CFSR_DIVBYZERO_S   25U

§ SCB_CFSR_UNALIGNED

#define SCB_CFSR_UNALIGNED   0x01000000U

§ SCB_CFSR_UNALIGNED_M

#define SCB_CFSR_UNALIGNED_M   0x01000000U

§ SCB_CFSR_UNALIGNED_S

#define SCB_CFSR_UNALIGNED_S   24U

§ SCB_CFSR_RES0_1_2_W

#define SCB_CFSR_RES0_1_2_W   3U

§ SCB_CFSR_RES0_1_2_M

#define SCB_CFSR_RES0_1_2_M   0x00E00000U

§ SCB_CFSR_RES0_1_2_S

#define SCB_CFSR_RES0_1_2_S   21U

§ SCB_CFSR_STKOF

#define SCB_CFSR_STKOF   0x00100000U

§ SCB_CFSR_STKOF_M

#define SCB_CFSR_STKOF_M   0x00100000U

§ SCB_CFSR_STKOF_S

#define SCB_CFSR_STKOF_S   20U

§ SCB_CFSR_NOCP

#define SCB_CFSR_NOCP   0x00080000U

§ SCB_CFSR_NOCP_M

#define SCB_CFSR_NOCP_M   0x00080000U

§ SCB_CFSR_NOCP_S

#define SCB_CFSR_NOCP_S   19U

§ SCB_CFSR_INVPC

#define SCB_CFSR_INVPC   0x00040000U

§ SCB_CFSR_INVPC_M

#define SCB_CFSR_INVPC_M   0x00040000U

§ SCB_CFSR_INVPC_S

#define SCB_CFSR_INVPC_S   18U

§ SCB_CFSR_INVSTATE

#define SCB_CFSR_INVSTATE   0x00020000U

§ SCB_CFSR_INVSTATE_M

#define SCB_CFSR_INVSTATE_M   0x00020000U

§ SCB_CFSR_INVSTATE_S

#define SCB_CFSR_INVSTATE_S   17U

§ SCB_CFSR_UNDEFINSTR

#define SCB_CFSR_UNDEFINSTR   0x00010000U

§ SCB_CFSR_UNDEFINSTR_M

#define SCB_CFSR_UNDEFINSTR_M   0x00010000U

§ SCB_CFSR_UNDEFINSTR_S

#define SCB_CFSR_UNDEFINSTR_S   16U

§ SCB_CFSR_BFARVALID

#define SCB_CFSR_BFARVALID   0x00008000U

§ SCB_CFSR_BFARVALID_M

#define SCB_CFSR_BFARVALID_M   0x00008000U

§ SCB_CFSR_BFARVALID_S

#define SCB_CFSR_BFARVALID_S   15U

§ SCB_CFSR_RES0_2

#define SCB_CFSR_RES0_2   0x00004000U

§ SCB_CFSR_RES0_2_M

#define SCB_CFSR_RES0_2_M   0x00004000U

§ SCB_CFSR_RES0_2_S

#define SCB_CFSR_RES0_2_S   14U

§ SCB_CFSR_LSPERR

#define SCB_CFSR_LSPERR   0x00002000U

§ SCB_CFSR_LSPERR_M

#define SCB_CFSR_LSPERR_M   0x00002000U

§ SCB_CFSR_LSPERR_S

#define SCB_CFSR_LSPERR_S   13U

§ SCB_CFSR_STKERR

#define SCB_CFSR_STKERR   0x00001000U

§ SCB_CFSR_STKERR_M

#define SCB_CFSR_STKERR_M   0x00001000U

§ SCB_CFSR_STKERR_S

#define SCB_CFSR_STKERR_S   12U

§ SCB_CFSR_UNSTKERR

#define SCB_CFSR_UNSTKERR   0x00000800U

§ SCB_CFSR_UNSTKERR_M

#define SCB_CFSR_UNSTKERR_M   0x00000800U

§ SCB_CFSR_UNSTKERR_S

#define SCB_CFSR_UNSTKERR_S   11U

§ SCB_CFSR_IMPRECISERR

#define SCB_CFSR_IMPRECISERR   0x00000400U

§ SCB_CFSR_IMPRECISERR_M

#define SCB_CFSR_IMPRECISERR_M   0x00000400U

§ SCB_CFSR_IMPRECISERR_S

#define SCB_CFSR_IMPRECISERR_S   10U

§ SCB_CFSR_PRECISERR

#define SCB_CFSR_PRECISERR   0x00000200U

§ SCB_CFSR_PRECISERR_M

#define SCB_CFSR_PRECISERR_M   0x00000200U

§ SCB_CFSR_PRECISERR_S

#define SCB_CFSR_PRECISERR_S   9U

§ SCB_CFSR_IBUSERR

#define SCB_CFSR_IBUSERR   0x00000100U

§ SCB_CFSR_IBUSERR_M

#define SCB_CFSR_IBUSERR_M   0x00000100U

§ SCB_CFSR_IBUSERR_S

#define SCB_CFSR_IBUSERR_S   8U

§ SCB_CFSR_MMARVALID

#define SCB_CFSR_MMARVALID   0x00000080U

§ SCB_CFSR_MMARVALID_M

#define SCB_CFSR_MMARVALID_M   0x00000080U

§ SCB_CFSR_MMARVALID_S

#define SCB_CFSR_MMARVALID_S   7U

§ SCB_CFSR_RES0

#define SCB_CFSR_RES0   0x00000040U

§ SCB_CFSR_RES0_M

#define SCB_CFSR_RES0_M   0x00000040U

§ SCB_CFSR_RES0_S

#define SCB_CFSR_RES0_S   6U

§ SCB_CFSR_MLSPERR

#define SCB_CFSR_MLSPERR   0x00000020U

§ SCB_CFSR_MLSPERR_M

#define SCB_CFSR_MLSPERR_M   0x00000020U

§ SCB_CFSR_MLSPERR_S

#define SCB_CFSR_MLSPERR_S   5U

§ SCB_CFSR_MSTKERR

#define SCB_CFSR_MSTKERR   0x00000010U

§ SCB_CFSR_MSTKERR_M

#define SCB_CFSR_MSTKERR_M   0x00000010U

§ SCB_CFSR_MSTKERR_S

#define SCB_CFSR_MSTKERR_S   4U

§ SCB_CFSR_MUNSTKERR

#define SCB_CFSR_MUNSTKERR   0x00000008U

§ SCB_CFSR_MUNSTKERR_M

#define SCB_CFSR_MUNSTKERR_M   0x00000008U

§ SCB_CFSR_MUNSTKERR_S

#define SCB_CFSR_MUNSTKERR_S   3U

§ SCB_CFSR_RES0_1

#define SCB_CFSR_RES0_1   0x00000004U

§ SCB_CFSR_RES0_1_M

#define SCB_CFSR_RES0_1_M   0x00000004U

§ SCB_CFSR_RES0_1_S

#define SCB_CFSR_RES0_1_S   2U

§ SCB_CFSR_DACCVIOL

#define SCB_CFSR_DACCVIOL   0x00000002U

§ SCB_CFSR_DACCVIOL_M

#define SCB_CFSR_DACCVIOL_M   0x00000002U

§ SCB_CFSR_DACCVIOL_S

#define SCB_CFSR_DACCVIOL_S   1U

§ SCB_CFSR_IACCVIOL

#define SCB_CFSR_IACCVIOL   0x00000001U

§ SCB_CFSR_IACCVIOL_M

#define SCB_CFSR_IACCVIOL_M   0x00000001U

§ SCB_CFSR_IACCVIOL_S

#define SCB_CFSR_IACCVIOL_S   0U

§ SCB_HFSR_DEBUGEVT

#define SCB_HFSR_DEBUGEVT   0x80000000U

§ SCB_HFSR_DEBUGEVT_M

#define SCB_HFSR_DEBUGEVT_M   0x80000000U

§ SCB_HFSR_DEBUGEVT_S

#define SCB_HFSR_DEBUGEVT_S   31U

§ SCB_HFSR_FORCED

#define SCB_HFSR_FORCED   0x40000000U

§ SCB_HFSR_FORCED_M

#define SCB_HFSR_FORCED_M   0x40000000U

§ SCB_HFSR_FORCED_S

#define SCB_HFSR_FORCED_S   30U

§ SCB_HFSR_RES0_W

#define SCB_HFSR_RES0_W   28U

§ SCB_HFSR_RES0_M

#define SCB_HFSR_RES0_M   0x3FFFFFFCU

§ SCB_HFSR_RES0_S

#define SCB_HFSR_RES0_S   2U

§ SCB_HFSR_VECTTBL

#define SCB_HFSR_VECTTBL   0x00000002U

§ SCB_HFSR_VECTTBL_M

#define SCB_HFSR_VECTTBL_M   0x00000002U

§ SCB_HFSR_VECTTBL_S

#define SCB_HFSR_VECTTBL_S   1U

§ SCB_HFSR_RES0_1

#define SCB_HFSR_RES0_1   0x00000001U

§ SCB_HFSR_RES0_1_M

#define SCB_HFSR_RES0_1_M   0x00000001U

§ SCB_HFSR_RES0_1_S

#define SCB_HFSR_RES0_1_S   0U

§ SCB_DFSR_RES0_W

#define SCB_DFSR_RES0_W   27U

§ SCB_DFSR_RES0_M

#define SCB_DFSR_RES0_M   0xFFFFFFE0U

§ SCB_DFSR_RES0_S

#define SCB_DFSR_RES0_S   5U

§ SCB_DFSR_EXTERNAL

#define SCB_DFSR_EXTERNAL   0x00000010U

§ SCB_DFSR_EXTERNAL_M

#define SCB_DFSR_EXTERNAL_M   0x00000010U

§ SCB_DFSR_EXTERNAL_S

#define SCB_DFSR_EXTERNAL_S   4U

§ SCB_DFSR_VCATCH

#define SCB_DFSR_VCATCH   0x00000008U

§ SCB_DFSR_VCATCH_M

#define SCB_DFSR_VCATCH_M   0x00000008U

§ SCB_DFSR_VCATCH_S

#define SCB_DFSR_VCATCH_S   3U

§ SCB_DFSR_DWTTRAP

#define SCB_DFSR_DWTTRAP   0x00000004U

§ SCB_DFSR_DWTTRAP_M

#define SCB_DFSR_DWTTRAP_M   0x00000004U

§ SCB_DFSR_DWTTRAP_S

#define SCB_DFSR_DWTTRAP_S   2U

§ SCB_DFSR_BKPT

#define SCB_DFSR_BKPT   0x00000002U

§ SCB_DFSR_BKPT_M

#define SCB_DFSR_BKPT_M   0x00000002U

§ SCB_DFSR_BKPT_S

#define SCB_DFSR_BKPT_S   1U

§ SCB_DFSR_HALTED

#define SCB_DFSR_HALTED   0x00000001U

§ SCB_DFSR_HALTED_M

#define SCB_DFSR_HALTED_M   0x00000001U

§ SCB_DFSR_HALTED_S

#define SCB_DFSR_HALTED_S   0U

§ SCB_MMFAR_ADDRESS_W

#define SCB_MMFAR_ADDRESS_W   32U

§ SCB_MMFAR_ADDRESS_M

#define SCB_MMFAR_ADDRESS_M   0xFFFFFFFFU

§ SCB_MMFAR_ADDRESS_S

#define SCB_MMFAR_ADDRESS_S   0U

§ SCB_BFAR_ADDRESS_W

#define SCB_BFAR_ADDRESS_W   32U

§ SCB_BFAR_ADDRESS_M

#define SCB_BFAR_ADDRESS_M   0xFFFFFFFFU

§ SCB_BFAR_ADDRESS_S

#define SCB_BFAR_ADDRESS_S   0U

§ SCB_AFSR_IMPDEF

#define SCB_AFSR_IMPDEF   0x00000001U

§ SCB_AFSR_IMPDEF_M

#define SCB_AFSR_IMPDEF_M   0x00000001U

§ SCB_AFSR_IMPDEF_S

#define SCB_AFSR_IMPDEF_S   0U

§ SCB_ID_PFR0_RES0_W

#define SCB_ID_PFR0_RES0_W   24U

§ SCB_ID_PFR0_RES0_M

#define SCB_ID_PFR0_RES0_M   0xFFFFFF00U

§ SCB_ID_PFR0_RES0_S

#define SCB_ID_PFR0_RES0_S   8U

§ SCB_ID_PFR0_STATE1_W

#define SCB_ID_PFR0_STATE1_W   4U

§ SCB_ID_PFR0_STATE1_M

#define SCB_ID_PFR0_STATE1_M   0x000000F0U

§ SCB_ID_PFR0_STATE1_S

#define SCB_ID_PFR0_STATE1_S   4U

§ SCB_ID_PFR0_STATE0_W

#define SCB_ID_PFR0_STATE0_W   4U

§ SCB_ID_PFR0_STATE0_M

#define SCB_ID_PFR0_STATE0_M   0x0000000FU

§ SCB_ID_PFR0_STATE0_S

#define SCB_ID_PFR0_STATE0_S   0U

§ SCB_ID_PFR1_RES0_W

#define SCB_ID_PFR1_RES0_W   20U

§ SCB_ID_PFR1_RES0_M

#define SCB_ID_PFR1_RES0_M   0xFFFFF000U

§ SCB_ID_PFR1_RES0_S

#define SCB_ID_PFR1_RES0_S   12U

§ SCB_ID_PFR1_MPROGMOD_W

#define SCB_ID_PFR1_MPROGMOD_W   4U

§ SCB_ID_PFR1_MPROGMOD_M

#define SCB_ID_PFR1_MPROGMOD_M   0x00000F00U

§ SCB_ID_PFR1_MPROGMOD_S

#define SCB_ID_PFR1_MPROGMOD_S   8U

§ SCB_ID_PFR1_SECURITY_W

#define SCB_ID_PFR1_SECURITY_W   4U

§ SCB_ID_PFR1_SECURITY_M

#define SCB_ID_PFR1_SECURITY_M   0x000000F0U

§ SCB_ID_PFR1_SECURITY_S

#define SCB_ID_PFR1_SECURITY_S   4U

§ SCB_ID_PFR1_RES0_1_W

#define SCB_ID_PFR1_RES0_1_W   4U

§ SCB_ID_PFR1_RES0_1_M

#define SCB_ID_PFR1_RES0_1_M   0x0000000FU

§ SCB_ID_PFR1_RES0_1_S

#define SCB_ID_PFR1_RES0_1_S   0U

§ SCB_ID_DFR0_RES0_W

#define SCB_ID_DFR0_RES0_W   8U

§ SCB_ID_DFR0_RES0_M

#define SCB_ID_DFR0_RES0_M   0xFF000000U

§ SCB_ID_DFR0_RES0_S

#define SCB_ID_DFR0_RES0_S   24U

§ SCB_ID_DFR0_MPROFDBG_W

#define SCB_ID_DFR0_MPROFDBG_W   4U

§ SCB_ID_DFR0_MPROFDBG_M

#define SCB_ID_DFR0_MPROFDBG_M   0x00F00000U

§ SCB_ID_DFR0_MPROFDBG_S

#define SCB_ID_DFR0_MPROFDBG_S   20U

§ SCB_ID_DFR0_RES0_1_W

#define SCB_ID_DFR0_RES0_1_W   20U

§ SCB_ID_DFR0_RES0_1_M

#define SCB_ID_DFR0_RES0_1_M   0x000FFFFFU

§ SCB_ID_DFR0_RES0_1_S

#define SCB_ID_DFR0_RES0_1_S   0U

§ SCB_ID_AFR0_RES0_W

#define SCB_ID_AFR0_RES0_W   16U

§ SCB_ID_AFR0_RES0_M

#define SCB_ID_AFR0_RES0_M   0xFFFF0000U

§ SCB_ID_AFR0_RES0_S

#define SCB_ID_AFR0_RES0_S   16U

§ SCB_ID_AFR0_IMPDEF3_W

#define SCB_ID_AFR0_IMPDEF3_W   4U

§ SCB_ID_AFR0_IMPDEF3_M

#define SCB_ID_AFR0_IMPDEF3_M   0x0000F000U

§ SCB_ID_AFR0_IMPDEF3_S

#define SCB_ID_AFR0_IMPDEF3_S   12U

§ SCB_ID_AFR0_IMPDEF2_W

#define SCB_ID_AFR0_IMPDEF2_W   4U

§ SCB_ID_AFR0_IMPDEF2_M

#define SCB_ID_AFR0_IMPDEF2_M   0x00000F00U

§ SCB_ID_AFR0_IMPDEF2_S

#define SCB_ID_AFR0_IMPDEF2_S   8U

§ SCB_ID_AFR0_IMPDEF1_W

#define SCB_ID_AFR0_IMPDEF1_W   4U

§ SCB_ID_AFR0_IMPDEF1_M

#define SCB_ID_AFR0_IMPDEF1_M   0x000000F0U

§ SCB_ID_AFR0_IMPDEF1_S

#define SCB_ID_AFR0_IMPDEF1_S   4U

§ SCB_ID_AFR0_IMPDEF0_W

#define SCB_ID_AFR0_IMPDEF0_W   4U

§ SCB_ID_AFR0_IMPDEF0_M

#define SCB_ID_AFR0_IMPDEF0_M   0x0000000FU

§ SCB_ID_AFR0_IMPDEF0_S

#define SCB_ID_AFR0_IMPDEF0_S   0U

§ SCB_ID_MMFR0_RES0_W

#define SCB_ID_MMFR0_RES0_W   8U

§ SCB_ID_MMFR0_RES0_M

#define SCB_ID_MMFR0_RES0_M   0xFF000000U

§ SCB_ID_MMFR0_RES0_S

#define SCB_ID_MMFR0_RES0_S   24U

§ SCB_ID_MMFR0_AUXREG_W

#define SCB_ID_MMFR0_AUXREG_W   4U

§ SCB_ID_MMFR0_AUXREG_M

#define SCB_ID_MMFR0_AUXREG_M   0x00F00000U

§ SCB_ID_MMFR0_AUXREG_S

#define SCB_ID_MMFR0_AUXREG_S   20U

§ SCB_ID_MMFR0_TCM_W

#define SCB_ID_MMFR0_TCM_W   4U

§ SCB_ID_MMFR0_TCM_M

#define SCB_ID_MMFR0_TCM_M   0x000F0000U

§ SCB_ID_MMFR0_TCM_S

#define SCB_ID_MMFR0_TCM_S   16U

§ SCB_ID_MMFR0_SHARELVL_W

#define SCB_ID_MMFR0_SHARELVL_W   4U

§ SCB_ID_MMFR0_SHARELVL_M

#define SCB_ID_MMFR0_SHARELVL_M   0x0000F000U

§ SCB_ID_MMFR0_SHARELVL_S

#define SCB_ID_MMFR0_SHARELVL_S   12U

§ SCB_ID_MMFR0_OUTERSHR_W

#define SCB_ID_MMFR0_OUTERSHR_W   4U

§ SCB_ID_MMFR0_OUTERSHR_M

#define SCB_ID_MMFR0_OUTERSHR_M   0x00000F00U

§ SCB_ID_MMFR0_OUTERSHR_S

#define SCB_ID_MMFR0_OUTERSHR_S   8U

§ SCB_ID_MMFR0_PMSA_W

#define SCB_ID_MMFR0_PMSA_W   4U

§ SCB_ID_MMFR0_PMSA_M

#define SCB_ID_MMFR0_PMSA_M   0x000000F0U

§ SCB_ID_MMFR0_PMSA_S

#define SCB_ID_MMFR0_PMSA_S   4U

§ SCB_ID_MMFR0_RES0_1_W

#define SCB_ID_MMFR0_RES0_1_W   4U

§ SCB_ID_MMFR0_RES0_1_M

#define SCB_ID_MMFR0_RES0_1_M   0x0000000FU

§ SCB_ID_MMFR0_RES0_1_S

#define SCB_ID_MMFR0_RES0_1_S   0U

§ SCB_ID_MMFR1_RES0_W

#define SCB_ID_MMFR1_RES0_W   32U

§ SCB_ID_MMFR1_RES0_M

#define SCB_ID_MMFR1_RES0_M   0xFFFFFFFFU

§ SCB_ID_MMFR1_RES0_S

#define SCB_ID_MMFR1_RES0_S   0U

§ SCB_ID_MMFR2_RES0_W

#define SCB_ID_MMFR2_RES0_W   4U

§ SCB_ID_MMFR2_RES0_M

#define SCB_ID_MMFR2_RES0_M   0xF0000000U

§ SCB_ID_MMFR2_RES0_S

#define SCB_ID_MMFR2_RES0_S   28U

§ SCB_ID_MMFR2_WFISTALL_W

#define SCB_ID_MMFR2_WFISTALL_W   4U

§ SCB_ID_MMFR2_WFISTALL_M

#define SCB_ID_MMFR2_WFISTALL_M   0x0F000000U

§ SCB_ID_MMFR2_WFISTALL_S

#define SCB_ID_MMFR2_WFISTALL_S   24U

§ SCB_ID_MMFR2_RES0_1_W

#define SCB_ID_MMFR2_RES0_1_W   24U

§ SCB_ID_MMFR2_RES0_1_M

#define SCB_ID_MMFR2_RES0_1_M   0x00FFFFFFU

§ SCB_ID_MMFR2_RES0_1_S

#define SCB_ID_MMFR2_RES0_1_S   0U

§ SCB_ID_MMFR3_RES0_W

#define SCB_ID_MMFR3_RES0_W   20U

§ SCB_ID_MMFR3_RES0_M

#define SCB_ID_MMFR3_RES0_M   0xFFFFF000U

§ SCB_ID_MMFR3_RES0_S

#define SCB_ID_MMFR3_RES0_S   12U

§ SCB_ID_MMFR3_BPMAINT_W

#define SCB_ID_MMFR3_BPMAINT_W   4U

§ SCB_ID_MMFR3_BPMAINT_M

#define SCB_ID_MMFR3_BPMAINT_M   0x00000F00U

§ SCB_ID_MMFR3_BPMAINT_S

#define SCB_ID_MMFR3_BPMAINT_S   8U

§ SCB_ID_MMFR3_CMAINTSW_W

#define SCB_ID_MMFR3_CMAINTSW_W   4U

§ SCB_ID_MMFR3_CMAINTSW_M

#define SCB_ID_MMFR3_CMAINTSW_M   0x000000F0U

§ SCB_ID_MMFR3_CMAINTSW_S

#define SCB_ID_MMFR3_CMAINTSW_S   4U

§ SCB_ID_MMFR3_CMAINTVA_W

#define SCB_ID_MMFR3_CMAINTVA_W   4U

§ SCB_ID_MMFR3_CMAINTVA_M

#define SCB_ID_MMFR3_CMAINTVA_M   0x0000000FU

§ SCB_ID_MMFR3_CMAINTVA_S

#define SCB_ID_MMFR3_CMAINTVA_S   0U

§ SCB_ID_ISAR0_RES0_W

#define SCB_ID_ISAR0_RES0_W   4U

§ SCB_ID_ISAR0_RES0_M

#define SCB_ID_ISAR0_RES0_M   0xF0000000U

§ SCB_ID_ISAR0_RES0_S

#define SCB_ID_ISAR0_RES0_S   28U

§ SCB_ID_ISAR0_DIVIDE_W

#define SCB_ID_ISAR0_DIVIDE_W   4U

§ SCB_ID_ISAR0_DIVIDE_M

#define SCB_ID_ISAR0_DIVIDE_M   0x0F000000U

§ SCB_ID_ISAR0_DIVIDE_S

#define SCB_ID_ISAR0_DIVIDE_S   24U

§ SCB_ID_ISAR0_DEBUG_W

#define SCB_ID_ISAR0_DEBUG_W   4U

§ SCB_ID_ISAR0_DEBUG_M

#define SCB_ID_ISAR0_DEBUG_M   0x00F00000U

§ SCB_ID_ISAR0_DEBUG_S

#define SCB_ID_ISAR0_DEBUG_S   20U

§ SCB_ID_ISAR0_COPROC_W

#define SCB_ID_ISAR0_COPROC_W   4U

§ SCB_ID_ISAR0_COPROC_M

#define SCB_ID_ISAR0_COPROC_M   0x000F0000U

§ SCB_ID_ISAR0_COPROC_S

#define SCB_ID_ISAR0_COPROC_S   16U

§ SCB_ID_ISAR0_CMPBRANCH_W

#define SCB_ID_ISAR0_CMPBRANCH_W   4U

§ SCB_ID_ISAR0_CMPBRANCH_M

#define SCB_ID_ISAR0_CMPBRANCH_M   0x0000F000U

§ SCB_ID_ISAR0_CMPBRANCH_S

#define SCB_ID_ISAR0_CMPBRANCH_S   12U

§ SCB_ID_ISAR0_BITFIELD_W

#define SCB_ID_ISAR0_BITFIELD_W   4U

§ SCB_ID_ISAR0_BITFIELD_M

#define SCB_ID_ISAR0_BITFIELD_M   0x00000F00U

§ SCB_ID_ISAR0_BITFIELD_S

#define SCB_ID_ISAR0_BITFIELD_S   8U

§ SCB_ID_ISAR0_BITCOUNT_W

#define SCB_ID_ISAR0_BITCOUNT_W   4U

§ SCB_ID_ISAR0_BITCOUNT_M

#define SCB_ID_ISAR0_BITCOUNT_M   0x000000F0U

§ SCB_ID_ISAR0_BITCOUNT_S

#define SCB_ID_ISAR0_BITCOUNT_S   4U

§ SCB_ID_ISAR0_RES0_1_W

#define SCB_ID_ISAR0_RES0_1_W   4U

§ SCB_ID_ISAR0_RES0_1_M

#define SCB_ID_ISAR0_RES0_1_M   0x0000000FU

§ SCB_ID_ISAR0_RES0_1_S

#define SCB_ID_ISAR0_RES0_1_S   0U

§ SCB_ID_ISAR1_RES0_W

#define SCB_ID_ISAR1_RES0_W   4U

§ SCB_ID_ISAR1_RES0_M

#define SCB_ID_ISAR1_RES0_M   0xF0000000U

§ SCB_ID_ISAR1_RES0_S

#define SCB_ID_ISAR1_RES0_S   28U

§ SCB_ID_ISAR1_INTERWORK_W

#define SCB_ID_ISAR1_INTERWORK_W   4U

§ SCB_ID_ISAR1_INTERWORK_M

#define SCB_ID_ISAR1_INTERWORK_M   0x0F000000U

§ SCB_ID_ISAR1_INTERWORK_S

#define SCB_ID_ISAR1_INTERWORK_S   24U

§ SCB_ID_ISAR1_IMMEDIATE_W

#define SCB_ID_ISAR1_IMMEDIATE_W   4U

§ SCB_ID_ISAR1_IMMEDIATE_M

#define SCB_ID_ISAR1_IMMEDIATE_M   0x00F00000U

§ SCB_ID_ISAR1_IMMEDIATE_S

#define SCB_ID_ISAR1_IMMEDIATE_S   20U

§ SCB_ID_ISAR1_IFTHEN_W

#define SCB_ID_ISAR1_IFTHEN_W   4U

§ SCB_ID_ISAR1_IFTHEN_M

#define SCB_ID_ISAR1_IFTHEN_M   0x000F0000U

§ SCB_ID_ISAR1_IFTHEN_S

#define SCB_ID_ISAR1_IFTHEN_S   16U

§ SCB_ID_ISAR1_EXTEND_W

#define SCB_ID_ISAR1_EXTEND_W   4U

§ SCB_ID_ISAR1_EXTEND_M

#define SCB_ID_ISAR1_EXTEND_M   0x0000F000U

§ SCB_ID_ISAR1_EXTEND_S

#define SCB_ID_ISAR1_EXTEND_S   12U

§ SCB_ID_ISAR1_RES0_1_W

#define SCB_ID_ISAR1_RES0_1_W   12U

§ SCB_ID_ISAR1_RES0_1_M

#define SCB_ID_ISAR1_RES0_1_M   0x00000FFFU

§ SCB_ID_ISAR1_RES0_1_S

#define SCB_ID_ISAR1_RES0_1_S   0U

§ SCB_ID_ISAR2_REVERSAL_W

#define SCB_ID_ISAR2_REVERSAL_W   4U

§ SCB_ID_ISAR2_REVERSAL_M

#define SCB_ID_ISAR2_REVERSAL_M   0xF0000000U

§ SCB_ID_ISAR2_REVERSAL_S

#define SCB_ID_ISAR2_REVERSAL_S   28U

§ SCB_ID_ISAR2_RES0_W

#define SCB_ID_ISAR2_RES0_W   4U

§ SCB_ID_ISAR2_RES0_M

#define SCB_ID_ISAR2_RES0_M   0x0F000000U

§ SCB_ID_ISAR2_RES0_S

#define SCB_ID_ISAR2_RES0_S   24U

§ SCB_ID_ISAR2_MULTU_W

#define SCB_ID_ISAR2_MULTU_W   4U

§ SCB_ID_ISAR2_MULTU_M

#define SCB_ID_ISAR2_MULTU_M   0x00F00000U

§ SCB_ID_ISAR2_MULTU_S

#define SCB_ID_ISAR2_MULTU_S   20U

§ SCB_ID_ISAR2_MULTS_W

#define SCB_ID_ISAR2_MULTS_W   4U

§ SCB_ID_ISAR2_MULTS_M

#define SCB_ID_ISAR2_MULTS_M   0x000F0000U

§ SCB_ID_ISAR2_MULTS_S

#define SCB_ID_ISAR2_MULTS_S   16U

§ SCB_ID_ISAR2_MULT_W

#define SCB_ID_ISAR2_MULT_W   4U

§ SCB_ID_ISAR2_MULT_M

#define SCB_ID_ISAR2_MULT_M   0x0000F000U

§ SCB_ID_ISAR2_MULT_S

#define SCB_ID_ISAR2_MULT_S   12U

§ SCB_ID_ISAR2_MULTIACCESSINT_W

#define SCB_ID_ISAR2_MULTIACCESSINT_W   4U

§ SCB_ID_ISAR2_MULTIACCESSINT_M

#define SCB_ID_ISAR2_MULTIACCESSINT_M   0x00000F00U

§ SCB_ID_ISAR2_MULTIACCESSINT_S

#define SCB_ID_ISAR2_MULTIACCESSINT_S   8U

§ SCB_ID_ISAR2_MEMHINT_W

#define SCB_ID_ISAR2_MEMHINT_W   4U

§ SCB_ID_ISAR2_MEMHINT_M

#define SCB_ID_ISAR2_MEMHINT_M   0x000000F0U

§ SCB_ID_ISAR2_MEMHINT_S

#define SCB_ID_ISAR2_MEMHINT_S   4U

§ SCB_ID_ISAR2_LOADSTORE_W

#define SCB_ID_ISAR2_LOADSTORE_W   4U

§ SCB_ID_ISAR2_LOADSTORE_M

#define SCB_ID_ISAR2_LOADSTORE_M   0x0000000FU

§ SCB_ID_ISAR2_LOADSTORE_S

#define SCB_ID_ISAR2_LOADSTORE_S   0U

§ SCB_ID_ISAR3_RES0_W

#define SCB_ID_ISAR3_RES0_W   4U

§ SCB_ID_ISAR3_RES0_M

#define SCB_ID_ISAR3_RES0_M   0xF0000000U

§ SCB_ID_ISAR3_RES0_S

#define SCB_ID_ISAR3_RES0_S   28U

§ SCB_ID_ISAR3_TRUENOP_W

#define SCB_ID_ISAR3_TRUENOP_W   4U

§ SCB_ID_ISAR3_TRUENOP_M

#define SCB_ID_ISAR3_TRUENOP_M   0x0F000000U

§ SCB_ID_ISAR3_TRUENOP_S

#define SCB_ID_ISAR3_TRUENOP_S   24U

§ SCB_ID_ISAR3_T32COPY_W

#define SCB_ID_ISAR3_T32COPY_W   4U

§ SCB_ID_ISAR3_T32COPY_M

#define SCB_ID_ISAR3_T32COPY_M   0x00F00000U

§ SCB_ID_ISAR3_T32COPY_S

#define SCB_ID_ISAR3_T32COPY_S   20U

§ SCB_ID_ISAR3_TABBRANCH_W

#define SCB_ID_ISAR3_TABBRANCH_W   4U

§ SCB_ID_ISAR3_TABBRANCH_M

#define SCB_ID_ISAR3_TABBRANCH_M   0x000F0000U

§ SCB_ID_ISAR3_TABBRANCH_S

#define SCB_ID_ISAR3_TABBRANCH_S   16U

§ SCB_ID_ISAR3_SYNCHPRIM_W

#define SCB_ID_ISAR3_SYNCHPRIM_W   4U

§ SCB_ID_ISAR3_SYNCHPRIM_M

#define SCB_ID_ISAR3_SYNCHPRIM_M   0x0000F000U

§ SCB_ID_ISAR3_SYNCHPRIM_S

#define SCB_ID_ISAR3_SYNCHPRIM_S   12U

§ SCB_ID_ISAR3_SVC_W

#define SCB_ID_ISAR3_SVC_W   4U

§ SCB_ID_ISAR3_SVC_M

#define SCB_ID_ISAR3_SVC_M   0x00000F00U

§ SCB_ID_ISAR3_SVC_S

#define SCB_ID_ISAR3_SVC_S   8U

§ SCB_ID_ISAR3_SIMD_W

#define SCB_ID_ISAR3_SIMD_W   4U

§ SCB_ID_ISAR3_SIMD_M

#define SCB_ID_ISAR3_SIMD_M   0x000000F0U

§ SCB_ID_ISAR3_SIMD_S

#define SCB_ID_ISAR3_SIMD_S   4U

§ SCB_ID_ISAR3_SATURATE_W

#define SCB_ID_ISAR3_SATURATE_W   4U

§ SCB_ID_ISAR3_SATURATE_M

#define SCB_ID_ISAR3_SATURATE_M   0x0000000FU

§ SCB_ID_ISAR3_SATURATE_S

#define SCB_ID_ISAR3_SATURATE_S   0U

§ SCB_ID_ISAR4_RES0_W

#define SCB_ID_ISAR4_RES0_W   4U

§ SCB_ID_ISAR4_RES0_M

#define SCB_ID_ISAR4_RES0_M   0xF0000000U

§ SCB_ID_ISAR4_RES0_S

#define SCB_ID_ISAR4_RES0_S   28U

§ SCB_ID_ISAR4_PSR_M_W

#define SCB_ID_ISAR4_PSR_M_W   4U

§ SCB_ID_ISAR4_PSR_M_M

#define SCB_ID_ISAR4_PSR_M_M   0x0F000000U

§ SCB_ID_ISAR4_PSR_M_S

#define SCB_ID_ISAR4_PSR_M_S   24U

§ SCB_ID_ISAR4_SYNCPRIM_FRAC_W

#define SCB_ID_ISAR4_SYNCPRIM_FRAC_W   4U

§ SCB_ID_ISAR4_SYNCPRIM_FRAC_M

#define SCB_ID_ISAR4_SYNCPRIM_FRAC_M   0x00F00000U

§ SCB_ID_ISAR4_SYNCPRIM_FRAC_S

#define SCB_ID_ISAR4_SYNCPRIM_FRAC_S   20U

§ SCB_ID_ISAR4_BARRIER_W

#define SCB_ID_ISAR4_BARRIER_W   4U

§ SCB_ID_ISAR4_BARRIER_M

#define SCB_ID_ISAR4_BARRIER_M   0x000F0000U

§ SCB_ID_ISAR4_BARRIER_S

#define SCB_ID_ISAR4_BARRIER_S   16U

§ SCB_ID_ISAR4_RES0_1_W

#define SCB_ID_ISAR4_RES0_1_W   4U

§ SCB_ID_ISAR4_RES0_1_M

#define SCB_ID_ISAR4_RES0_1_M   0x0000F000U

§ SCB_ID_ISAR4_RES0_1_S

#define SCB_ID_ISAR4_RES0_1_S   12U

§ SCB_ID_ISAR4_WRITEBACK_W

#define SCB_ID_ISAR4_WRITEBACK_W   4U

§ SCB_ID_ISAR4_WRITEBACK_M

#define SCB_ID_ISAR4_WRITEBACK_M   0x00000F00U

§ SCB_ID_ISAR4_WRITEBACK_S

#define SCB_ID_ISAR4_WRITEBACK_S   8U

§ SCB_ID_ISAR4_WITHSHIFTS_W

#define SCB_ID_ISAR4_WITHSHIFTS_W   4U

§ SCB_ID_ISAR4_WITHSHIFTS_M

#define SCB_ID_ISAR4_WITHSHIFTS_M   0x000000F0U

§ SCB_ID_ISAR4_WITHSHIFTS_S

#define SCB_ID_ISAR4_WITHSHIFTS_S   4U

§ SCB_ID_ISAR4_UNPRIV_W

#define SCB_ID_ISAR4_UNPRIV_W   4U

§ SCB_ID_ISAR4_UNPRIV_M

#define SCB_ID_ISAR4_UNPRIV_M   0x0000000FU

§ SCB_ID_ISAR4_UNPRIV_S

#define SCB_ID_ISAR4_UNPRIV_S   0U

§ SCB_ID_ISAR5_RES0_W

#define SCB_ID_ISAR5_RES0_W   32U

§ SCB_ID_ISAR5_RES0_M

#define SCB_ID_ISAR5_RES0_M   0xFFFFFFFFU

§ SCB_ID_ISAR5_RES0_S

#define SCB_ID_ISAR5_RES0_S   0U

§ SCB_CLIDR_ICB_W

#define SCB_CLIDR_ICB_W   2U

§ SCB_CLIDR_ICB_M

#define SCB_CLIDR_ICB_M   0xC0000000U

§ SCB_CLIDR_ICB_S

#define SCB_CLIDR_ICB_S   30U

§ SCB_CLIDR_ICB_L3

#define SCB_CLIDR_ICB_L3   0xC0000000U

§ SCB_CLIDR_ICB_L2

#define SCB_CLIDR_ICB_L2   0x80000000U

§ SCB_CLIDR_ICB_L1

#define SCB_CLIDR_ICB_L1   0x40000000U

§ SCB_CLIDR_ICB_NA

#define SCB_CLIDR_ICB_NA   0x00000000U

§ SCB_CLIDR_LOUU_W

#define SCB_CLIDR_LOUU_W   3U

§ SCB_CLIDR_LOUU_M

#define SCB_CLIDR_LOUU_M   0x38000000U

§ SCB_CLIDR_LOUU_S

#define SCB_CLIDR_LOUU_S   27U

§ SCB_CLIDR_LOC_W

#define SCB_CLIDR_LOC_W   3U

§ SCB_CLIDR_LOC_M

#define SCB_CLIDR_LOC_M   0x07000000U

§ SCB_CLIDR_LOC_S

#define SCB_CLIDR_LOC_S   24U

§ SCB_CLIDR_LOUIS_W

#define SCB_CLIDR_LOUIS_W   3U

§ SCB_CLIDR_LOUIS_M

#define SCB_CLIDR_LOUIS_M   0x00E00000U

§ SCB_CLIDR_LOUIS_S

#define SCB_CLIDR_LOUIS_S   21U

§ SCB_CLIDR_CTYPE7_W

#define SCB_CLIDR_CTYPE7_W   3U

§ SCB_CLIDR_CTYPE7_M

#define SCB_CLIDR_CTYPE7_M   0x001C0000U

§ SCB_CLIDR_CTYPE7_S

#define SCB_CLIDR_CTYPE7_S   18U

§ SCB_CLIDR_CTYPE7_BOTH_UNIFIED

#define SCB_CLIDR_CTYPE7_BOTH_UNIFIED   0x00100000U

§ SCB_CLIDR_CTYPE7_BOTH_SEP

#define SCB_CLIDR_CTYPE7_BOTH_SEP   0x000C0000U

§ SCB_CLIDR_CTYPE7_DATA

#define SCB_CLIDR_CTYPE7_DATA   0x00080000U

§ SCB_CLIDR_CTYPE7_INSTR

#define SCB_CLIDR_CTYPE7_INSTR   0x00040000U

§ SCB_CLIDR_CTYPE7_NO_CACHE

#define SCB_CLIDR_CTYPE7_NO_CACHE   0x00000000U

§ SCB_CLIDR_CTYPE6_W

#define SCB_CLIDR_CTYPE6_W   3U

§ SCB_CLIDR_CTYPE6_M

#define SCB_CLIDR_CTYPE6_M   0x00038000U

§ SCB_CLIDR_CTYPE6_S

#define SCB_CLIDR_CTYPE6_S   15U

§ SCB_CLIDR_CTYPE6_BOTH_UNIFIED

#define SCB_CLIDR_CTYPE6_BOTH_UNIFIED   0x00020000U

§ SCB_CLIDR_CTYPE6_BOTH_SEP

#define SCB_CLIDR_CTYPE6_BOTH_SEP   0x00018000U

§ SCB_CLIDR_CTYPE6_DATA

#define SCB_CLIDR_CTYPE6_DATA   0x00010000U

§ SCB_CLIDR_CTYPE6_INSTR

#define SCB_CLIDR_CTYPE6_INSTR   0x00008000U

§ SCB_CLIDR_CTYPE6_NO_CACHE

#define SCB_CLIDR_CTYPE6_NO_CACHE   0x00000000U

§ SCB_CLIDR_CTYPE5_W

#define SCB_CLIDR_CTYPE5_W   3U

§ SCB_CLIDR_CTYPE5_M

#define SCB_CLIDR_CTYPE5_M   0x00007000U

§ SCB_CLIDR_CTYPE5_S

#define SCB_CLIDR_CTYPE5_S   12U

§ SCB_CLIDR_CTYPE5_BOTH_UNIFIED

#define SCB_CLIDR_CTYPE5_BOTH_UNIFIED   0x00004000U

§ SCB_CLIDR_CTYPE5_BOTH_SEP

#define SCB_CLIDR_CTYPE5_BOTH_SEP   0x00003000U

§ SCB_CLIDR_CTYPE5_DATA

#define SCB_CLIDR_CTYPE5_DATA   0x00002000U

§ SCB_CLIDR_CTYPE5_INSTR

#define SCB_CLIDR_CTYPE5_INSTR   0x00001000U

§ SCB_CLIDR_CTYPE5_NO_CACHE

#define SCB_CLIDR_CTYPE5_NO_CACHE   0x00000000U

§ SCB_CLIDR_CTYPE4_W

#define SCB_CLIDR_CTYPE4_W   3U

§ SCB_CLIDR_CTYPE4_M

#define SCB_CLIDR_CTYPE4_M   0x00000E00U

§ SCB_CLIDR_CTYPE4_S

#define SCB_CLIDR_CTYPE4_S   9U

§ SCB_CLIDR_CTYPE4_BOTH_UNIFIED

#define SCB_CLIDR_CTYPE4_BOTH_UNIFIED   0x00000800U

§ SCB_CLIDR_CTYPE4_BOTH_SEP

#define SCB_CLIDR_CTYPE4_BOTH_SEP   0x00000600U

§ SCB_CLIDR_CTYPE4_DATA

#define SCB_CLIDR_CTYPE4_DATA   0x00000400U

§ SCB_CLIDR_CTYPE4_INSTR

#define SCB_CLIDR_CTYPE4_INSTR   0x00000200U

§ SCB_CLIDR_CTYPE4_NO_CACHE

#define SCB_CLIDR_CTYPE4_NO_CACHE   0x00000000U

§ SCB_CLIDR_CTYPE3_W

#define SCB_CLIDR_CTYPE3_W   3U

§ SCB_CLIDR_CTYPE3_M

#define SCB_CLIDR_CTYPE3_M   0x000001C0U

§ SCB_CLIDR_CTYPE3_S

#define SCB_CLIDR_CTYPE3_S   6U

§ SCB_CLIDR_CTYPE3_BOTH_UNIFIED

#define SCB_CLIDR_CTYPE3_BOTH_UNIFIED   0x00000100U

§ SCB_CLIDR_CTYPE3_BOTH_SEP

#define SCB_CLIDR_CTYPE3_BOTH_SEP   0x000000C0U

§ SCB_CLIDR_CTYPE3_DATA

#define SCB_CLIDR_CTYPE3_DATA   0x00000080U

§ SCB_CLIDR_CTYPE3_INSTR

#define SCB_CLIDR_CTYPE3_INSTR   0x00000040U

§ SCB_CLIDR_CTYPE3_NO_CACHE

#define SCB_CLIDR_CTYPE3_NO_CACHE   0x00000000U

§ SCB_CLIDR_CTYPE2_W

#define SCB_CLIDR_CTYPE2_W   3U

§ SCB_CLIDR_CTYPE2_M

#define SCB_CLIDR_CTYPE2_M   0x00000038U

§ SCB_CLIDR_CTYPE2_S

#define SCB_CLIDR_CTYPE2_S   3U

§ SCB_CLIDR_CTYPE2_BOTH_UNIFIED

#define SCB_CLIDR_CTYPE2_BOTH_UNIFIED   0x00000020U

§ SCB_CLIDR_CTYPE2_BOTH_SEP

#define SCB_CLIDR_CTYPE2_BOTH_SEP   0x00000018U

§ SCB_CLIDR_CTYPE2_DATA

#define SCB_CLIDR_CTYPE2_DATA   0x00000010U

§ SCB_CLIDR_CTYPE2_INSTR

#define SCB_CLIDR_CTYPE2_INSTR   0x00000008U

§ SCB_CLIDR_CTYPE2_NO_CACHE

#define SCB_CLIDR_CTYPE2_NO_CACHE   0x00000000U

§ SCB_CLIDR_CTYPE1_W

#define SCB_CLIDR_CTYPE1_W   3U

§ SCB_CLIDR_CTYPE1_M

#define SCB_CLIDR_CTYPE1_M   0x00000007U

§ SCB_CLIDR_CTYPE1_S

#define SCB_CLIDR_CTYPE1_S   0U

§ SCB_CLIDR_CTYPE1_BOTH_UNIFIED

#define SCB_CLIDR_CTYPE1_BOTH_UNIFIED   0x00000004U

§ SCB_CLIDR_CTYPE1_BOTH_SEP

#define SCB_CLIDR_CTYPE1_BOTH_SEP   0x00000003U

§ SCB_CLIDR_CTYPE1_DATA

#define SCB_CLIDR_CTYPE1_DATA   0x00000002U

§ SCB_CLIDR_CTYPE1_INSTR

#define SCB_CLIDR_CTYPE1_INSTR   0x00000001U

§ SCB_CLIDR_CTYPE1_NO_CACHE

#define SCB_CLIDR_CTYPE1_NO_CACHE   0x00000000U

§ SCB_CTR_RES1

#define SCB_CTR_RES1   0x80000000U

§ SCB_CTR_RES1_M

#define SCB_CTR_RES1_M   0x80000000U

§ SCB_CTR_RES1_S

#define SCB_CTR_RES1_S   31U

§ SCB_CTR_RES0_W

#define SCB_CTR_RES0_W   3U

§ SCB_CTR_RES0_M

#define SCB_CTR_RES0_M   0x70000000U

§ SCB_CTR_RES0_S

#define SCB_CTR_RES0_S   28U

§ SCB_CTR_CWG_W

#define SCB_CTR_CWG_W   4U

§ SCB_CTR_CWG_M

#define SCB_CTR_CWG_M   0x0F000000U

§ SCB_CTR_CWG_S

#define SCB_CTR_CWG_S   24U

§ SCB_CTR_ERG_W

#define SCB_CTR_ERG_W   4U

§ SCB_CTR_ERG_M

#define SCB_CTR_ERG_M   0x00F00000U

§ SCB_CTR_ERG_S

#define SCB_CTR_ERG_S   20U

§ SCB_CTR_DMINLINE_W

#define SCB_CTR_DMINLINE_W   4U

§ SCB_CTR_DMINLINE_M

#define SCB_CTR_DMINLINE_M   0x000F0000U

§ SCB_CTR_DMINLINE_S

#define SCB_CTR_DMINLINE_S   16U

§ SCB_CTR_RES1_1_W

#define SCB_CTR_RES1_1_W   2U

§ SCB_CTR_RES1_1_M

#define SCB_CTR_RES1_1_M   0x0000C000U

§ SCB_CTR_RES1_1_S

#define SCB_CTR_RES1_1_S   14U

§ SCB_CTR_RES0_1_W

#define SCB_CTR_RES0_1_W   10U

§ SCB_CTR_RES0_1_M

#define SCB_CTR_RES0_1_M   0x00003FF0U

§ SCB_CTR_RES0_1_S

#define SCB_CTR_RES0_1_S   4U

§ SCB_CTR_IMINLINE_W

#define SCB_CTR_IMINLINE_W   4U

§ SCB_CTR_IMINLINE_M

#define SCB_CTR_IMINLINE_M   0x0000000FU

§ SCB_CTR_IMINLINE_S

#define SCB_CTR_IMINLINE_S   0U

§ SCB_CCSIDR_WT

#define SCB_CCSIDR_WT   0x80000000U

§ SCB_CCSIDR_WT_M

#define SCB_CCSIDR_WT_M   0x80000000U

§ SCB_CCSIDR_WT_S

#define SCB_CCSIDR_WT_S   31U

§ SCB_CCSIDR_WT_SUPPORTED

#define SCB_CCSIDR_WT_SUPPORTED   0x80000000U

§ SCB_CCSIDR_WT_NOT_SUPPORTED

#define SCB_CCSIDR_WT_NOT_SUPPORTED   0x00000000U

§ SCB_CCSIDR_WB

#define SCB_CCSIDR_WB   0x40000000U

§ SCB_CCSIDR_WB_M

#define SCB_CCSIDR_WB_M   0x40000000U

§ SCB_CCSIDR_WB_S

#define SCB_CCSIDR_WB_S   30U

§ SCB_CCSIDR_WB_SUPPORTED

#define SCB_CCSIDR_WB_SUPPORTED   0x40000000U

§ SCB_CCSIDR_WB_NOT_SUPPORTED

#define SCB_CCSIDR_WB_NOT_SUPPORTED   0x00000000U

§ SCB_CCSIDR_RA

#define SCB_CCSIDR_RA   0x20000000U

§ SCB_CCSIDR_RA_M

#define SCB_CCSIDR_RA_M   0x20000000U

§ SCB_CCSIDR_RA_S

#define SCB_CCSIDR_RA_S   29U

§ SCB_CCSIDR_RA_SUPPORTED

#define SCB_CCSIDR_RA_SUPPORTED   0x20000000U

§ SCB_CCSIDR_RA_NOT_SUPPORTED

#define SCB_CCSIDR_RA_NOT_SUPPORTED   0x00000000U

§ SCB_CCSIDR_WA

#define SCB_CCSIDR_WA   0x10000000U

§ SCB_CCSIDR_WA_M

#define SCB_CCSIDR_WA_M   0x10000000U

§ SCB_CCSIDR_WA_S

#define SCB_CCSIDR_WA_S   28U

§ SCB_CCSIDR_WA_SUPPORTED

#define SCB_CCSIDR_WA_SUPPORTED   0x10000000U

§ SCB_CCSIDR_WA_NOT_SUPPORTED

#define SCB_CCSIDR_WA_NOT_SUPPORTED   0x00000000U

§ SCB_CCSIDR_NUMSETS_W

#define SCB_CCSIDR_NUMSETS_W   15U

§ SCB_CCSIDR_NUMSETS_M

#define SCB_CCSIDR_NUMSETS_M   0x0FFFE000U

§ SCB_CCSIDR_NUMSETS_S

#define SCB_CCSIDR_NUMSETS_S   13U

§ SCB_CCSIDR_ASSOCIATIVITY_W

#define SCB_CCSIDR_ASSOCIATIVITY_W   10U

§ SCB_CCSIDR_ASSOCIATIVITY_M

#define SCB_CCSIDR_ASSOCIATIVITY_M   0x00001FF8U

§ SCB_CCSIDR_ASSOCIATIVITY_S

#define SCB_CCSIDR_ASSOCIATIVITY_S   3U

§ SCB_CCSIDR_LINESIZE_W

#define SCB_CCSIDR_LINESIZE_W   3U

§ SCB_CCSIDR_LINESIZE_M

#define SCB_CCSIDR_LINESIZE_M   0x00000007U

§ SCB_CCSIDR_LINESIZE_S

#define SCB_CCSIDR_LINESIZE_S   0U

§ SCB_CSSELR_RES0_W

#define SCB_CSSELR_RES0_W   28U

§ SCB_CSSELR_RES0_M

#define SCB_CSSELR_RES0_M   0xFFFFFFF0U

§ SCB_CSSELR_RES0_S

#define SCB_CSSELR_RES0_S   4U

§ SCB_CSSELR_LEVEL_W

#define SCB_CSSELR_LEVEL_W   3U

§ SCB_CSSELR_LEVEL_M

#define SCB_CSSELR_LEVEL_M   0x0000000EU

§ SCB_CSSELR_LEVEL_S

#define SCB_CSSELR_LEVEL_S   1U

§ SCB_CSSELR_LEVEL_L7

#define SCB_CSSELR_LEVEL_L7   0x0000000CU

§ SCB_CSSELR_LEVEL_L6

#define SCB_CSSELR_LEVEL_L6   0x0000000AU

§ SCB_CSSELR_LEVEL_L5

#define SCB_CSSELR_LEVEL_L5   0x00000008U

§ SCB_CSSELR_LEVEL_L4

#define SCB_CSSELR_LEVEL_L4   0x00000006U

§ SCB_CSSELR_LEVEL_L3

#define SCB_CSSELR_LEVEL_L3   0x00000004U

§ SCB_CSSELR_LEVEL_L2

#define SCB_CSSELR_LEVEL_L2   0x00000002U

§ SCB_CSSELR_LEVEL_L1

#define SCB_CSSELR_LEVEL_L1   0x00000000U

§ SCB_CSSELR_IND

#define SCB_CSSELR_IND   0x00000001U

§ SCB_CSSELR_IND_M

#define SCB_CSSELR_IND_M   0x00000001U

§ SCB_CSSELR_IND_S

#define SCB_CSSELR_IND_S   0U

§ SCB_CSSELR_IND_INSTR

#define SCB_CSSELR_IND_INSTR   0x00000001U

§ SCB_CSSELR_IND_DATA

#define SCB_CSSELR_IND_DATA   0x00000000U

§ SCB_CPACR_RES0_W

#define SCB_CPACR_RES0_W   8U

§ SCB_CPACR_RES0_M

#define SCB_CPACR_RES0_M   0xFF000000U

§ SCB_CPACR_RES0_S

#define SCB_CPACR_RES0_S   24U

§ SCB_CPACR_CP11_W

#define SCB_CPACR_CP11_W   2U

§ SCB_CPACR_CP11_M

#define SCB_CPACR_CP11_M   0x00C00000U

§ SCB_CPACR_CP11_S

#define SCB_CPACR_CP11_S   22U

§ SCB_CPACR_CP10_W

#define SCB_CPACR_CP10_W   2U

§ SCB_CPACR_CP10_M

#define SCB_CPACR_CP10_M   0x00300000U

§ SCB_CPACR_CP10_S

#define SCB_CPACR_CP10_S   20U

§ SCB_CPACR_RES0_1_W

#define SCB_CPACR_RES0_1_W   4U

§ SCB_CPACR_RES0_1_M

#define SCB_CPACR_RES0_1_M   0x000F0000U

§ SCB_CPACR_RES0_1_S

#define SCB_CPACR_RES0_1_S   16U

§ SCB_CPACR_CP7_W

#define SCB_CPACR_CP7_W   2U

§ SCB_CPACR_CP7_M

#define SCB_CPACR_CP7_M   0x0000C000U

§ SCB_CPACR_CP7_S

#define SCB_CPACR_CP7_S   14U

§ SCB_CPACR_CP6_W

#define SCB_CPACR_CP6_W   2U

§ SCB_CPACR_CP6_M

#define SCB_CPACR_CP6_M   0x00003000U

§ SCB_CPACR_CP6_S

#define SCB_CPACR_CP6_S   12U

§ SCB_CPACR_CP5_W

#define SCB_CPACR_CP5_W   2U

§ SCB_CPACR_CP5_M

#define SCB_CPACR_CP5_M   0x00000C00U

§ SCB_CPACR_CP5_S

#define SCB_CPACR_CP5_S   10U

§ SCB_CPACR_CP4_W

#define SCB_CPACR_CP4_W   2U

§ SCB_CPACR_CP4_M

#define SCB_CPACR_CP4_M   0x00000300U

§ SCB_CPACR_CP4_S

#define SCB_CPACR_CP4_S   8U

§ SCB_CPACR_CP3_W

#define SCB_CPACR_CP3_W   2U

§ SCB_CPACR_CP3_M

#define SCB_CPACR_CP3_M   0x000000C0U

§ SCB_CPACR_CP3_S

#define SCB_CPACR_CP3_S   6U

§ SCB_CPACR_CP2_W

#define SCB_CPACR_CP2_W   2U

§ SCB_CPACR_CP2_M

#define SCB_CPACR_CP2_M   0x00000030U

§ SCB_CPACR_CP2_S

#define SCB_CPACR_CP2_S   4U

§ SCB_CPACR_CP1_W

#define SCB_CPACR_CP1_W   2U

§ SCB_CPACR_CP1_M

#define SCB_CPACR_CP1_M   0x0000000CU

§ SCB_CPACR_CP1_S

#define SCB_CPACR_CP1_S   2U

§ SCB_CPACR_CP0_W

#define SCB_CPACR_CP0_W   2U

§ SCB_CPACR_CP0_M

#define SCB_CPACR_CP0_M   0x00000003U

§ SCB_CPACR_CP0_S

#define SCB_CPACR_CP0_S   0U

§ SCB_NSACR_RES0_W

#define SCB_NSACR_RES0_W   20U

§ SCB_NSACR_RES0_M

#define SCB_NSACR_RES0_M   0xFFFFF000U

§ SCB_NSACR_RES0_S

#define SCB_NSACR_RES0_S   12U

§ SCB_NSACR_CP11

#define SCB_NSACR_CP11   0x00000800U

§ SCB_NSACR_CP11_M

#define SCB_NSACR_CP11_M   0x00000800U

§ SCB_NSACR_CP11_S

#define SCB_NSACR_CP11_S   11U

§ SCB_NSACR_CP10

#define SCB_NSACR_CP10   0x00000400U

§ SCB_NSACR_CP10_M

#define SCB_NSACR_CP10_M   0x00000400U

§ SCB_NSACR_CP10_S

#define SCB_NSACR_CP10_S   10U

§ SCB_NSACR_RES0_1_W

#define SCB_NSACR_RES0_1_W   2U

§ SCB_NSACR_RES0_1_M

#define SCB_NSACR_RES0_1_M   0x00000300U

§ SCB_NSACR_RES0_1_S

#define SCB_NSACR_RES0_1_S   8U

§ SCB_NSACR_CP7

#define SCB_NSACR_CP7   0x00000080U

§ SCB_NSACR_CP7_M

#define SCB_NSACR_CP7_M   0x00000080U

§ SCB_NSACR_CP7_S

#define SCB_NSACR_CP7_S   7U

§ SCB_NSACR_CP6

#define SCB_NSACR_CP6   0x00000040U

§ SCB_NSACR_CP6_M

#define SCB_NSACR_CP6_M   0x00000040U

§ SCB_NSACR_CP6_S

#define SCB_NSACR_CP6_S   6U

§ SCB_NSACR_CP5

#define SCB_NSACR_CP5   0x00000020U

§ SCB_NSACR_CP5_M

#define SCB_NSACR_CP5_M   0x00000020U

§ SCB_NSACR_CP5_S

#define SCB_NSACR_CP5_S   5U

§ SCB_NSACR_CP4

#define SCB_NSACR_CP4   0x00000010U

§ SCB_NSACR_CP4_M

#define SCB_NSACR_CP4_M   0x00000010U

§ SCB_NSACR_CP4_S

#define SCB_NSACR_CP4_S   4U

§ SCB_NSACR_CP3

#define SCB_NSACR_CP3   0x00000008U

§ SCB_NSACR_CP3_M

#define SCB_NSACR_CP3_M   0x00000008U

§ SCB_NSACR_CP3_S

#define SCB_NSACR_CP3_S   3U

§ SCB_NSACR_CP2

#define SCB_NSACR_CP2   0x00000004U

§ SCB_NSACR_CP2_M

#define SCB_NSACR_CP2_M   0x00000004U

§ SCB_NSACR_CP2_S

#define SCB_NSACR_CP2_S   2U

§ SCB_NSACR_CP1

#define SCB_NSACR_CP1   0x00000002U

§ SCB_NSACR_CP1_M

#define SCB_NSACR_CP1_M   0x00000002U

§ SCB_NSACR_CP1_S

#define SCB_NSACR_CP1_S   1U

§ SCB_NSACR_CP0

#define SCB_NSACR_CP0   0x00000001U

§ SCB_NSACR_CP0_M

#define SCB_NSACR_CP0_M   0x00000001U

§ SCB_NSACR_CP0_S

#define SCB_NSACR_CP0_S   0U