Instance: EVTULL
Component: EVTULL
Base address: 0x40005000
This is top module of ULL Event Fabric
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RO |
32 |
0x3045 1010 |
0x0000 0000 |
0x4000 5000 |
|
RO |
32 |
0x0001 0106 |
0x0000 0004 |
0x4000 5004 |
|
RW |
32 |
0x0000 0000 |
0x0000 0064 |
0x4000 5064 |
|
RW |
32 |
0x0000 0000 |
0x0000 0400 |
0x4000 5400 |
|
RW |
32 |
0x0000 0000 |
0x0000 0404 |
0x4000 5404 |
|
RW |
32 |
0x0000 0000 |
0x0000 0800 |
0x4000 5800 |
Address Offset | 0x0000 0000 | ||
Physical Address | 0x4000 5000 | Instance | 0x4000 5000 |
Description | Description This register provides IP module ID, revision information, instance index and standard MMR registers offset. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:16 | MODID | Module identifier used to uniquely identify this IP. | RO | 0x3045 | ||
15:12 | STDIPOFF | Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB. 0: Standard IP MMRs do not exist 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address) |
RO | 0x1 | ||
11:8 | INSTIDX | IP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15). | RO | 0x0 | ||
7:4 | MAJREV | Major revision of IP (0-15). | RO | 0x1 | ||
3:0 | MINREV | Minor revision of IP (0-15). | RO | 0x0 |
Address Offset | 0x0000 0004 | ||
Physical Address | 0x4000 5004 | Instance | 0x4000 5004 |
Description | Extended Description This register provides configuration details of the IP to software drivers and end users. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:22 | IDMA | Number of DMA input channels | RO | 0b00 0000 0000 | ||
21:17 | NDMA | Number of DMA output channels | RO | 0b0 0000 | ||
16 | PD | Power Domain. 0 : SVT 1 : ULL |
RO | 1 | ||
15:8 | NSUB | Number of Subscribers | RO | 0x01 | ||
7:0 | NPUB | Number of Publishers | RO | 0x06 |
Address Offset | 0x0000 0064 | ||
Physical Address | 0x4000 5064 | Instance | 0x4000 5064 |
Description | Digital test bus control register This register can be used to bring out IP internal signals to the pads for observation. 16 signals can be observed per select value. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||
31:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b000 0000 0000 0000 0000 0000 0000 0000 | ||||||||
0 | SEL | Digital test bus selection mux control Non-zero select values output a 16 bit selected group of signals per value.
|
RW | 0 |
Address Offset | 0x0000 0400 | ||
Physical Address | 0x4000 5400 | Instance | 0x4000 5400 |
Description | Output Selection for CPU NMI Exception | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 0404 | ||
Physical Address | 0x4000 5404 | Instance | 0x4000 5404 |
Description | Output Selection for RTCCPT | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||||||||||||||||||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 0000 0000 0000 0000 0000 0000 | ||||||||||||||||||||||||||
5:0 | PUBID | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior.
|
RW | 0b00 0000 |
Address Offset | 0x0000 0800 | ||
Physical Address | 0x4000 5800 | Instance | 0x4000 5800 |
Description | WAKEUP Mask | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0x00 0000 | ||
7 | AON_IOC_COMB | Wake-up mask for AON_IOC_COMB. 0 - Wakeup Disabled 1 - Wakeup Enabled |
RW | 0 | ||
6 | AON_LPMCMP_IRQ | Wake-up mask for AON_LPMCMP_IRQ. 0 - Wakeup Disabled 1 - Wakeup Enabled |
RW | 0 | ||
5 | AON_DBG_COMB | Wake-up mask for AON_DBG_COMB. 0 - Wakeup Disabled 1 - Wakeup Enabled |
RW | 0 | ||
4 | AON_RTC_COMB | Wake-up mask for AON_RTC_COMB. 0 - Wakeup Disabled 1 - Wakeup Enabled |
RW | 0 | ||
3 | AON_CKM_COMB | Wake-up mask for AON_CKM_COMB. 0 - Wakeup Disabled 1 - Wakeup Enabled |
RW | 0 | ||
2 | AON_PMU_COMB | Wake-up mask for AON_PMU_COMB. 0 - Wakeup Disabled 1 - Wakeup Enabled |
RW | 0 | ||
1:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior | RO | 0b00 |
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