Instance: DBGSS
Component: DBGSS
Base address: 0x4000F000
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
RO |
32 |
0xB24D 1010 |
0x0000 0000 |
0x4000 F000 |
|
RW |
32 |
0x0000 0000 |
0x0000 0044 |
0x4000 F044 |
|
RO |
32 |
0x0000 0000 |
0x0000 004C |
0x4000 F04C |
|
RO |
32 |
0x0000 0000 |
0x0000 0054 |
0x4000 F054 |
|
WO |
32 |
0x0000 0000 |
0x0000 005C |
0x4000 F05C |
|
WO |
32 |
0x0000 0000 |
0x0000 0064 |
0x4000 F064 |
|
WO |
32 |
0x0000 0000 |
0x0000 006C |
0x4000 F06C |
|
WO |
32 |
0x0000 0000 |
0x0000 0074 |
0x4000 F074 |
|
RO |
32 |
0x0000 0000 |
0x0000 0100 |
0x4000 F100 |
|
RO |
32 |
0x0000 0000 |
0x0000 0104 |
0x4000 F104 |
|
RW |
32 |
0x0000 0000 |
0x0000 0108 |
0x4000 F108 |
|
RW |
32 |
0x0000 0000 |
0x0000 010C |
0x4000 F10C |
|
RO |
32 |
0x0000 0000 |
0x0000 0110 |
0x4000 F110 |
|
RO |
32 |
0x0000 0000 |
0x0000 0114 |
0x4000 F114 |
|
RO |
32 |
0x0000 0013 |
0x0000 0200 |
0x4000 F200 |
|
WO |
32 |
0x0000 0013 |
0x0000 0204 |
0x4000 F204 |
|
WO |
32 |
0x0000 0000 |
0x0000 0208 |
0x4000 F208 |
|
RO |
32 |
0x0000 0000 |
0x0000 0210 |
0x4000 F210 |
|
WO |
32 |
0x0000 0000 |
0x0000 0214 |
0x4000 F214 |
|
WO |
32 |
0x0000 0000 |
0x0000 0218 |
0x4000 F218 |
|
RW |
32 |
0x0000 0020 |
0x0000 021C |
0x4000 F21C |
Address Offset | 0x0000 0000 | ||
Physical Address | 0x4000 F000 | Instance | 0x4000 F000 |
Description | Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset. | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:16 | MODULEID | Module identifier used to uniquely identify this IP.
|
RW | 0xB24D | |||||||||||
15:12 | STDIPOFF | Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB. 0: Standard IP MMRs do not exist 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address) 0: STDIP MMRs do not exist 0x1-0xF: These MMRs begin at offset 64*STDIPOFF from IP base address
|
RW | 0x1 | |||||||||||
11:8 | INSTIDX | IP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15).
|
RW | 0x0 | |||||||||||
7:4 | MAJREV | Major revision of IP (0-15).
|
RW | 0x1 | |||||||||||
3:0 | MINREV | Minor revision of IP (0-15).
|
RW | 0x0 |
Address Offset | 0x0000 0044 | ||
Physical Address | 0x4000 F044 | Instance | 0x4000 F044 |
Description | Interrupt mask. This register selects interrupt sources which are allowed to pass from RIS to MIS when the corresponding bit-fields are set to 1. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | |||||||||||
3 | PWRDWNIFG | PWRDWNIFG interrupt mask
|
RW | 0 | |||||||||||
2 | PWRUPIFG | PWRUPIFG interrupt mask
|
RW | 0 | |||||||||||
1 | RXIFG | RXIFG interrupt mask
|
RW | 0 | |||||||||||
0 | TXIFG | TXIFG interrupt mask
|
RW | 0 |
Address Offset | 0x0000 004C | ||
Physical Address | 0x4000 F04C | Instance | 0x4000 F04C |
Description | Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit. | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | |||||||||||
3 | PWRDWNIFG | Raw interrupt status for PWRDWNIFG
|
RW | 0 | |||||||||||
2 | PWRUPIFG | Raw interrupt status for PWRUPIFG
|
RW | 0 | |||||||||||
1 | RXIFG | Raw interrupt status for RXIFG
|
RW | 0 | |||||||||||
0 | TXIFG | Raw interrupt status for TXIFG
|
RW | 0 |
Address Offset | 0x0000 0054 | ||
Physical Address | 0x4000 F054 | Instance | 0x4000 F054 |
Description | Masked interrupt status. This register is simply a bitwise AND of the contents of IMASK and RIS registers. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit. | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | |||||||||||
3 | PWRDWNIFG | Masked interrupt status for PWRDWNIFG
|
RW | 0 | |||||||||||
2 | PWRUPIFG | Masked interrupt status for PWRUPIFG
|
RW | 0 | |||||||||||
1 | RXIFG | Masked interrupt status for RXIFG
|
RW | 0 | |||||||||||
0 | TXIFG | Masked interrupt status for TXIFG
|
RW | 0 |
Address Offset | 0x0000 005C | ||
Physical Address | 0x4000 F05C | Instance | 0x4000 F05C |
Description | Interrupt set register. This register can be used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set. | ||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | |||||||||||
3 | PWRDWNIFG | Sets PWRDWNIFG in RIS register
|
RW | 0 | |||||||||||
2 | PWRUPIFG | Sets PWRUPIFG in RIS register
|
RW | 0 | |||||||||||
1 | RXIFG | Sets RXIFG in RIS register
|
RW | 0 | |||||||||||
0 | TXIFG | Sets TXIFG in RIS register
|
RW | 0 |
Address Offset | 0x0000 0064 | ||
Physical Address | 0x4000 F064 | Instance | 0x4000 F064 |
Description | Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding RIS bit also gets cleared. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets cleared. | ||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | |||||||||||
3 | PWRDWNIFG | Clears PWRDWNIFG interrupt
|
RW | 0 | |||||||||||
2 | PWRUPIFG | Clears PWRUPIFG interrupt
|
RW | 0 | |||||||||||
1 | RXIFG | Clears RXIFG interrupt
|
RW | 0 | |||||||||||
0 | TXIFG | Clears TXIFG interrupt
|
RW | 0 |
Address Offset | 0x0000 006C | ||
Physical Address | 0x4000 F06C | Instance | 0x4000 F06C |
Description | Interrupt mask set register. Writing a 1 to a bit in this register will set the corresponding IMASK bit. | ||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | |||||||||||
3 | PWRDWNIFG | Set PWRDWNIFG interrupt mask
|
RW | 0 | |||||||||||
2 | PWRUPIFG | Set PWRUPIFG interrupt mask
|
RW | 0 | |||||||||||
1 | RXIFG | Set RXIFG interrupt mask
|
RW | 0 | |||||||||||
0 | TXIFG | Set TXIFG interrupt mask
|
RW | 0 |
Address Offset | 0x0000 0074 | ||
Physical Address | 0x4000 F074 | Instance | 0x4000 F074 |
Description | Interrupt mask clear register. Writing a 1 to a bit in this register will clear the corresponding IMASK bit. | ||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:4 | RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 0000 | |||||||||||
3 | PWRDWNIFG | Clears PWRDWNIFG interrupt mask
|
RW | 0 | |||||||||||
2 | PWRUPIFG | Clears PWRUPIFG interrupt mask
|
RW | 0 | |||||||||||
1 | RXIFG | Clears RXIFG interrupt mask
|
RW | 0 | |||||||||||
0 | TXIFG | Clears TXIFG interrupt mask
|
RW | 0 |
Address Offset | 0x0000 0100 | ||
Physical Address | 0x4000 F100 | Instance | 0x4000 F100 |
Description | Transmit data register. This register is used for sending SACI (SECAP command interface) data from the host to the device. The host (SWD interface) can write this register. This updates the value of TXD, and sets TXCTL.TXDSTA = FULL The host should only write TXD while TXCTL.TXDSTA = EMPTY. If the host incorrectly writes TXD while TXCTL.TXDSTA = FULL, this will just update the value of TXD. The host (SWD interface) can read the TXD register. This does not affect TXCTL.TXDSTA. The device (boot code) can only read the TXD register. This sets TXCTL.TXDSTA = EMPTY. The device should only read TXD while TXCTL.TXDSTA = FULL. If the device incorrectly reads TXD while TXCTL.TXDSTA = EMPTY, this will just return the value of TXD. If the host writes TXD on the same clock cycle as the device reads TXD: The device reads the old TXD value. TXD is updated with the new value, and TXCTL.TXDSTA is set to FULL. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | VAL | SACI command/parameter word. Valid value when TXCTL.TXDSTA=1. TXCTL.TXDSTA gets automatically cleared upon read. | RO | 0x0000 0000 |
Address Offset | 0x0000 0104 | ||
Physical Address | 0x4000 F104 | Instance | 0x4000 F104 |
Description | Transmit control register. This register contains status of the TXD register (full/empty), and also software defined flags that are used by the SACI protocol. The host (SWD interface) can write the FLAGS field of the TXCTL register. The host (SWD interface) can read the TXCTL register. The device (boot code) can only read the TXCTL register. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||
7:1 | FLAGS | Software defined flags that are used by the SACI protocol (host to device). | RO | 0b000 0000 | |||||||||||
0 | TXDSTA | Indicates whether the host has written a word to the TXD register, which can be read by the device: TXDSTA is automatically set upon write to TXD register in SECAP and automatically gets cleared upon read from TXD
|
RO | 0 |
Address Offset | 0x0000 0108 | ||
Physical Address | 0x4000 F108 | Instance | 0x4000 F108 |
Description | Receive data register. This register is used to send SACI command response data from the device to the host. The device (boot code) can write the RXD register. This updates the value of RXD, and sets RXCTL.RXDSTA = FULL. The device should only write RXD while RXCTL.RXDSTA = EMPTY. If the device incorrectly writes RXD while RXCTL.RXDSTA = FULL, this will just update the value of RXD. The device (boot code) can read the RXD register in order to flush it. This sets RXCTL.RXDSTA = EMPTY. The host (SWD interface) can only read the RXD register. This sets RXCTL.RXDSTA = EMPTY. The host should only read RXD while RXCTL.RXDSTA = FULL. If the host incorrectly reads RXD while RXCTL.RXDSTA = EMPTY, this will just return the value of RXD. If the device writes RXD on the same clock cycle as the host reads RXD: The host reads the old RXD value. RXD is updated with the new value, and RXCTL.RXDSTA is set to FULL. |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | ||
31:0 | VAL | SACI command response word. RXCTL.RXDSTA automatically set upon write. RXCTL.RXDSTA automatically cleared upon read (flush operation). | RW | 0x0000 0000 |
Address Offset | 0x0000 010C | ||
Physical Address | 0x4000 F10C | Instance | 0x4000 F10C |
Description | Receive control register. This register contains status of the RXD register (full/empty), and also software defined flags that are used by the SACI protocol. The device (boot code) can write the FLAGS field of the RXCTL register. The device (boot code) can read the RXCTL register. The host (SWD interface) can only read the RXCTL register |
||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:8 | RESERVED8 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x00 0000 | |||||||||||
7:1 | FLAGS | Software defined flags that are used by the SACI protocol (device to host). | RW | 0b000 0000 | |||||||||||
0 | RXDSTA | Indicates whether the device has written a word to the RXD register, which can be read by the host: RXDSTA is automatically set upon write to RXD and automatically cleared upon read from RXD register of SECAP or RXD.
|
RO | 0 |
Address Offset | 0x0000 0110 | ||
Physical Address | 0x4000 F110 | Instance | 0x4000 F110 |
Description | Transmit data peek register . This register is a read-only version of the TXD register that can be read by host and device without any side-effects. This register is used to peek at the values in TXD without affecting the FULL/EMPTY flag. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | VAL | Transmit Data Peek Register. SACI command parameter word. TXCTL.TXDSTA not affected by read of TXDPEEK | RO | 0x0000 0000 |
Address Offset | 0x0000 0114 | ||
Physical Address | 0x4000 F114 | Instance | 0x4000 F114 |
Description | Receive data peek register. The RXDPEEK register is a read-only version of the RXD register that can be read by host and device without any side-effects This register is used to peek at the values in Receive Data Register without affecting the FULL/EMPTY flag. |
||
Type | RO |
Bits | Field Name | Description | Type | Reset | ||
31:0 | VAL | Receive Data Peek Register. SACI command response word. RXCTL.RXDSTA not affected by read of RXDPEEK | RO | 0x0000 0000 |
Address Offset | 0x0000 0200 | ||
Physical Address | 0x4000 F200 | Instance | 0x4000 F200 |
Description | This register indicates the status of different AP firewalls. | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 0000 0000 | |||||||||||
6 | DBGDIS | Indicates status of DBGDIS.
|
RO | 0 | |||||||||||
5 | AHBAPEN | Indicates status of AHBAPEN
|
RO | 0 | |||||||||||
4 | CFGAPEN | Indicates status of CFGAPEN
|
RO | 1 | |||||||||||
3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
2 | DFTAPEN | Indicates status of DFTAPEN
|
RO | 0 | |||||||||||
1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 1 | |||||||||||
0 | SECAPEN | Indicates status of SECAP
|
RO | 1 |
Address Offset | 0x0000 0204 | ||
Physical Address | 0x4000 F204 | Instance | 0x4000 F204 |
Description | This register is used for setting bits in SPECIAL_AUTH register. This register is configured and locked during device boot. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:24 | KEY | This field must be configured with 0xA5 in order to access this register.
|
WO | 0x00 | |||||||||||
23:7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 | |||||||||||
6 | DBGDIS | This bit sets DBGDIS in SPECIAL_AUTH register.
|
WO | 0 | |||||||||||
5 | AHBAPEN | This bit sets AHBAPEN in SPECIAL_AUTH register.
|
WO | 0 | |||||||||||
4 | CFGAPEN | This bit sets CFGAPEN in SPECIAL_AUTH register.
|
WO | 1 | |||||||||||
3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | WO | 0 | |||||||||||
2 | DFTAPEN | This bit sets DFTAPEN in SPECIAL_AUTH register.
|
WO | 0 | |||||||||||
1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | WO | 1 | |||||||||||
0 | SECAPEN | This bit sets SECAPEN bit in SPECIAL_AUTH register.
|
WO | 1 |
Address Offset | 0x0000 0208 | ||
Physical Address | 0x4000 F208 | Instance | 0x4000 F208 |
Description | This register is used for clearing bits in SPECIAL_AUTH register. This register is configured and locked during device boot. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:24 | KEY | This field must be configured with 0x22 in order to access this register.
|
WO | 0x00 | |||||||||||
23:7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 0000 0000 | |||||||||||
6 | DBGDIS | This bit clears DBGDIS in SPECIAL_AUTH register.
|
WO | 0 | |||||||||||
5 | AHBAPEN | This bit clears AHBAPEN in SPECIAL_AUTH register.
|
WO | 0 | |||||||||||
4 | CFGAPEN | This bit clears CFGAPEN in SPECIAL_AUTH register.
|
WO | 0 | |||||||||||
3 | RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | WO | 0 | |||||||||||
2 | DFTAPEN | This bit clears DFTAPEN in SPECIAL_AUTH register.
|
WO | 0 | |||||||||||
1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | WO | 0 | |||||||||||
0 | SECAPEN | This bit clears SECAPEN in SPECIAL_AUTH register.
|
WO | 0 |
Address Offset | 0x0000 0210 | ||
Physical Address | 0x4000 F210 | Instance | 0x4000 F210 |
Description | This register indicates the debug privileges of ARM Cortex CPU. | ||
Type | RO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 0000 | |||||||||||
1 | NIDEN | Controls non-invasive debug enable.
|
RO | 0 | |||||||||||
0 | DBGEN | Controls invasive debug enable.
|
RO | 0 |
Address Offset | 0x0000 0214 | ||
Physical Address | 0x4000 F214 | Instance | 0x4000 F214 |
Description | This register is used for setting bits in APP_AUTH register. This register is configured and locked during device boot. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:24 | KEY | This field must be configured with 0x39 in order to access this register.
|
WO | 0x00 | |||||||||||
23:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b00 0000 0000 0000 0000 0000 | |||||||||||
1 | NIDEN | Sets NIDEN bit in [APP_AUTH ]register.
|
WO | 0 | |||||||||||
0 | DBGEN | Sets DBGEN bit in APP_AUTH register.
|
WO | 0 |
Address Offset | 0x0000 0218 | ||
Physical Address | 0x4000 F218 | Instance | 0x4000 F218 |
Description | This register is used for clearing bits in APP_AUTH register. This register is configured and locked during device boot. |
||
Type | WO |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:24 | KEY | This field must be configured with 0x7D in order to access this register.
|
WO | 0x00 | |||||||||||
23:2 | RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RW | 0b00 0000 0000 0000 0000 0000 | |||||||||||
1 | NIDEN | Clears NIDEN bit in APP_AUTH register.
|
WO | 0 | |||||||||||
0 | DBGEN | Clears DBGEN bit in APP_AUTH register.
|
WO | 0 |
Address Offset | 0x0000 021C | ||
Physical Address | 0x4000 F21C | Instance | 0x4000 F21C |
Description | Debug control register. This register is used for controlling debug connection and read out debug status. | ||
Type | RW |
Bits | Field Name | Description | Type | Reset | |||||||||||
31:6 | RESERVED6 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 0000 0000 0000 0000 0000 0000 | |||||||||||
5 | SWDCEN | This bit is used to enable connection between SWD pads and IceMelter (wakeup circuit used for detecting debug probe)
|
RW | 1 | |||||||||||
4 | DBGPWRUPACK | This bit field specifies the status of dbgpwrupack from pmctl.
|
RO | 0 | |||||||||||
3 | SYSPWRUPACK | This bit field specify the status of syspwrupack from pmctl.
|
RO | 0 | |||||||||||
2 | JTAGSEL | This bit field specifies the status of JTAG MODE for TEST TAP.
|
RO | 0 | |||||||||||
1 | SWDSEL | This bit field specifies the status of SWD MODE for connection.
|
RO | 0 | |||||||||||
0 | SWDOVR | This bit is used for connecting to IO pads to SWCLK/IO on SW-DP through a software request and establish SWD connection without IceMelter trigger for debug purpose.
|
RW | 0 |
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