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Structure for MCAN Message RAM Configuration Parameters. Message RAM can contain following sections: Standard ID filters, Extended ID filters, RX FIFO0, RX FIFO1, RX Buffers, TX EventFIFO, TX Buffers, TX FIFO (or TX Q) More...
#include <MCAN.h>
Data Fields | |
| uint32_t | sidFilterStartAddr |
| uint32_t | sidFilterListSize |
| uint32_t | xidFilterStartAddr |
| uint32_t | xidFilterListSize |
| uint32_t | rxFIFO0StartAddr |
| uint32_t | rxFIFO0Size |
| uint32_t | rxFIFO0Watermark |
| uint32_t | rxFIFO0OpMode |
| uint32_t | rxFIFO1StartAddr |
| uint32_t | rxFIFO1Size |
| uint32_t | rxFIFO1Watermark |
| uint32_t | rxFIFO1OpMode |
| uint32_t | rxBufStartAddr |
| uint32_t | rxBufElemSize |
| uint32_t | rxFIFO0ElemSize |
| uint32_t | rxFIFO1ElemSize |
| uint32_t | txEventFIFOStartAddr |
| uint32_t | txEventFIFOSize |
| uint32_t | txEventFIFOWatermark |
| uint32_t | txBufStartAddr |
| uint32_t | txBufNum |
| uint32_t | txFIFOQSize |
| uint32_t | txFIFOQMode |
| uint32_t | txBufElemSize |
Structure for MCAN Message RAM Configuration Parameters. Message RAM can contain following sections: Standard ID filters, Extended ID filters, RX FIFO0, RX FIFO1, RX Buffers, TX EventFIFO, TX Buffers, TX FIFO (or TX Q)
Note: If particular section in the RAM is not used then it's size should be initialized to '0' (Number of buffers in case of Tx/Rx buffer).
| uint32_t MCAN_MsgRAMConfig::sidFilterStartAddr |
Standard ID Filter List Start Address
| uint32_t MCAN_MsgRAMConfig::sidFilterListSize |
List Size: Standard ID 0 = No standard Message ID filter 1-128 = Number of standard Message ID filter elements
| uint32_t MCAN_MsgRAMConfig::xidFilterStartAddr |
Extended ID Filter List Start Address
| uint32_t MCAN_MsgRAMConfig::xidFilterListSize |
List Size: Extended ID 0 = No standard Message ID filter 1-64 = Number of standard Message ID filter elements
| uint32_t MCAN_MsgRAMConfig::rxFIFO0StartAddr |
Rx FIFO0 Start Address
| uint32_t MCAN_MsgRAMConfig::rxFIFO0Size |
Rx FIFO0 Size 0 = No Rx FIFO 1-64 = Number of Rx FIFO elements
| uint32_t MCAN_MsgRAMConfig::rxFIFO0Watermark |
Rx FIFO0 Watermark 0 = Watermark interrupt disabled 1-64 = Level for Rx FIFO 0 watermark interrupt
| uint32_t MCAN_MsgRAMConfig::rxFIFO0OpMode |
Rx FIFO0 Operation Mode 0 = FIFO blocking mode 1 = FIFO overwrite mode
| uint32_t MCAN_MsgRAMConfig::rxFIFO1StartAddr |
Rx FIFO1 Start Address
| uint32_t MCAN_MsgRAMConfig::rxFIFO1Size |
Rx FIFO1 Size 0 = No Rx FIFO 1-64 = Number of Rx FIFO elements
| uint32_t MCAN_MsgRAMConfig::rxFIFO1Watermark |
Rx FIFO1 Watermark 0 = Watermark interrupt disabled 1-64 = Level for Rx FIFO 1 watermark interrupt
| uint32_t MCAN_MsgRAMConfig::rxFIFO1OpMode |
Rx FIFO1 Operation Mode 0 = FIFO blocking mode 1 = FIFO overwrite mode
| uint32_t MCAN_MsgRAMConfig::rxBufStartAddr |
Rx Buffer Start Address
| uint32_t MCAN_MsgRAMConfig::rxBufElemSize |
Rx Buffer Element Size
| uint32_t MCAN_MsgRAMConfig::rxFIFO0ElemSize |
Rx FIFO0 Element Size
| uint32_t MCAN_MsgRAMConfig::rxFIFO1ElemSize |
Rx FIFO1 Element Size
| uint32_t MCAN_MsgRAMConfig::txEventFIFOStartAddr |
Tx Event FIFO Start Address
| uint32_t MCAN_MsgRAMConfig::txEventFIFOSize |
Event FIFO Size 0 = Tx Event FIFO disabled 1-32 = Number of Tx Event FIFO elements
| uint32_t MCAN_MsgRAMConfig::txEventFIFOWatermark |
Tx Event FIFO Watermark 0 = Watermark interrupt disabled 1-32 = Level for Tx Event FIFO watermark interrupt
| uint32_t MCAN_MsgRAMConfig::txBufStartAddr |
Tx Buffers Start Address
| uint32_t MCAN_MsgRAMConfig::txBufNum |
Number of Dedicated Transmit Buffers 0 = No Dedicated Tx Buffers 1-32 = Number of Dedicated Tx Buffers
| uint32_t MCAN_MsgRAMConfig::txFIFOQSize |
Transmit FIFO/Queue Size 0 = No Tx FIFO/Queue 1-32 = Number of Tx Buffers used for Tx FIFO/Queue
| uint32_t MCAN_MsgRAMConfig::txFIFOQMode |
Tx FIFO/Queue Mode 0 = Tx FIFO operation 1 = Tx Queue operation
| uint32_t MCAN_MsgRAMConfig::txBufElemSize |
Tx Buffer Element Size