AESCTRLPF3.h

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/*
 * Copyright (c) 2021-2023, Texas Instruments Incorporated
 * All rights reserved.
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 * *  Redistributions in binary form must reproduce the above copyright
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 *    documentation and/or other materials provided with the distribution.
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 *    from this software without specific prior written permission.
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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 */
#ifndef ti_drivers_aesctr_AESCTRLPF3__include
#define ti_drivers_aesctr_AESCTRLPF3__include

#include <stdbool.h>
#include <stdint.h>

#include <ti/drivers/AESCTR.h>
#include <ti/drivers/cryptoutils/aes/AESCommonLPF3.h>
#include <ti/drivers/cryptoutils/sharedresources/CryptoResourceLPF3.h>

#include <ti/devices/DeviceFamily.h>
#include DeviceFamily_constructPath(driverlib/aes.h)

#ifdef __cplusplus
extern "C" {
#endif

/*
 * Default AES CTR auto config:
 *  ECB SRC as BUF
 *  Trigger points for auto ECB as RDTX3 and WRBUF3S
 *   (the first encryption starts by writing BUF3, the successive ones by reading TXT3)
 *  Counter size as 128-bits
 *  Counter endianness as Big Endian
 *  BUSHALT enabled
 */
#define AESCTRLPF3_DEFAULT_AUTOCFG                                                                                   \
    ((uint32_t)AES_AUTOCFG_ECBSRC_BUF | (uint32_t)AES_AUTOCFG_TRGECB_WRBUF3S | (uint32_t)AES_AUTOCFG_TRGECB_RDTXT3 | \
     (uint32_t)AES_AUTOCFG_CTRSIZE_CTR128 | (uint32_t)AES_AUTOCFG_CTRENDN_BIGENDIAN |                                \
     (uint32_t)AES_AUTOCFG_BUSHALT_EN)

/*
 * AES CTR auto config for handling processing of the last
 * block of input to avoid starting encryption of the next counter block and
 * incrementing the counter value when the output is read from TXT3.
 *
 *  ECB SRC as BUF
 *  Trigger for auto ECB as WRBUF3S
 *   (the first encryption starts by writing BUF3)
 *  Counter size as 128-bits
 *  Counter endianness as Big Endian
 */
#define AESCTRLPF3_LAST_BLOCK_AUTOCFG                                                                                 \
    ((uint32_t)AES_AUTOCFG_ECBSRC_BUF | (uint32_t)AES_AUTOCFG_TRGECB_WRBUF3S | (uint32_t)AES_AUTOCFG_CTRSIZE_CTR128 | \
     (uint32_t)AES_AUTOCFG_CTRENDN_BIGENDIAN | (uint32_t)AES_AUTOCFG_BUSHALT_EN)

typedef AESCommonLPF3_HWAttrs AESCTRLPF3_HWAttrs;

typedef struct
{
    /* Common member first to allow struct to be cast to the common type */
    AESCommonLPF3_Object common;
    volatile uint32_t counter[AES_BLOCK_SIZE_WORDS];
    const uint8_t *input;
    uint8_t *output;
    size_t inputLength;
    size_t inputLengthRemaining;
    AESCTR_OperationUnion *operation;
    AESCTR_CallbackFxn callbackFxn;
    AESCTR_OperationType operationType;
    bool threadSafe;
} AESCTRLPF3_Object;

void AESCTRLPF3_processData(const uint8_t *input, uint8_t *output, size_t inputLength, bool isOneStepOrFinalOperation);

size_t AESCTRLPF3_configDataDMA(AESCommonLPF3_Object *object,
                                const uint8_t *input,
                                uint8_t *output,
                                size_t inputLength);

__STATIC_INLINE void AESCTRLPF3_readCounter(uint32_t counterOut[AES_BLOCK_SIZE_WORDS])
{
    /* Read the latest counter value from the AES engine */
    AESReadBUF32(&counterOut[0]);
}

__STATIC_INLINE void AESCTRLPF3_writeCounter(uint32_t counterIn[AES_BLOCK_SIZE_WORDS])
{
    AESWriteBUF32(&counterIn[0]);
}

__STATIC_INLINE bool AESCTR_acquireLock(AESCTR_Handle handle, uint32_t timeout)
{
    return CryptoResourceLPF3_acquireLock(timeout);
}
__STATIC_INLINE void AESCTR_releaseLock(AESCTR_Handle handle)
{
    CryptoResourceLPF3_releaseLock();
}
__STATIC_INLINE void AESCTR_enableThreadSafety(AESCTR_Handle handle)
{
    AESCTRLPF3_Object *object = handle->object;
    object->threadSafe        = true;
}
__STATIC_INLINE void AESCTR_disableThreadSafety(AESCTR_Handle handle)
{
    AESCTRLPF3_Object *object = handle->object;
    object->threadSafe        = false;
}
#ifdef __cplusplus
}
#endif

#endif /* ti_drivers_aesctr_AESCTRLPF3__include */