VIMS

Instance: VIMS
Component: VIMS
Base address: 0x40024000


VIMS (Versatile Instruction Memory System)
All registers in this module are retained, unless explicitely mentioned.

TOP:VIMS Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

DESC

RO

32

0xD140 0010

0x0000 0000

0x4002 4000

DESCEX

RO

32

0x08FF B000

0x0000 0004

0x4002 4004

FLWS1T

RW

32

0x0000 0007

0x0000 0008

0x4002 4008

FLWS2T

RW

32

0x0000 0007

0x0000 000C

0x4002 400C

PTRMC0

RW

32

0x131A 0000

0x0000 0018

0x4002 4018

B0TRMC1

RW

32

0x0000 0000

0x0000 001C

0x4002 401C

B0TRMC0

RW

32

0x0000 0000

0x0000 0020

0x4002 4020

FLBLCK

RW

32

0x0000 0000

0x0000 0100

0x4002 4100

CFG

RW

32

0x0000 0001

0x0000 03FC

0x4002 43FC

RDPRMN

RW

32

0x0000 0007

0x0000 0400

0x4002 4400

RDPRNMN

RW

32

0x0000 003F

0x0000 0404

0x4002 4404

RDPRTRM

RW

32

0x0000 003F

0x0000 0408

0x4002 4408

RDPREGR

RW

32

0x0000 0001

0x0000 040C

0x4002 440C

WEPRA

RW

32

0xFFFF FFFF

0x0000 0410

0x4002 4410

WEPRB

RW

32

0x0FFF FFFF

0x0000 0414

0x4002 4414

WEPRAUX

RW

32

0x0000 0007

0x0000 041C

0x4002 441C

FLBSTAT

RO

32

0x0000 0000

0x0000 0420

0x4002 4420

CCHCTRL

RW

32

0x0000 0007

0x0000 0424

0x4002 4424

DTB

RW

32

0x0000 0000

0x0000 0800

0x4002 4800

TOP:VIMS Register Descriptions

TOP:VIMS:DESC

Address Offset 0x0000 0000
Physical Address 0x4002 4000 Instance 0x4002 4000
Description Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset.
Type RO
Bits Field Name Description Type Reset
31:16 MODID Module identifier used to uniquely identify this IP. RO 0xD140
15:12 STDIPOFF Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB.

0: Standard IP MMRs do not exist

0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address)		 RO 0x0
11:8 INSTIDX IP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15). RO 0x0
7:4 MAJREV Major revision of IP (0-15). RO 0x1
3:0 MINREV Minor revision of IP (0-15). RO 0x0

TOP:VIMS:DESCEX

Address Offset 0x0000 0004
Physical Address 0x4002 4004 Instance 0x4002 4004
Description Extended Description Register. This register provides configuration details of the IP to software drivers and end users.
Type RO
Bits Field Name Description Type Reset
31:28 RESERVED28 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0
27 NBANK Provides the FLASH Bank count RO 1
26:15 FLSZ This provides the total FLASH size in Kilo Bytes. The total FLASH size is (FLSZ + 1)KB RO 0x1FF
14:0 ROMSZ Provides the size of ROM in Bytes. RO 0b011 0000 0000 0000

TOP:VIMS:FLWS1T

Address Offset 0x0000 0008
Physical Address 0x4002 4008 Instance 0x4002 4008
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Internal. Only to be used through TI provided API. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2:0 VAL Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 WS0 Internal. Only to be used through TI provided API.
0x1 WS1 Internal. Only to be used through TI provided API.
0x2 WS2 Internal. Only to be used through TI provided API.
0x3 WS3 Internal. Only to be used through TI provided API.
0x4 WS4 Internal. Only to be used through TI provided API.
0x5 WS5 Internal. Only to be used through TI provided API.
0x6 WS6 Internal. Only to be used through TI provided API.
0x7 WS7 Internal. Only to be used through TI provided API.
RW 0b111

TOP:VIMS:FLWS2T

Address Offset 0x0000 000C
Physical Address 0x4002 400C Instance 0x4002 400C
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Internal. Only to be used through TI provided API. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2:0 VAL Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 WS0 Internal. Only to be used through TI provided API.
0x1 WS1 Internal. Only to be used through TI provided API.
0x2 WS2 Internal. Only to be used through TI provided API.
0x3 WS3 Internal. Only to be used through TI provided API.
0x4 WS4 Internal. Only to be used through TI provided API.
0x5 WS5 Internal. Only to be used through TI provided API.
0x6 WS6 Internal. Only to be used through TI provided API.
0x7 WS7 Internal. Only to be used through TI provided API.
RW 0b111

TOP:VIMS:PTRMC0

Address Offset 0x0000 0018
Physical Address 0x4002 4018 Instance 0x4002 4018
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:0 VAL Internal. Only to be used through TI provided API. RW 0x131A 0000

TOP:VIMS:B0TRMC1

Address Offset 0x0000 001C
Physical Address 0x4002 401C Instance 0x4002 401C
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:0 VAL Internal. Only to be used through TI provided API. RW 0x0000 0000

TOP:VIMS:B0TRMC0

Address Offset 0x0000 0020
Physical Address 0x4002 4020 Instance 0x4002 4020
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:0 VAL Internal. Only to be used through TI provided API. RW 0x0000 0000

TOP:VIMS:FLBLCK

Address Offset 0x0000 0100
Physical Address 0x4002 4100 Instance 0x4002 4100
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Internal. Only to be used through TI provided API. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 VAL Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 ALLOW Internal. Only to be used through TI provided API.
0x1 BLOCK Internal. Only to be used through TI provided API.
RW 0

TOP:VIMS:CFG

Address Offset 0x0000 03FC
Physical Address 0x4002 43FC Instance 0x4002 43FC
Description Internal. Only to be used through TI provided API.
Type RW
Bits Field Name Description Type Reset
31:2 RESERVED2 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RW 0b00 0000 0000 0000 0000 0000 0000 0000
1 TRMVLID Internal. Only to be used through TI provided API. RW 0
0 WEPRTRM Internal. Only to be used through TI provided API.
Value ENUM Name Description
0x0 RESTRICT Internal. Only to be used through TI provided API.
0x1 ALLOW Internal. Only to be used through TI provided API.
RW 1

TOP:VIMS:RDPRMN

Address Offset 0x0000 0400
Physical Address 0x4002 4400 Instance 0x4002 4400
Description Flash main region read protection register upto first 8KB. This register is sticky when written with value 0.
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2:0 VAL Flash read protection configuration value. RW 0b111

TOP:VIMS:RDPRNMN

Address Offset 0x0000 0404
Physical Address 0x4002 4404 Instance 0x4002 4404
Description Flash non main region read protection register for last 512 B. This register is sticky when written with value 0.
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000
5:0 VAL Flash read protection configuration value. RW 0b11 1111

TOP:VIMS:RDPRTRM

Address Offset 0x0000 0408
Physical Address 0x4002 4408 Instance 0x4002 4408
Description Flash trim region read protection register for last 512 B. This register is sticky when written with value 0.
Type RW
Bits Field Name Description Type Reset
31:6 RESERVED6 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b00 0000 0000 0000 0000 0000 0000
5:0 VAL Flash read protection configuration value. RW 0b11 1111

TOP:VIMS:RDPREGR

Address Offset 0x0000 040C
Physical Address 0x4002 440C Instance 0x4002 440C
Description Flash engr region read protection register. This register is sticky when written with value 0.
Type RW
Bits Field Name Description Type Reset
31:1 RESERVED1 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b000 0000 0000 0000 0000 0000 0000 0000
0 VAL Flash read protection configuration value. RW 1

TOP:VIMS:WEPRA

Address Offset 0x0000 0410
Physical Address 0x4002 4410 Instance 0x4002 4410
Description Flash main region write/erase protection for first 32 sectors. Nth bit corresponds to the Nth sector. This register is sticky when written with value 0.
Type RW
Bits Field Name Description Type Reset
31:0 VAL Flash write/erase protection configuration value. RW 0xFFFF FFFF

TOP:VIMS:WEPRB

Address Offset 0x0000 0414
Physical Address 0x4002 4414 Instance 0x4002 4414
Description Flash main region write/erase protection for remaining sectors. Each bit corresponds to 8 sectors. Bit 0 corresponds to sector 32-39, bit 1 corresponds to sector 40-47 and so on. This register is sticky when written with value 0.
Type RW
Bits Field Name Description Type Reset
31:28 RESERVED28 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x0
27:0 VAL Flash write/erase protection configuration value. RW 0xFFF FFFF

TOP:VIMS:WEPRAUX

Address Offset 0x0000 041C
Physical Address 0x4002 441C Instance 0x4002 441C
Description Flash Write/Erase protection for Non-Main, TRIM and ENGR Regions. This register is sticky when written with value 0.
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2 WEPREGR Flash engr region write/erase protection configuration value. RW 1
1 WEPRTRM Flash trim region write/erase protection configuration value. RW 1
0 WEPRNMN Flash non main region write/erase protection configuration value. RW 1

TOP:VIMS:FLBSTAT

Address Offset 0x0000 0420
Physical Address 0x4002 4420 Instance 0x4002 4420
Description This register is used to indicate status of flash. This register is not retained.
Type RO
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3 PARERR This bit indicates parity error on write/erase and read protection MMRs. This bit is sticky when set to 1 by hardware.
Value ENUM Name Description
0x0 NOERROR No Error
0x1 ERROR Error
RO 0
2 B0BSY This bit indicates if flash is busy.
Value ENUM Name Description
0x0 IDLE Idle
0x1 BUSY Busy
RO 0
1 B2TRDY This bit indicates if flash is ready in 2T mode.
Value ENUM Name Description
0x0 NOTREADY Not Ready
0x1 READY Ready
RO 0
0 B1TRDY This bit indicates if flash is ready in 1T mode.
Value ENUM Name Description
0x0 NOTREADY Not Ready
0x1 READY Ready
RO 0

TOP:VIMS:CCHCTRL

Address Offset 0x0000 0424
Physical Address 0x4002 4424 Instance 0x4002 4424
Description This register is used for enabling cache, prefetch and micropredictor units.
Type RW
Bits Field Name Description Type Reset
31:3 RESERVED3 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0b0 0000 0000 0000 0000 0000 0000 0000
2 CCHMPEN This bit is used to enable the micropredictor unit.
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 1
1 CCHPFEN This bit is used to enable the prefetch unit.
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 1
0 CCHEN This bit is used to enable the cache.
Value ENUM Name Description
0x0 DIS Disable
0x1 EN Enable
RW 1

TOP:VIMS:DTB

Address Offset 0x0000 0800
Physical Address 0x4002 4800 Instance 0x4002 4800
Description Digital test bus control register. This register can be used to bring out IP internal signals to the pads for observation. 16 signals can be observed per select value.
Type RW
Bits Field Name Description Type Reset
31:4 RESERVED4 Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. RO 0x000 0000
3:0 SEL DTB MUX select pin value
Value ENUM Name Description
0x0 DIS DTB output from peripheral is 0x0.
RW 0x0


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